DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guidash et al. (U.S. Patent Application Publication 2015022985).
[The following rejection coincides, at least in part with the Written Opinion dated 06/03/25].
U.S. Patent Application Publication 20150229859
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Abstract
A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.
As per claim 1, Guidash et al. disclose a method comprising the step(s) of:
applying a first pulse (TG) to a first gate line of a plurality of gate lines of an imaging array;
applying a second pulse (Null) while applying the first pulse, the second pulse having a polarity opposite to the first pulse.
sampling pixels coupled to the first gate line while applying the first pulse using sampling circuits.
[Examiner note: Examiner equates photocharge transfer [0080;0081] and reading out [0078] as analogous to sampling (measuring pixel values at specific intervals)]
Guidash et al. do not explicitly disclose
applying a second pulse to other gate lines of the plurality of gate lines
Guidash et al. teach however, applying a second pulse (Null) in order to reduce capacitive feedthrough effects (noise) during pixel readout (see for example, Abstract above).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the method of Guidash et al. such that it applied a second pulse to other gate lines of the plurality of gate lines. One would have been motivated to make such a modification for the purpose of reducing capacitive feedback during pixel readout as suggested by Guidash et al. (see for example, Abstract above).
As per claims 2-3, Guidash et al. as modified, disclose a method as recited in claim 1, but do not explicitly disclose a method further comprising: resetting the sampling circuits and before applying the first pulse. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the method of Guidash et al. such that it incorporated the step of resetting the sampling circuits and before applying the first pulse. One would have been motivated to make such a modification for the purpose of accurately capturing a new input signal without interference from previous readings, as is well known in the art.
As per claims 4-5, Guidash et al. as modified, disclose a method as recited in claim 1, but do not explicitly disclose a method further comprising: clamping an output of the sampling circuits. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the method of Guidash et al. such that it incorporated the step of clamping an output of the sampling circuits. One would have been motivated to make such a modification for the purpose of fixing levels of an input signal to remain stable and within a defined range, which is crucial for signal processing and analysis, as is well known in the art.
As per claims 6-9, Guidash et al. as modified, disclose a method as recited in claim 1, but do not explicitly disclose a method further comprising: generating a voltage for the second pulse; and filtering the voltage for the second pulse. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the method of Guidash et al. such that it incorporated the step of generating a voltage for the second pulse and filtering the voltage for the second pulse. One would have been motivated to make such a modification for the purpose of creating a signal that has a specific voltage level (in this case, Guidash et al. specify a polarity (Null) opposite a first pulse – see above). Filtering ensures certain signals to pass while blocking others, which helps to improve signal quality and reduce noise, as is well known in the art.
As per claim 10, Guidash et al. as modified, disclose a method as recited in claim 1, but do not explicitly disclose a method further comprising: applying the first pulse to a set of multiple adjacent gate lines of the plurality of gate lines including the first gate line; wherein the other gate lines do not include the set of multiple adjacent gate lines. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the method of Guidash et al. such that it incorporated applying the first pulse to a set of multiple adjacent gate lines of the plurality of gate lines including the first gate line; wherein the other gate lines do not include the set of multiple adjacent gate lines. One would have been motivated to make such a modification for the purpose of reducing capacitive feedback during pixel readout in multiple gate lines, as suggested by Guidash et al. (see for example, Abstract above).
As per claim 11, Guidash et al. as modified, disclose a method as recited in claim 1, but do not explicitly disclose a method further comprising: measuring a dark level of the imaging array; and setting a voltage for the second pulse based on the dark level. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the method of Guidash et al. such that it incorporated the step of: measuring a dark level of the imaging array; and setting a voltage for the second pulse based on the dark level. One would have been motivated to make such a modification for the purpose of obtaining a signal of a sensor (or array) when no light is present, representing a baseline noise level. This is a well-known calibration step that ensures interpretation of low light images and maintains overall image quality.
As per claims 12 and 19, Guidash et al. disclose an imaging array including a plurality of pixels [0002]; circuitry configured to apply voltages to a plurality of gate lines of the imaging array; sample signals from the pixels of the imaging array; apply a first pulse to a first gate line of the plurality of gate lines; apply a second pulse, the second pulse having a polarity opposite to the first pulse; sampling circuits to sample pixels coupled to the first gate line while applying the first pulse (see for example, selected Figs. and Abstract above).
[Examiner note: Guidash et al. do not explicitly use terms “row driver”, “sampling circuits” and/or “control logic.” Examiner recognizes however, that a row driver is a standard implementation of a gate-line control circuitry; sampling circuits are analogous to readout circuitry and serve to process signals from the sensor; control logic refers to components and systems that manage operations of an electronic device by processing inputs and producing outputs. For purposes of examination, Examiner regards the difference in term usage as non-patentable distinctions]
Guidash et al. do not explicitly disclose circuitry configured to apply a second pulse to other gate lines of the plurality of gate lines.
Guidash et al. teach however, applying a second pulse (Null) in order to reduce capacitive feedthrough effects (noise) during pixel readout (see for example, Abstract above).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the system of Guidash et al. such that circuitry is configured to apply a second pulse to other gate lines of the plurality of gate lines. One would have been motivated to make such a modification for the purpose of reducing capacitive feedback during pixel readout as suggested by Guidash et al. (see for example, Abstract above).
As per claims 13-14, Guidash et al. as modified, disclose a system as recited in claim 12, but do not explicitly disclose a system further comprising circuitry configured to: reset sampling circuits before applying the first pulse. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the system of Guidash et al. such that it incorporated circuitry configured to reset sampling circuits before applying the first pulse. One would have been motivated to make such a modification for the purpose of accurately capturing a new input signal without interference from previous readings, as is well known in the art.
As per claim 15, Guidash et al. as modified above, disclose a system as recited in claim 12, but do not explicitly disclose a system further comprising circuitry configured to: apply the first pulse to a set of multiple adjacent gate lines of the plurality of gate lines including the first gate line; wherein the other gate lines do not include the set of multiple adjacent gate lines. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the system of Guidash et al. such that it incorporated circuitry applying the first pulse to a set of multiple adjacent gate lines of the plurality of gate lines including the first gate line; wherein the other gate lines do not include the set of multiple adjacent gate lines. One would have been motivated to make such a modification for the purpose of reducing capacitive feedback during pixel readout in multiple gate lines, as suggested by Guidash et al. (see for example, Abstract above).
As per claim 16, Guidash et al. as modified, disclose a system as recited in claim 12, but do not explicitly disclose a system further comprising circuitry configured to: clamp an output of the sampling circuits; and gate the clamping of the output of the sampling circuits to operate after a start of the first pulse. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the system of Guidash et al. such that it incorporated circuitry configured to clamp an output of the sampling circuits and gate the clamping of the output of the sampling circuits to operate after a start of the first pulse. One would have been motivated to make such a modification for the purpose of fixing levels of an input signal to remain stable and within a defined range, which is crucial for signal processing and analysis, as is well known in the art.
As per claims 17 and 20, Guidash et al. as modified, disclose a system as recited in claims 12 and 19 respectively, but do not explicitly disclose a system further comprising circuitry configured to generate a voltage for a second pulse and filter the voltage of the second pulse. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the system of Guidash et al. such that it incorporated circuitry configured to generate a voltage for the second pulse and filter the voltage for the second pulse. One would have been motivated to make such a modification for the purpose of creating a signal that has a specific voltage level while filtering ensures certain signals to pass while blocking others, which helps to improve signal quality and reduce noise, as is well known in the art.
As per claim 18, Guidash et al. as modified, disclose a system as recited in claim 12, but do not explicitly disclose a system further comprising circuitry configured to measure a dark level of an imaging array; and set a voltage for the second pulse based on the dark level. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the system of Guidash et al. such that it incorporated circuitry configured to measure a dark level of an imaging array; and set a voltage for the second pulse based on the dark level. One would have been motivated to make such a modification for the purpose of obtaining a signal of a sensor (or array) when no light is present, representing a baseline noise level. This is a well-known calibration step that ensures interpretation of low light images and maintains overall image quality.
Conclusion
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/COURTNEY D THOMAS/Primary Examiner, Art Unit 2884