DETAILED ACTION
This Office action is in response to the communication filed on January 16, 2026. Claims 1-14 have been cancelled and claims 29-48 have been added in this application. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on application filed in China on October 22, 2021 has been acknowledged and considered by Examiner. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d) that are placed on record in the application file.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 16, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to new claim 29 in the Remarks section (pages 7-8) have been fully considered but are moot because the arguments do not apply to the current combination of references being used in the current rejection.
Foreign Patent Publication CN 110874990 A by Cai et al. (“Cai”), for which a machine translation is used for the citations below, in view of U.S. Patent Publication 2022/0020321 A1 by Jung et al. (“Jung,”) and further in view of U.S. Patent Publication 2021/0202592 A1 by Kim et al. (“Kim”) address the limitations set forth in the amended claims as the new grounds for rejection.
Applicant's arguments have been fully considered with respect to 30-48 in the Remarks section (page 8) but they are not persuasive as the claims depend upon the features recited in the amended independent claims.
Claim Objections
Claim 29, 31, 43 and 45 are objected to because of the following informalities:
a. “the anode is connected to an anode connection electrode in a fourth conductive layer through a thirteenth via penetrating through a second planarization layer, the anode connection electrode is connected to a third connection electrode through a twelfth via penetrating through a first planarization layer, and the third connection electrode is connected to a second region of a sixth active layer through a fourth via penetrating through a fourth insulating layer, a third insulating layer and a second insulating layer” should be amended to:
“the anode is connected to an anode connection electrode in a third conductive layer through a second via penetrating through a second planarization layer, the anode connection electrode is connected to a first via penetrating through a first planarization layer, and the third via penetrating through a first insulating layer, a second insulating layer and a third insulating layer” in the last six lines of claim 29,
while the elements may be present in the specification, the numbering does not apply as they have no antecedent basis in the claims. For instance, there is no recitation of a first connection electrode and a second connection electrode in the claims, therefore there is not antecedent basis for a third connection electrode. Similar issues arise for other numbered claim limitations. Claim 45 requires the same changes.
b. “wherein the functional component at least partially overlap the hollow pattern” should be amended to:
“wherein the functional component at least partially overlaps the hollow pattern” in the last two lines of claim 43.
c. “The display substrate according to claim 38” should be reviewed to make sure claim 38 is the correct dependency for claim 31.
d. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 29-48 are rejected under 35 U.S.C. 103 as being unpatentable over Foreign Patent Publication CN 110874990 A by Cai, for which a machine translation is used for the citations below, in view of U.S. Patent Publication 2022/0020321 A1 by Jung, and further in view of U.S. Patent Publication 2012/0202592 by Kim.
Regarding claim 29, Cai teaches a display substrate having a display region (Fig. 20, Page 4, first paragraph, The display panel includes a base substrate),
and a main display region surrounding the functional region; the functional region has at least one functional unit; wherein the at least one functional unit (Page 10, first paragraph, The display panel provided in the embodiment of the present application can be applied to an under-screen optical device solution. The optical device is set below the first display area AA1 and Page 4, first paragraph, the display panel comprises a substrate base plate);
wherein the display region comprises a functional region (Fig. 20, transition area AAG and first display area AA1) and a main display region surrounding the functional region (Fig. 1 and 20, second display area AA2 surrounds the transition area AAG and AA1);
the functional region has at least one functional unit (Page 10, first paragraph, The display panel provided in the embodiment of the present application can be applied to an under-screen optical device solution. The optical device is set below the first display area AA1);
each of the at least one functional unit has a winding region (Fig. 20, area where winding lines Rx are located as in Page 29, first paragraph) and a circuit region (Fig. 20, pixel region where area where windings Rx are located in transition area as in Page 29, first paragraph);
the display substrate comprises a base substrate, and a plurality of conductive layers on the base substrate; and each of the at least one hollow pattern is in the blank region; the plurality of conductive layers comprise a first signal line (Page 4, first paragraph and Page 3, last two paragraphs, The display panel includes a base substrate and a first metal layer and a second metal layer located on the base substrate. Connection lines between sub-pixels are located on metal layers), and
the first signal line comprises a first line segment in the main display, a second line segment in the circuit region and a third line segment in the winding region (Fig. 20, Page 28, first paragraph and last paragraph, two second signal lines 2X1 positioned at both sides of the first display area AA1 including a section in transition pixel area and one the main display pixel region in the direction a are electrically connected through the first winding line R1);
wherein extending directions of the first line segment and the second line segment are the same (Fig. 20, a direction), the third line segment electrically connects the first line segment and the second line segment together (See Page 29, first paragraph), and the third line segment comprises at least two line sub-segments with different extending directions (Fig. 20, first winding line R1 projects in a direction and b direction).
wherein the light emitting devices each comprise an anode (Page 11, first paragraph, The first sub-pixel includes an anode, a light-emitting layer and a cathode that are stacked in sequence, the anode is electrically connected to one end of the connection line)
the anode is connected to an anode connection electrode in a third conductive layer through a second via penetrating through a second planarization layer (Page 11, first paragraph, the anode is electrically connected to one end of the connection line, and the other end of the connection line is electrically connected to the first pixel circuit, so as to realize the connection between the first sub-pixel and the first pixel circuit electrical connection. The anode connected through the light emitting layer and cathode and enveloping planarization layers to connect to first and second metal layers using the connection line (via));
the anode connection electrode is connected to a first via penetrating through a first planarization layer(Page 4, first paragraph, The display panel includes a base substrate and a first metal layer and a second metal layer located on the base substrate. The first connection line and the third connection line are located on the first metal layer. The second connection line is located on the second metal layer. The pixel circuit had a connection electrode (source/drain) that connected through lower planarization layers to gate as in Fig. 16). The connection line was an anode connection electrode that went through planarization layer in Fig. 3);
the third via penetrating through a first insulating layer, a second insulating layer and a third insulating layer (Fig. 16; Page 24, last paragraph, The first metal layer 102, the second metal layer 103 and the source-drain metal layer 105 are arranged in sequence on the base substrate 101, wherein the scan line S, the first plate B1, and the gate g are located in the first metal layer 102, The second plate B2 is located on the second metal layer 103, the data line D, and the source electrode s and the drain electrode d are located on the source-drain metal layer 105; that is, the first metal layer 102 is the gate metal layer, and the second metal layer 103 insulated from one another).
Cai does not teach each of the at least one functional unit has a blank region and the plurality of conductive layers form at least one hollow pattern. However, Cai did teach connections between sub-pixels were located on the conductive metal layers overlapping the optical device in Cai Page 4, first paragraph and Page 24, last paragraph, and if there are no sub-pixels, that would mean the conductive layers also facilitate a hollow pattern.
In the analogous art of having a first and second display areas with optical structures, Jung teaches a second display area was able to have been configured to a be a transparent window where the opaque wiring lines were detoured around the second display area (Jung Fig. 18B; [0012]-[0013]; [0204]). The opaque wiring lines were gate and data wires formed pixels in the form of a matrix. In the first display area, all the gate wiring lines and the data wiring lines may be provided in straight lines, but some of the gate wiring lines and the data wiring lines in the second display area may be bent outwards from the center of the second display area (Jung Fig. 18B; [0012]; [0204]-[0205]). Two or more components were able to have been disposed in one second display area, where a component included at least one of an antenna integrated with the display and touch area between the transparent substrate and the display (Jung [0137] and [0209]).
It would have been obvious before the effective filing date to have configured the rerouted wiring first display region of Cai as a transparent/blank window with a hollow pattern without pixels with a component such as an antenna arranged in the seco as taught by Jung. One of ordinary skill in the art would have motivated to have the opaque wiring lines 1852 are arranged to be detoured around the second display area, so that the transparency and transmittance of the second display area can be improved (Jung Fig. 18B; [0204]-[0205]).
However, Cai in view of Jung does not specifically teach the layers enveloping the anode, light emitting layer and cathode are planarization layers and insulating layers are used for insulating.
However, in the analogous art of organic light emitting display structure, Kim teaches a planarization layer 146 is disposed on the passivation layer to planarize an upper portion of the thin film transistor TFT. In the planarization layer 146, a contact hole which exposes the source electrode S or the drain electrode D of the thin film transistor TFT is formed (Kim Fig. 2; [0072]). The organic light emitting element 150 is disposed on the planarization layer 146. The organic light emitting element 150 includes a first organic light emitting element disposed in a first sub pixel SP1 area. The anode 152 is disposed on the planarization layer 146. The anode 152 is disposed on the planarization layer 146 to be electrically connected to the source electrode S or the drain electrode D through the contact hole formed in the planarization layer 146 (Kim Fig. 2; [0073]-[0074]). The encapsulation layer covers the layers of the organic light emitting diode such as the anode, cathode, and light emitting layer that must be connected thorough in the arrangement of the anode as in Cai (Kim Fig. 2; [0042]). An interlayer insulating layer 142 is disposed on the first buffer layer 114 and the gate electrode G. The interlayer insulating layer 142 insulates the gate electrode G from the source electrode S and the drain electrode D. The interlayer insulating layer 142 may be formed as a single layer or a multi-layer of silicon nitride SiNx or silicon oxide SiOx (Kim Fig. 2; [0069]). It would have been obvious before the effective filing date to have the intermediary layers as taught by Kim. One having ordinary skill in the art would have been motivated to have provideda manufacturing method of an organic light emitting display device which simplifies the entire process of the organic light emitting display device and reduces the process cost with necessary layers without a polarizing plate that prevents foldable organic light emitting devices (Kim [0007] and [0014])
Regarding claim 30, Cai of the combination of references further teaches the electronic apparatus according to claim 29, wherein in the functional unit, the winding region surrounds the blank region (Fig. 20, windings surrounds first display region AA1), and the circuit region surrounds the winding region (Fig. 20, transition area surrounds windings Rx); and the first line segment, the second line segment and the third line segment of the first signal line are directly and electrically connected together (Page 29, first paragraph, It is further provided that the two second signal lines on both sides of the first display area are connected through the second winding in the transition area, so that the second signal line extending in the fourth direction does not need to run through the first display area, reducing the number of traces in the first display area can help to increase the area of the light-transmitting area in the first display area, and then be applied to the scheme of the optical device under the screen to increase the amount of light received by the optical device).
Regarding claim 31, Cai of the combination of references further teaches the electronic apparatus according to claim 38, wherein the plurality of conductive layers comprise a first conductive layer and a second conductive layer on the base substrate (Page 4, first paragraph, The display panel includes a base substrate and a first metal layer and a second metal layer located on the base substrate. The first connection line and the third connection line are located on the first metal layer. The second connection line is located on the second metal layer); the first conductive layer comprises first type signal lines each having a main body part extending in a first direction (Page 13, last paragraph and Page 14, first paragraph, among the three line segments arranged in sequence, two line segments that are not adjacent in the arrangement direction are located in the same film layer, that is, the use of two layers of metal can realize the production of three connection lines, and can ensure that the three connection lines are in the same direction. The parts (that is, the first line segment, the second line segment, and the third line segment) extending in sequence along the other direction are insulated from each other), and the first type signal lines comprise a first sub-type signal line and a second sub-type signal line; the first sub-type signal line is only in the main display region; and the second sub-type signal line is in both the main display region and the winding region (Fig. 20, Page 28, first paragraph and last paragraph; Page 4, first paragraph and Page 24, last paragraph, two second signal lines 2X1 positioned at both sides of the first display area AA1 including a section in transition pixel area (first sub-type) and one the main display pixel region (first sub-type) in the direction a are electrically connected through the first winding line R1(second sub-type)) The scan line S, the first electrode plate B1, and the gate g are located in the first metal layer 102);
the second conductive layer comprises second type signal lines each having a main body part extending in a second direction, and the second type signal lines comprise a third sub-type signal line and a fourth sub-type signal line; the third sub-type signal line is only in the main display region; and the fourth sub-signal line is in both the main display region and the winding region; and the first signal line comprises the second sub-type signal line and/or the fourth sub-type signal line (Fig. 20, Page 28, first paragraph and last paragraph; Page 4, first paragraph and Page 24, last paragraph, two second signal lines 2X2 positioned at both sides of the first display area AA1 including a section in transition pixel area (first sub-type) and one the main display pixel region (third sub-type) in the direction a are electrically connected through the first winding line R2(fourth sub-type)) The second electrode plate B2 is located on the second metal layer 103, the data line D, and the source electrode s and the drain electrode d are located on the source and drain metal layer 105).
Regarding claim 32, Cai of the combination of references further teaches the electronic apparatus according to claim 31, wherein the third line segment comprises a first line sub-segment extending in the first direction and a second line sub-segment extending in the second direction (Fig. 20, first winding line R1 projects in a direction and b direction via different line segments).
Regarding claim 33, Cai of the combination of references further teaches the electronic apparatus according to claim 32, wherein the first line sub-segment and the second line sub-segment of the third line segment are directly electrically connected together (Fig. 20, first winding line R1 projects in a direction and b direction via different directly connected line segments).
Regarding claim 34, Cai of the combination of references further teaches electronic apparatus according to claim 32, wherein the first conductive layer comprises the first line sub-segment, the second conductive layer comprises the second line sub-segment, and the first line sub-segment and the second line sub-segment of the third line segment are electrically connected together through a via penetrating through an interlayer insulating layer (Page 13, last paragraph and Page 14, first paragraph, among the three line segments arranged in sequence, two line segments that are not adjacent in the arrangement direction are located in the same film layer, that is, the use of two layers of metal can realize the production of three connection lines, and can ensure that the three connection lines are in the same direction. The parts (that is, the first line segment, the second line segment, and the third line segment) extending in sequence along the other direction are insulated from each other).
Regarding claim 35, Cai of the combination of references further teaches electronic apparatus according to claim 31, wherein the first signal line is the second sub-type signal line, and the second sub-type signal line is arranged in mirror symmetry, taking a straight line passing through a center of the functional region and extending in the first direction as a symmetry axis; or the first signal line is the fourth sub-signal line, and the fourth sub-signal line is arranged in mirror symmetry, taking a straight line passing through the center of the functional region and extending in the second direction as a symmetry axis (Fig. 20, Page 28, first paragraph and last paragraph, two second signal lines 2X1 positioned at both sides of the first display area AA1 including a section in transition pixel area and one the main display pixel region in the direction a are electrically connected through the first winding line R1 are mirror symmetric with respect to the center of first display region AA1 when rerouting straight line 1X1 in b direction by windings Rx).
Regarding claim 36, Cai of the combination of references further teaches the electronic apparatus according to claim 31, wherein the first type signal lines comprise at least one of a gate line, a reset signal line, and a light emitting control line (Page 4, first paragraph and Page 24, last paragraph, The display panel includes a base substrate and a first metal layer and a second metal layer located on the base substrate. The first connection line and the third connection line are located on the first metal layer. The second connection line is located on the second metal layer. The scan line S, the first electrode plate B1, and the gate g are located in the first metal layer 102).
Regarding claim 37, Cai of the combination of references further teaches electronic apparatus according to claim 31, wherein the second type signal lines comprise at least one of a data line, an initial signal line, and a power supply signal line (Page 4, first paragraph and Page 24, last paragraph, The display panel includes a base substrate and a first metal layer and a second metal layer located on the base substrate. The first connection line and the third connection line are located on the first metal layer. The second connection line is located on the second metal layer. The second electrode plate B2 is located on the second metal layer 103, the data line D, and the source electrode s and the drain electrode d are located on the source and drain metal layer 105).
Regarding claim 38, Cai of the combination of references further teaches the electronic apparatus according to claim 29, wherein a spacing between the third line is less than a spacing between the first line segments (Fig. 20, spacing between windings R1, R2 was less than between second signal lines 2X1 to reduce spacing through first display area, meaning same amount of wires with less space as in Page 28, first paragraph).
Regarding claim 39, Cai of the combination of references further teaches the electronic apparatus according to claim 29, further comprising pixel driving circuits in the main display region and the circuit region, where a distribution density of the pixel driving circuits in the main display region is the same as a distribution density of the pixel driving circuits in the circuit region (Fig. 20, distribution density of sub-pixels same in the transition region and the main display area. Also see Page 28, first paragraph).
Regarding claim 40, Cai of the combination of references further teaches the electronic apparatus according to claim 29, further comprising light emitting devices in the main display region and the functional region, wherein a distribution density of the light emitting devices in the main display region is greater than a distribution density of the light emitting devices in the functional region (Fig. 19, distribution density of sub-pixels in the main display area is greater than in the transition region. Also see Page 27, last paragraph).
Regarding claim 41, Cai of the combination of references further teaches the electronic apparatus according to claim 29, further comprising light emitting devices in the main display region and the functional region, wherein the light emitting devices each comprise an anode on the base substrate; for the light emitting devices of a same color, an area of the anode of the light emitting device in the main display region is less than an area of the anode of the light emitting device in the functional region (Fig. 21, Page 11, first paragraph, Page 29, last paragraph, Page 30, first paragraph The first sub-pixel includes an anode, a light-emitting layer, and a cathode, which are sequentially stacked. The anode is electrically connected to one end of the connection line, and the other end of the connection line is electrically connected to the first pixel circuit, thereby realizing the first sub-pixel and the first pixel circuit. The transition area AAG includes a plurality of pixel areas P1 and a plurality of circuit areas P2, the transition sub-pixel spg is located in the pixel area P1, and the first pixel circuit DL1 is located in the circuit area P2, increasing anode area with more sub-pixels).
Regarding claim 42, Cai of the combination of references further teaches the electronic apparatus according to claim 41, wherein a part of the anodes of the light emitting devices partially cover the blank region (Page 11, first paragraph, The first sub-pixel includes an anode, a light-emitting layer, and a cathode, which are sequentially stacked. The anode is electrically connected to one end of the connection line, and the other end of the connection line is electrically connected to the first pixel circuit, thereby realizing the first sub-pixel and the first pixel circuit.)
However, Cai does not teach orthographic projections of the functional component and the first signal line on the base substrate do not overlap each other.
In the analogous art of having a first and second display areas with optical structures, Jung teaches a second display area was able to have been configured to a be a transparent window where the opaque wiring lines were detoured around the second display area (Jung Fig. 18B; [0012]-[0013]; [0204]). The opaque wiring lines were gate and data wires formed pixels in the form of a matrix. In the first display area, all the gate wiring lines and the data wiring lines may be provided in straight lines, but some of the gate wiring lines and the data wiring lines in the second display area may be bent outwards from the center of the second display area (Jung Fig. 18B; [0012]; [0204]-[0205]). Two or more components were able to have been disposed in one second display area, where a component included at least one of an antenna integrated with the display and touch area between the transparent substrate and the display (Jung [0137] and [0209]). It would have been obvious before the effective filing date to have configured the rerouted wiring first display region of Cai as a transparent/blank window with a hollow pattern without pixels with a component such as an antenna arranged in the seco as taught by Jung. One of ordinary skill in the art would have motivated to have the opaque wiring lines 1852 are arranged to be detoured around the second display area, so that the transparency and transmittance of the second display area can be improved (Jung Fig. 18B; [0204]-[0205]).
Regarding claim 43, an electronic apparatus, comprising the display substrate according to claim 29 and a functional component, wherein the functional component at least partially overlap the hollow pattern.
Regarding claim 44, Cai in view of Jung and Kim renders obvious the claim limitations in consideration of the grounds of rejection of claim 30 above.
Regarding claim 45, Cai in view of Jung and Kim renders obvious the claim limitations in consideration of the grounds of rejection of claim 31 above.
Regarding claim 46, Cai in view of Jung and Kim renders obvious the claim limitations in consideration of the grounds of rejection of claim 32 above.
Regarding claim 47, Cai in view of Jung and Kim renders obvious the claim limitations in consideration of the grounds of rejection of claim 41 above.
Regarding claim 48, Cai does not teach the electronic apparatus according to claim 47, wherein a part of the anodes of the light emitting devices partially cover the blank region; and orthographic projections of the functional component and the anode on the base substrate do not overlap each other.
In the analogous art of having a first and second display areas with optical structures, Jung teaches a second display area was able to have been configured to a be a transparent window where the opaque wiring lines were detoured around the second display area (Jung Fig. 18B; [0012]-[0013]; [0204]). The opaque wiring lines were gate and data wires formed pixels in the form of a matrix. In the first display area, all the gate wiring lines and the data wiring lines may be provided in straight lines, but some of the gate wiring lines and the data wiring lines in the second display area may be bent outwards from the center of the second display area (Jung Fig. 18B; [0012]; [0204]-[0205]). Two or more components were able to have been disposed in one second display area, where a component included at least one of an antenna integrated with the display and touch area between the transparent substrate and the display (Jung [0137] and [0209]). It would have been obvious before the effective filing date to have configured the rerouted wiring first display region of Cai as a transparent/blank window with a hollow pattern without pixels with a component such as an antenna arranged in the seco as taught by Jung. Therefore, the anodes would connect only to pixel circuit and not where the antenna was integrated One of ordinary skill in the art would have motivated to have the opaque wiring lines 1852 are arranged to be detoured around the second display area, so that the transparency and transmittance of the second display area can be improved (Jung Fig. 18B; [0204]-[0205]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Publication 2020/0343314A1 by Nakamura et al. teaching a display device on substrates with antennas integrated in the display, the number of turns of a loop antenna can be selected based on the selection of the resonance frequency and the setting condition of the impedance of the antenna optimum for resonance. The loop was preferably a large area.
Foreign Patent Publication CN113451358A by Li et al. teaches a display panel comprises a punching area, a non-display area and a display area, wherein the plurality of first signal lines comprise first signal lines which simultaneously pass through the display area and the non-display area and second signal lines which only pass through the display area and do not pass through the non-display area.
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/MAHEEN I JAVED/Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621