DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Final Rejection is in response to the Applicant’s remarks and arguments filed on 1/20/2026. Claims 1, 3, 21, and 22 have been amended and claim 2 has been cancelled. Therefore, claims 1, 3, 7-19, and 21-24 remain pending in the application and are being considered on the merits.
Response to Arguments
Applicant’s arguments filed on 1/20/2026 have been fully considered with the following results:
Regarding the claim objections, the Applicant has amended claims 1, 3, 21, and 22 to fix various informalities.
As a result, the Examiner believes the objections have been overcome and therefore they will be withdrawn.
Regarding the non-statutory double patenting rejection, the Applicant has incorporated the contents of claim 2 into claims 1, 21, and 22.
The Examiner believes that this amendment has overcome the double patenting rejection and as such the rejection will be withdrawn.
Regarding the claim rejections under 35 U.S.C. 112, the Applicant has amended claim 21 to remove the term “apparatus” and “constructing unit” from the claim language.
As a result, the Examiner concludes that the rejections under 35 U.S.C. 112 will be withdrawn.
Regarding the rejections under 35 U.S.C. 103, the Applicant has incorporated the contents of claim 2 into claims 1, 21, and 22 while amending claim 3. The Applicant argues various points regarding the prior art combination used. For example, the Applicant contends that Gurfinkel cannot be used as a combined reference since its teachings are “serving to optimize the computing accuracy of a single node rather than driving cross-node communication among multiple nodes.” Further, the Applicant argues that the combination of Chai and Gurfinkel do not teach the three types of sub-information in the “task description information” such as the “receiving address information,” “computing task information,” and “sending address information.”
The Examiner respectfully disagrees. The Examiner contends that the combination of Gurfinkel with the Chai reference is built at least in part on enhancing the nodes within the architecture of Chai. As explained within the U.S.C. 103 section within the previous Non-Final Rejection, the teachings of Chai include constructing task description information within a multi-node network topology. The teachings of Gurfinkel include compute tasks with parameters including starting addresses, source/destination locations of memory blocks, and the size or amount of memory which is necessary for the task. The implication of the Gurfinkel reference is not that it teaches a multi-node network topology as Chai does, but rather that the teachings of Gurfinkel provide an enhancement to the nodes within the multi-node network topology by including various parameters that outline receiving and sending addresses. These parameters would allow for the expansion of a multi-node environment by providing information relating to addresses of a compute task, source/destination locations of memory blocks as well as the amount of memory for the task. The Examiner maintains that the teachings of Chai are inclusive of creating task description information and sending the task description information to various nodes, thereby performing inter-node communication in which the task description information is being shared between the various nodes. The Examiner further maintains that the teachings of Gurfinkel are inclusive of at least one of the “receiving address information,” “computing task information,” and “sending address information” (although the Examiner would also contend that all three are taught by the Gurfinkel reference) which can be used to make up the task description information which is further utilized by the Chai reference. The Examiner concludes that since the BRI of the current claim language is taught/suggested by the combination of references that the rejection under 35 U.S.C. 103 will be maintained. For further explanation please refer to the 103 rejection section below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 19, 21, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai (US 10200287) in view of Gurfinkel et al. (US 20210149734).
Regarding claims 1, 21, and 22, Chai teaches: A system comprising a host, which includes a second constructing unit (host physical machine connected to scheduler platform and to the RM Col. 8 lines 1 – 5) / electronic device comprising a memory, on which a computer-executable instruction is stored, wherein, when the computer-executable instruction is run by the one or the plurality of processors, the electronic device performs a method steps of: (program code used to implement the technical solution stored in memory and executed by processor Col. 19 Lines 35 – 43)/ method for performing inter-node communication based on a plurality of processing nodes, wherein at least two processing nodes of the plurality of processing nodes form a communication topology structure (computation nodes as a part of network topology Col. 22 Line 62 – Col. 23 Line 2), the method comprising: constructing task description information (obtaining task description information Col. 2 Line 59 – Col. 3 Line 17), wherein the task description information includes at least one of following: receiving address information, computing task information, and sending address information (task description information includes network information which includes IP addresses and port numbers corresponding to computation node Col. 2 Line 59 – Col. 3 Line 37); and sending the task description information to the at least two processing nodes to enable processing nodes that have received the task description information to perform the inter-node communication according to the task description information (sending module providing decomposed task description information to nodes of the computation environment and working through a designation module to designate/monitor status of the computation task as well as using a routing policy for communication Col. 2 Line 1 – Col. 3 Line 37 and Col. 15 Line 30 – Col. 16 Line 4)
Chai does not explicitly teach the specifics of the receiving address, computing task, and sending address information.
However, Gurfinkel teaches: wherein the receiving address information is used to indicate a memory address and a memory size for storing data by the processing nodes after receiving the data; the computing task information is used to indicate an entry address of a computing function and a parameter of the computing function (compute task including parameters including starting address of a compute task, source/destination locations of memory blocks, and size or amount of memory necessary for the task par. 0317 – 0318); and the sending address information is used to indicate a memory address and a memory size of to-be-sent data (information regarding the task including source/destination locations of memory blocks, and size or amount of memory necessary for the task par. 0317 – 0318).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai with the teachings of Gurfinkel since the compute clusters alongside the modifiable node parameters of Gurfinkel would enhance the system/methods of Chai by improving memory performance as well as allowing for task graphs to be applied to executable graphs generated from another task graph.
Claim 23 recites performing the methods of claim 1, therefore it is rejected for the same reasonings and rationale as above.
Regarding claim 7, Gurfinkel teaches: wherein sending the task description information to the at least two processing nodes includes sending the task description information to the at least two processing nodes in the form of a queue, so as to enable the task description information to be executed sequentially (out-of-order execution engine may prepare instructions for execution, re-ordering the flow of instructions as they go down the pipeline, including a memory uop queue which may allocate instructions to queues par. 0152 see also par. 0102 and 0276 in which a work descriptor can contain a pointer to a queue of jobs as well as the usage of command queues for distributing commands to workload managers).
For motivation to combine see claim 1 above.
Regarding claim 19, Gurfinkel teaches: wherein the task description information further includes synchronization information used for enabling the processing nodes to perform a computing operation after receiving at least two pieces of data involved in computing (multiple instances of GPGPU can be configured to operate as a compute cluster which includes GPU linking between instances, enabling communication and synchronization. These compute clusters perform the computing operations once vendor specific communication/execution threads/commands are received from a host processor par. 0116 – 0119 and 0126 - 0127. Further, this synchronization may occur within thread blocks, in which threads within a thread block share data and synchronize execution to coordinate memory accesses par. 0267).
It would be obvious to one of ordinary skill in the art that since the synchronization of the GPUs/compute clusters may be done through thread/thread block implementation, and that there is a plurality of threads/thread blocks throughout the GPU network, that sharing data between all of the thread blocks requires at least communication including two pieces of data (such as data exchanged through GPU instances or intermediate data produced by one or more of the clusters).
For motivation to combine see claim 1 above.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai in view of Gurfinkel and further in view of Bruneau et al. (US 20210367755).
Regarding claim 3, Gurfinkel teaches: wherein the parameter of the computing function includes at least one of following: an address of to-be-computed data (starting address to a compute task par. 0318), an output address of a computing result (pointer to next task to be performed par. 0318), and a data type of a computing operation; wherein the parameter of the computing function further includes scheduling information (processing tasks can include indices of data to be processed, and these processing tasks are sent to a scheduler which uses task information to perform scheduling and work distribution par. 0122 – 0127); and wherein the scheduling information includes at least one of following: a count of computing resources occupied, priorities of computing resources used, and a priority of each task in a plurality of tasks (scheduler unit tracks state information related to various tasks including priority levels associated with each task par. 0181).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai with the teachings of Gurfinkel since the compute clusters alongside the modifiable node parameters of Gurfinkel would enhance the system/methods of Chai by improving memory performance as well as allowing for task graphs to be applied to executable graphs generated from another task graph.
Gurfinkel does not explicitly teach the listed functions.
However, Bruneau teaches: wherein the entry address of the computing function includes the entry address of at least on of the following functions: an addition function, a subtraction function, a multiplication function, a division function, a maximum function, a minimum function, and a logical and-or-invert function (in a dependency graph, in which nodes represent an instruction of the intermediary representation, variables used/required to execute these instructions may include arithmetic functions or boolean functions applicable to the variables within the nodes par. 0129 – 0144)
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai and Gurfinkel with the functions of Bruneau since the teachings of Bruneau provide further use cases for statements which may be an address assignment as well as using computation functions. These statements/operations can be used in the execution of programs (in this case cryptographic programs) which may be structured as a graph-based or tree-based object oriented structure as well as a special tuple. Therefore, the methods/systems of Chai and Gurfinkel would be enhanced by the ability to use these types of functions throughout the various nodes within the topology.
Claim(s) 8 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai and Gurfinkel in view of Ishibashi et al. (US 20030147352).
Regarding claims 8 and 24, Ishibashi teaches: wherein the at least two processing nodes of the plurality of processing nodes form the communication topology structure by: constructing node configuration information (in response to path setup request, creation of route information par. 0085 – 0087), wherein the node configuration information includes upstream node information (path table including upstream node information par. 0058 and 0147), current node information (current node link/path identifiers par. 0050 – 0052), and downstream node information (path table including downstream node information par. 0058 and 0147); and sending the node configuration information to the at least two processing nodes to construct the communication topology structure (node controller sends control messages to all nodes to establish connections through the switches of all nodes based on the topology/path par. 0147).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai and Gurfinkel with the teachings of Ishibashi since Ishibashi provides the enhancement of communication networks being modified so that port tables, path tables, and link tables of all nodes are concentrated into a network controller and created in the memory of said network controller, making it so that no routing protocol is used to broadcast link state messages (Ishibashi: par. 0147).
Claim(s) 9-11, and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai and Gurfinkel in view of Ishibashi and further in view of Wan (US 20050237948).
Regarding claim 9, Wan teaches: wherein the upstream node information is used to indicate a processing node that sends data to a current node, the current node information is used to indicate a processing node that computes the data received, and the downstream node information is used to indicate a processing node that receives the data computed from the current node (“front”, “own”, and “behind” indicating the positioning of a node in the network par. 0046 – 0047).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai, Gurfinkel, and Ishibashi with the teachings of Wan since the teachings of Wan provide a network topology configuration method in which new entry nodes can quickly find positional relationships in the network as well as allowing for failure to only locally affect the network (Wan: par. 0016).
Regarding claim 10, Wan teaches: wherein the node configuration information is in the form of a queue tuple, including <upstream node, downstream node> or <upstream node, current node, downstream node> (distributed hash table includes node address/hash values “front”, “own”, and “behind”, i.e., <upstream node, current node, downstream node> see Fig. 9 and par. 0059).
For motivation to combine see claim 9 above.
Regarding claim 11, Wan teaches: wherein node configuration information for a single processing node has a plurality of pieces of node configuration information, and the node configuration information has a plurality of pieces of different upstream node information and/or a plurality of pieces of different downstream node information (distributed has table including “front”, “own”, and “behind” as a plurality of pieces, see Fig. 9 and “front” and “behind” each including hash value node address which is a plurality of pieces of different upstream/downstream node information see Fig. 9 and par. 0057 – 0061).
For motivation to combine see claim 9 above.
Regarding claim 13, Wan teaches: wherein sending the node configuration information to the at least two processing nodes to construct the communication topology structure includes: sending different node configuration information to at least part of processing nodes of all processing nodes (transmitting the network topology configuration information to the new entry node par. 0068) to construct the at least part of processing nodes as different communication topology structures (new node establishes connections with the nodes involved based on the network topology configuration information par. 0053).
For motivation to combine see claim 9 above.
Regarding claim 14, Wan teaches: wherein the communication topology structure includes at least one of a chain topology structure, a ring topology structure (ring network par. 0041), and a tree topology structure.
For motivation to combine see claim 9 above.
Regarding claim 15, Wan teaches: wherein constructing the communication topology structure includes enabling the processing nodes in the communication topology structure to reserve resources (establishing/reserving connections with nodes involved par. 0053).
For motivation to combine see claim 9 above.
Regarding claim 16, Wan teaches: wherein the resources include communication resources and/or register resources (connections are being established through communication resources par. 0053).
For motivation to combine see claim 9 above.
Regarding claim 17, Wan teaches: wherein the communication resources include: a port and/or a channel required for the inter-node communication (establishing connections with nodes involved through inter-node communication methods par. 0053); and the register resources include: storage space used for storing the task description information, wherein the task description information is used to indicate an operation to be performed by each processing node in the communication topology structure constructed (claimed in the alternative of claim 16).
For motivation to combine see claim 9 above.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai and Gurfinkel in view of Ishibashi and Wan and further in view of Wu et al. (US 11341009).
Regarding claim 12, Wu teaches: wherein one of the upstream node information and the downstream node information is null (using null values in a distributed hash table Col. 7 Lines 11-17).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai, Gurfinkel, Ishibashi, and Wan with the teachings of Wu because doing so would provide an easier way to update distributed hash tables in the even that a node leaves the network (Wu: Col. 7 Lines 12-13).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai and Gurfinkel in view of Ishibashi and Wan.
Regarding claim 18, Gurfinkel teaches: wherein the task description information is stored in the storage space in the form of a queue (work descriptor can contain a pointer to a queue of jobs in application effective address space par. 0102).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Chai, Ishibashi, and Wan with the teachings of Gurfinkel since the compute clusters alongside the modifiable node parameters of Gurfinkel would enhance the system/methods of Chai, Ishibashi, and Wan by improving memory performance as well as allowing for task graphs to be applied to executable graphs generated from another task graph.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.S.M./ Examiner, Art Unit 2198
/PIERRE VITAL/ Supervisory Patent Examiner, Art Unit 2198
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