DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Response to Amendment
The Examiner acknowledges the amending of claims 1, 5, 8, 12, 15 and the cancellation of claim 20.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The Examiner notes an updated interpretation of Joseph, as well as application of new art, is used to make the following rejections.
Claim Rejections - 35 USC § 112
The previous 112 rejections are withdrawn due to the current amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joseph (US 2017/0033535) in view of Izumiya et al. (US 2021/0167579; note foreign priority with support) and Dummer et al. (US 2020/0278426).
With respect to claim 1, Joseph teaches a Vertical Cavity Surface Emitting Laser (VCSEL) array device (fig.8-14c), comprising: a submount (fig.14b #1403); and a VCSEL array chip (fig.14b seen above mount) attached to the submount (fig.14c), the VCSEL array chip comprising: a substrate (fig.8 #81); and a plurality of VCSEL structures (fig.14b 6 VCSELs) formed in a first chip region (fig.14b central region containing the 6 VCSELs + surround outer trenches) above the substrate, each VCSEL structure comprising: a contact layer (fig.8 #84) above the substrate; a first reflector region (fig.8 #83/85) formed above the contact layer (portion #85 above #84); an active region (fig.8 #86) formed above the first reflector region; a second reflector region (fig.8 #88) formed above the active region; a first metal layer (fig.12 #1201) above and connected to the contact layer ([0251]); a second metal layer (fig.12 #1303) above and connected to the first metal layer (#1201 and #1303 electrically connected via mesa stack); and a third metal layer (fig.12 #1302/1304) formed above the second reflector region, wherein the second metal layer partially surrounds each of the plurality of VCSEL structures, respectively, (#1303 at least partially surrounds the VCSELs on an individual basis) and extends through the second reflector region, the active region, and the first reflector region (as seen in fig.13), and the second and third metal layers face the submount and are between the substrate and the submount after the VCSEL array chip is attached to the submount (as seen in fig.14b/c). Joseph further teaches the second metal layer is useful for heat sinking ([0255]), but does not teach the second metal layer to completely surround each of the plurality of VCSEL structures, respectively. Izumiya teaches a related VCSEL array (fig.15/16), which forms the mesas in a connected manner (fig.16 via #102) and which includes a metal layer completely surrounding each of the plurality of VCSEL structures, respectively (fig.15/16 #460, note can also include #112). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the device of Joseph to make the second metal layer completely surround each of the VCSEL devices, respectively, by more fully etching around each mesa in order to more fully sink heat from the mesas (Izumiya, [0092, 94, 95]).
Joseph does not teach a multijunction active region including a plurality of multiple-quantum-well (MQW) active regions. Dummer teaches a VCSEL array (fig.9) which makes use of a multijunction active region including a plurality of multiple-quantum-well (MQW) active regions (fig.13, [0106-109]). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to replace the active region of Joseph with the multijunction active region including a plurality of multiple-quantum-well (MQW) active regions taught by Dummer in order to improve efficiency (Dummer, [0111]).
With respect to claim 2, Joseph teaches the first reflector region and the second reflector region each comprise a Distributed Bragg Reflector (DBR) structure ([0139]).
With respect to claim 3, Joseph teaches the second metal layer is formed on the first metal layer (fig.13, on meaning ‘in close proximity’).
With respect to claim 4, Jospeh, as modified, teaches the device outlined above, but does not teach the embodiment to make use of a plurality of lenses formed on a surface of the substrate. Joseph teaches an additional embodiment (fig.22) which uses lens (fig.22 #257s) formed on a surface of the substrate. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the initial embodiment of Joseph to include lens formed on a surface of the substrate as taught by the later embodiment of Joseph in order to control the path of the output light.
With respect to claim 5, Joseph teaches the contact layer (fig.8 #84) formed between the first reflector region and the substrate (formed between at least portion #85 of first reflector and substrate) is doped ([0055, 255]).
With respect to claim 6, Joseph teaches a fourth metal layer (fig.14b #1404/1406 leftmost) electrically connected to the second metal layer (fig.14b via solder + plating layer; would be electrically connected via path through semiconductor mesa), wherein the fourth metal layer is outside the first chip region (formed in non-emitter/trench area) and the third metal layer is inside the first chip region (formed in emitter/trench area).
With respect to claim 7, Joseph, as modified, teaches the second metal layer has a ring shape (see Izumiya, fig.15).
With respect to claim 8, Joseph teaches a method for fabricating (0219-0264] outline formation methods including epitaxy) a Vertical Cavity Surface Emitting Laser (VCSEL) array device (fig.8-14c), comprising: forming a plurality of VCSEL structures (fig.14b 6 VCSELs) in a first chip region (fig.14b central region containing the 6 VCSELs + surrounding trenches) above a substrate (fig.8 #81) of a VCSEL array chip; and attaching the VCSEL array chip on a submount (fig.14b/c #1403), wherein forming the plurality of VCSEL structures comprises: growing a contact layer (fig.8 #84) above the substrate; growing a first reflector region (fig.8 #83/85) above the contact layer (fig.8 #85 above #84); growing an active region (fig.8 #86) above the first reflector region; growing a second reflector region (fig.8 #88) above the active region; forming a first metal layer (fig.12 #1201) above the contact layer (fig.12 #1201 on #84); forming a second metal layer (fig.13 #1303) above the first metal layer (fig.13); and forming a third metal layer (fig.12 #1302/1304) above the second reflector region, wherein the second metal layer partially surrounds the plurality of VCSEL structures, respectively, (#1303 at least partially surrounds the VCSELs on an individual basis) and extends through the second reflector region, the active region, and the first reflector region (fig.13), and the second and third metal layers face the submount and are between the substrate and the submount after the VCSEL array chip is attached on the submount (as seen in fig.14b/c). Joseph further teaches the second metal layer is useful for heat sinking ([0255]), but does not teach the second metal layer to completely surround each of the plurality of VCSEL structures, respectively. Izumiya teaches a related VCSEL array (fig.15/16), which forms the mesas in a connected manner (fig.16 via #102) and which includes a metal layer completely surround each of the plurality of VCSEL structures, respectively (fig.15/16 #460, note can also include #112). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the device of Joseph to make the second metal layer completely surround each of the VCSEL devices, respectively, by more fully etching around each mesa in order to more fully sink heat from the mesas (Izumiya, [0092, 94, 95]).
Joseph does not teach a multijunction active region. Dummer teaches a VCSEL array (fig.9) which makes use of a multijunction active region including a plurality of multiple-quantum-well (MQW) active regions (fig.13, [0106-109]). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to replace the active region of Joseph with the multijunction active region including a plurality of multiple-quantum-well (MQW) active regions taught by Dummer in order to improve efficiency (Dummer, [0111]).
With respect to claim 9, Joseph teaches the first reflector region and the second reflector region each comprise a Distributed Bragg Reflector (DBR) structure ([0139]).
With respect to claim 10, Joseph teaches the second metal layer is formed on the first metal layer (fig.13 #1303 on, as in close proximity with, #1201).
With respect to claim 11, Jospeh, as modified, teaches the device outlined above, but does not teach the embodiment to form a plurality of lenses formed on a surface of the substrate. Joseph teaches an additional embodiment (fig.22) which forms a plurality of lenses (fig.22 #257s) formed on a surface of the substrate. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the initial embodiment of Joseph to include lens formed on a surface of the substrate as taught by the later embodiment of Joseph in order to control the path of the output light.
With respect to claim 12, Jospeh teaches the contact layer (fig.8 #84) between the first reflector region and the substrate (formed between at least portion #85 of first reflector and substrate) is doped ([0055, 255]).
With respect to claim 13, Jospeh teaches depositing a fourth metal layer (fig.14b #1404/1406 leftmost) electrically connected to the second metal layer (fig.14b via solder + plating layer and through semiconductor structure), wherein the fourth metal layer is outside the first chip region (formed in non-emitter/trench area) and the third metal layer is inside the first chip region (formed in emitter/trench area).
With respect to claim 14, Joseph, as modified, teaches the second metal layer has a ring shape (Izumiya, fig.15).
With respect to claim 15, Joseph teaches a Vertical Cavity Surface Emitting Laser (VCSEL) array device (fig.8-14c), comprising: a submount (fig.14 #1403); and a VCSEL array chip (fig.14b above submount) attached to the submount (as seen in fig.14b), the VCSEL array chip comprising: a substrate (fig.8 #81); and a plurality of VCSEL structures (fig.14b 6 VCSELs) formed in a first chip region (fig.14b central region containing the 6 VCSELs + surrounding trenches) above the substrate, each VCSEL structure comprising: a contact layer (fig.8 #84) formed above the substrate; a first reflector region (fig.8 #83/85) formed above the contact layer (at least portion #85); a active region (fig.8 #86) formed above the first reflector region; a second reflector region (fig.8 #88) formed above the active region; a first metal layer (fig.12 #1201) above the contact layer (fig.12); a second metal layer (fig.13 #1303), above the first metal layer, and connected to the contact layer (fig.13 #1303 connected to contact via mesa); and a third metal layer (fig.12 #1302/1304) formed above the second reflector layer, wherein the second metal layer partially surrounds the VCSELS (fig.13) and extends through the second reflector region, the active region, and the first reflector region (fig.13), and the second and third metal layers face the submount and are between the substrate and the submount after the VCSEL array chip is attached to the submount (as seen in fig.14b/c). Joseph further teaches the second metal layer is useful for heat sinking ([0255]), but does not teach the second metal layer to be ring shaped and completely surround each of the plurality of VCSEL structures, respectively. Izumiya teaches a related VCSEL array (fig.15/16), which forms the mesas in a connected manner (fig.16 via #102) and which includes a ring-shaped metal layer completely surround each of the plurality of VCSEL structures, respectively (fig.15/16 #460, note can also include #112). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the device of Joseph to make the second metal layer ring shaped and completely surround each of the VCSEL devices, respectively, by more fully etching around each mesa in order to more fully sink heat from the mesas (Izumiya, [0092, 94, 95]).
Joseph does not teach a multijunction active region. Dummer teaches a VCSEL array (fig.9) which makes use of a multijunction active region including a plurality of multiple-quantum-well (MQW) active regions (fig.13, [0106-109]). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to replace the active region of Joseph with the multijunction active region including a plurality of multiple-quantum-well (MQW) active regions taught by Dummer in order to improve efficiency (Dummer, [0111]).
With respect to claim 16, Joseph teaches the first reflector region and the second reflector region each comprise a Distributed Bragg Reflector (DBR) structure ([0139]).
With respect to claim 17, Jospeh, as modified, teaches the device outlined above, but does not teach the embodiment to make use of a plurality of lenses formed on a surface of the substrate. Joseph teaches an additional embodiment (fig.22) which uses lens (fig.22 #257s) formed on a surface of the substrate. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the initial embodiment of Joseph to include lens formed on a surface of the substrate as taught by the later embodiment of Joseph in order to control the path of the output light.
With respect to claim 18, Joseph teaches a fourth metal layer (fig.14b #1404/1406 leftmost) electrically connected to the second metal layer (fig.14b via solder + plating layer and via semiconductor structure) and located outside the first chip region (not in emitter/trench area).
With respect to claim 19, Joesph teaches the second metal layer is formed on the first metal layer (fig.13 #1303 on, as in close proximity with, #1201)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Please see the previously included pto892 form for a list of related art.
US 9065235 is noted as providing similar teachings to Joseph outlined above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOD THOMAS VAN ROY whose telephone number is (571)272-8447. The examiner can normally be reached M-F: 8AM-430PM.
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/TOD T VAN ROY/ Primary Examiner, Art Unit 2828