Prosecution Insights
Last updated: May 28, 2026
Application No. 17/921,259

DISPLAY DEVICE AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Oct 25, 2022
Priority
May 08, 2020 — JP 2020-082762 +1 more
Examiner
CHEEK, EDWARD RHETT
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
52 granted / 64 resolved
+13.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
19 currently pending
Career history
95
Total Applications
across all art units

Statute-Specific Performance

§103
87.2%
+47.2% vs TC avg
§102
1.4%
-38.6% vs TC avg
§112
8.7%
-31.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 64 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive. Applicant’s arguments (Applicant’s Remarks pages 7-10) correctly observe that the disclosure of US 20140240370 A1 (Sakairi et al) alone does not teach the amended limitation “the connection unit includes a semiconductor layer and a semiconductor compound layer”. However, as was discussed regarding claim 3 in the Office action mailed 11/17/2025, the disclosure of US 20100117072 A1 (Ofuji et al) teaches a structure that would have led a person of ordinary skill in the art to modify the device of Sakairi in a manner such that the amended limitation of claim 1 is met. Accordingly, claim 1 is found obvious in view of the teaching of the prior art of record. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1-5, 10, 12-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20140240370 A1 (Sakairi et al hereinafter Sakairi) in view of US 20100117072 A1 (Ofuji et al hereinafter Ofuji). Regarding claim 1, Sakairi discloses a display device (the device of FIG. 1 ¶ [0017]) comprising: a drive substrate (FIG. 1, silicon substrate layer 13A is understood to constitute a drive substrate ¶ [0077]) including a first surface (FIG. 1, surface S1 ¶ [0066]) and a second surface (FIG. 1, lower surface of silicon substrate layer 13A ¶ [0077]); and a plurality of light emitting elements (FIG. 1, a plurality of pixels include light emitting sections 20 on surface S1, one being shown in the cross-sectional view ¶ [0066-0068]) on the first surface, wherein the drive substrate includes: a plurality of drive transistors (FIG. 1, drive transistor TR2 are on lower surface of silicon substrate layer 13A, which drives light emitting section 20 ¶ [0066]), on the second surface, drives a plurality of the light emitting elements, respectively; a plurality of through electrodes (FIG. 1, an upper portion of penetrating electrode 13V which penetrates between surface S1 and lower surface of silicon substrate layer 13A ¶ [0078]) that penetrates between the first surface and the second surface; and a plurality of connection units (FIG. 1, a lower portion of penetrating electrode 13V, sidewalls of which are on edges of the lower surface of silicon substrate layer 13A) on the second surface, wherein each of the plurality of connection units connects a diffusion layer (FIG. 1, source-drain region 132A is a diffusion layer connected to the upper portion of through electrode 13V via the lower portion of penetrating electrode 13V ¶ [0077-0078]) of each of the plurality of drive transistors with each of the plurality of through electrodes, and the connection unit is includes a semiconductor layer (lower portion of penetrating electrode 13V being formed of polysilicon, it is a semiconductor layer with conductive properties ¶ [0078]) and a layer (FIG. 1, wire 121 ¶ [0078]). Sakairi does not teach that the layer is a semiconductor compound layer. However, Ofuji discloses a display device (Abstract) comprising a transistor and wiring (source, drain, and gate electrodes, and conductive lines ¶ [0079]), wherein it is noted that the wiring may be formed of a metal silicide (conductive lines may be formed of a metal silicide such as WSi ¶ [0079]). Sakairi and Ofuji both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Sakairi in view of Ofuji such that the wire 121 of Sakairi is formed of a metal silicide, and consequently the layer is a semiconductor compound layer, in order to provide a known material for the layer suitable for its intended purpose which may be cost-effective based on changing materials costs and market conditions. Regarding claim 2, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and further discloses that the semiconductor layer is a polysilicon layer (lower portion of penetrating electrode 13V being formed of polysilicon, Sakairi ¶ [0078]), and the semiconductor compound layer is a silicide layer (in view of Ofuji ¶ [0079], the wire 121 of Sakairi FIG. 1 may be formed of WSi, a silicide materal). Regarding claim 3, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above, and further discloses that the semiconductor compound layer of the connection unit (Sakairi FIG. 1, wire 121 ¶ [0078], being WSi in view of Ofuji ¶ [0079]) is on the semiconductor layer of the connection unit (FIG. 1, wire 121 is provided on the bottom of the semiconductor layer portion of penetrating electrode 13V; FIG. 4 of the present application has an analogous “on the bottom” configuration). Regarding claim 4, Sakairi in view of Ofuji discloses the limitations of claim 3 as detailed above, and further discloses that the semiconductor layer is a polysilicon layer (lower portion of penetrating electrode 13V being formed of polysilicon, Sakairi ¶ [0078]), and the semiconductor compound layer is a silicide layer (wire 121 of Sakairi is formed of a metal silicide in view of Ofuji ¶ [0079]). Regarding claim 5, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and Sakairi further discloses that a surface of the diffusion layer is non-silicide (FIG. 1, the diffusion layer being source/drain region 132A, which has surfaces contacting semiconductor well 133, insulating layer 13B, and conductive plug 13W5 ¶ [0099]; none of those surfaces are stated to be a silicide). Regarding claim 10, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and Sakairi further discloses that the through electrode includes polysilicon (FIG. 1, electrode 13V, the upper portion of which is considered the through electrode, is formed of polysilicon ¶ [0078]). Regarding claim 12, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and Sakairi further discloses that each of the plurality of light emitting elements is an organic light emitting diode element (FIG. 1, light emitting section 20 is formed of first electrode 21, organic layer 22, and second electrode 23; this structure is an organic light emitting diode ¶ [0082, 0111]). Regarding claim 13, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and Sakairi further discloses that the drive substrate further includes a pixel circuit (FIG. 3 shows a pixel circuit diagram for pixel drive circuit 150 in the pixel shown in FIG. 1, ¶ [0017-0019, 0068]) that corrects a threshold voltage Vth of the drive transistor and controls light emission of each of the plurality of light emitting elements (pixel drive circuit 150 is provided in a manner such that a threshold voltage of drive transistor Tr2 may be corrected and the light emission of the light emitting element may be controlled), and the pixel circuit includes the drive transistor (FIG. 3, drive transistor Tr2 is present in pixel drive circuit 150 ¶ [0066]), a signal write transistor (FIG. 3, write transistor Tr1 is present in pixel drive circuit 150 ¶ [0066]), and a capacitive element (FIG. 3, capacitor Cs is present in pixel drive circuit 150 ¶ [0071]). Regarding claim 15, Sakairi in view of Ofuji discloses an electronic device (an electronic apparatus such as that illustrated in FIG. 26 ¶ [0133-0134]) comprising: the display device according to claim 1 (the device of claim 1, disclosed by Sakairi in view of Ofuji as detailed above, may be applied in the electronic device of FIG. 26 ¶ [0134]). Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sakairi in view of Ofuji as applied to claim 1 above, and further in view of US patent publication US 20160293643 A1 (Kim et al hereinafter Kim). Regarding claim 6, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and Sakairi further discloses that the connection unit further includes a first polysilicon layer (lower portion of penetrating electrode 13V being formed of polysilicon ¶ [0078]), and a gate electrode of the drive transistor (FIG. 1, gate TG2 of drive transistor Tr2 ¶ [0077]), but does not further disclose that the gate electrode of the drive transistor includes a second polysilicon layer, and the first polysilicon layer and the second polysilicon layer include a same material. However, Kim discloses a display device (the device including circuitry 70 of FIG. 5 ¶ [0009-0013, 0042]) comprising a connection unit includes a first polysilicon layer (FIG. 5, polysilicon layer 76 at source/drain contact regions 78 is a connection unit ¶ [0041]) a gate electrode includes a second polysilicon layer (FIG. 5, polysilicon layer 76 at regions 98 and 100 serve as a gate electrode for transistor 74 ¶ [0043]), and the first polysilicon layer and the second polysilicon layer include a same material (being formed of the same polysilicon layer 76, the first and second polysilicon layers are a same polysilicon material ¶ [0039]). Sakairi and Kim both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Sakairi in view of Kim such that the gate electrode of the drive transistor includes a second polysilicon layer, and the first polysilicon layer and the second polysilicon layer include a same material, as it has been demonstrated by Kim that polysilicon is a known alternative material for forming gate electrodes which may be employed based on changing materials costs and market conditions. Regarding claim 7, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above and further discloses that the connection unit further includes a first polysilicon layer (lower portion of penetrating electrode 13V being formed of polysilicon ¶ [0078]), and a gate electrode of the drive transistor (FIG. 1, gate TG2 of drive transistor Tr2 ¶ [0077]), but does not further disclose that the gate electrode of the drive transistor includes a second polysilicon layer, and the first polysilicon layer and the second polysilicon layer include different materials. However, Kim discloses a display device (the device including circuitry 70 of FIG. 5 ¶ [0009-0013, 0042]) comprising a connection unit including a first polysilicon layer (FIG. 5, polysilicon layer 76 at source/drain contact regions 78 is a connection unit ¶ [0041]) a gate electrode including a second polysilicon layer (FIG. 5, polysilicon layer 76 at regions 98 and 100 serve as a gate electrode for transistor 74 ¶ [0043]), and the first polysilicon layer and the second polysilicon layer include different materials (the doping of polysilicon layer 76 is not uniform: region 78 is noted to have heavily doped ¶ [0041], as is region 100 ¶ [0043], but regions 98 are not heavily doped ¶ [0043], therefore being nonidentical i.e. different materials). Sakairi and Kim both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Sakairi in view of Kim such that the gate electrode of the drive transistor includes a second polysilicon layer, and the first polysilicon layer and the second polysilicon layer include different materials, as it has been demonstrated by Kim that polysilicon is a known alternative material for forming gate electrodes which may be employed based on changing materials costs and market conditions, and the doping concentrations need not be uniform throughout the polysilicon layers. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sakairi in view of Ofuji as applied to claim 1 above, and further in view of US patent publication US 20060261336 A1 (Ohnuma et al hereinafter Ohnuma). Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed above but does not explicitly teach that a channel of the drive transistor includes single crystal silicon (in FIG. 1, N-type semiconductor well region 133 includes the channel region for the drive transistor Tr2 ¶ [0077], but it is not stated whether or not N-type well region 133 includes single crystal silicon). Sakairi does teach that substrate 13A that N-type well region 133 is formed in is formed of silicon (¶ [0077]). Further, Ohnuma discloses a display device (¶ [0002] indicates the disclosure is directed to display technology) wherein a channel of a drive transistor includes single crystal silicon (¶ [0057] indicates that the active layer of transistors of the display device may be formed from a semiconductor substrate which may be either n-type or p-type single-crystal silicon). Sakairi and Ohnuma both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Sakairi in view of Ohnuma such that a channel of the drive transistor includes single crystal silicon, because Ohnuma has demonstrated that such a configuration is a known and obvious option in the art, which may be prove cost-effective based on materials costs and/or changing market conditions. Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over an alternative interpretation of the disclosure of Sakairi in view of Ofuji. Regarding claim 1, Sakairi discloses a drive substrate (FIG. 1, substrate 13 is understood to constitute a drive substrate ¶ [0077]) including a first surface (FIG. 1, surface S1 ¶ [0066]) and a second surface (FIG. 1, surface S2 ¶ [0066]); and a plurality of light emitting elements (FIG. 1, a plurality of pixels include light emitting sections 20 on surface S1, one being shown in the cross-sectional view ¶ [0066-0068]) on the first surface, wherein the drive substrate includes: a plurality of drive transistors (FIG. 1, drive transistor TR2 provided on lower surface of silicon substrate layer 13A, which drives light emitting section 20 ¶ [0066]), on the second surface, drives a plurality of the light emitting elements, respectively; a plurality of through electrodes (FIG. 1, penetrating electrode 13V which penetrates between surfaces S1 and S2 ¶ [0078]) that penetrates between the first surface and the second surface; and a plurality of connection units (FIG. 1, wire 121 and conductive plug 13W5 form a connection unit in each pixel, wherein wire 121 is on the bottom of surface S2 ¶ [0078]) on the second surface, each of the plurality of connection units connects a diffusion layer (FIG. 1, source-drain region 132A is a diffusion layer connected to penetrating electrode 13V via wire 121 ¶ [0077-0078]) of each of the plurality of drive transistors with each of the plurality of through electrodes. Under this interpretation of the disclosure of Sakairi, it is not explicitly stated that the connection unit includes a semiconductor layer and a semiconductor compound layer (the connection unit being wire 121 and conductive plug 13W5 of FIG. 1). Notably, Sakairi does not explicitly suggest suitable materials of the wire and conductive plugs, said materials not of particular importance to the disclosure of their invention. However, Sakairi does teach that penetrating electrode 13V (FIG. 1) may be formed of either tungsten or polysilicon, the latter of which is a semiconductor layer with conductive properties (¶ [0078]). A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to take into consideration the materials suggested for penetrating electrode 13V and consider them viable materials to use for the conductive plugs such as 13W5, as those materials have been shown to provide electrical connection between features of the device. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have further found it obvious to form conductive plug 13W5 of polysilicon, and consequently the connection unit is provided with a semiconductor layer, in order to provide a known material for the connection unit suitable for its intended purpose which may be cost-effective based on changing materials costs and market conditions. Sakairi does not further disclose that the connection unit is provided with a semiconductor compound layer; the material of wire 121 not of particular importance to the disclosure of their invention. However, Ofuji discloses a display device (Abstract) comprising a transistor and wiring (source, drain, and gate electrodes, and conductive lines ¶ [0079]), wherein it is noted that the wiring may be formed of a metal silicide (conductive lines may be formed of a metal silicide such as WSi ¶ [0079]). Sakairi and Ofuji both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Sakairi in view of Ofuji such that the wire 121 of Sakairi is formed of a metal silicide, and consequently the connection unit is provided with a semiconductor compound layer, in order to provide a known material for the connection unit suitable for its intended purpose which may be cost-effective based on changing materials costs and market conditions. Regarding claim 9, Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed in the alternative interpretation above and further discloses that the through electrode includes tungsten (penetrating electrode 13V may be formed of tungsten (W), Sakairi ¶ [0078]). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sakairi in view of Ofuji as applied to claim 1 in the alternative interpretation above, and further in view of US patent publication US 20080308894 A1 (Tsai et al hereinafter Tsai). Sakairi in view of Ofuji discloses the limitations of claim 1 as detailed in the alternative interpretation above, but does not further disclose that the through electrode includes single crystal silicon. However, Tsai discloses a display device (FIGS. 2 and 11, as the illustrated structure of FIG. 2 is applied in a display device ¶ [0014, 0027]) wherein conductive contact pads (FIG. 2, contact pads 110 ¶ [0029]) may be formed of a metal such as tungsten, polysilicon, or single crystal silicon interchangeably (¶ [0029]). Sakairi, Ofuji, and Tsai all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Sakairi in view of Ofuji further in view of Tsai such that the through electrode includes single crystal silicon, in order to provide a known material for the through electrode suitable for its intended purpose which may be cost-effective based on changing materials costs and market conditions. Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent US 12453243 B2. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD RHETT CHEEK whose telephone number is (571)272-3461. The examiner can normally be reached Monday - Thursday 7:30am - 5pm, Every other Friday 8:30am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.R.C./Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Oct 25, 2022
Application Filed
Nov 17, 2025
Non-Final Rejection mailed — §103
Dec 18, 2025
Response Filed
Feb 18, 2026
Final Rejection mailed — §103
Apr 08, 2026
Response after Non-Final Action
May 18, 2026
Request for Continued Examination
May 21, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
96%
With Interview (+14.3%)
3y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 64 resolved cases by this examiner. Grant probability derived from career allowance rate.

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