Prosecution Insights
Last updated: April 19, 2026
Application No. 17/921,903

DISPLAY SUBSTRATE AND DISPLAY APPARATUS

Non-Final OA §103
Filed
Oct 27, 2022
Examiner
SHEKER, RHYS PONIENTE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
3y 3m
To Grant
91%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
41 granted / 48 resolved
+17.4% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
45 currently pending
Career history
93
Total Applications
across all art units

Statute-Specific Performance

§103
59.2%
+19.2% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the Applicant Remarks filed on 02/26/2026. Currently, claims 1, 3, 4, 6-12, 14, 15, and 17-20 are pending in the application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/26/2026 has been entered. Response to Amendments Applicant' s arguments with respect to claim(s) 1, 3, 4, 6-12, 14, 15, and 17-20 have been considered. Applicant argues that the cited prior art does not teach all of the limitations of the amended independent claims. This argument is not found persuasive because the cited prior art does teach all of the limitations of the amended independent claims (see prior art rejection below). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 4, 6-12, 14, 15, and 17-20 are rejected under 35 U.S.C. 103 as being obvious over XIONG et al. (US Pub. No. 2016/0268354) in view of BI et al. (US Pub. No. 2017/0155075). Regarding independent claim 1, Xiong teaches a display substrate (Fig. 2A), comprising: a base substrate (Fig. 6, 21, ¶ [0038]) divided into a plurality of sub-pixel areas (Figs. 6 & 9, 23, ¶ [0036] teaches pixel regions 23 in-between adjacent sections of pixel definition layers 22); a first electrode layer (Figs. 1 & 6, 16, ¶ [0033], the Examiner notes that anode 16 appears to be unlabeled in Fig. 6) located on one side of the base substrate, wherein the first electrode layer comprises a plurality of first electrodes (Fig. 6, middle and right 16) located in the plurality of sub-pixel areas (Fig. 6, Xiong’s anodes 16 are at least partially located in Xiong’s pixel areas 23); a pixel definition layer (Fig. 6, 22, ¶ [0036]) located on one side of the first electrode layer facing away from the base substrate (Fig. 6), wherein the pixel definition layer comprises a plurality of pixel definition portions (Figs. 6 & 9, ¶ [0052] teaches portions of pixel definition layer 22 in between sub-pixels) configured for defining the plurality of sub-pixel areas, and a pixel definition portion located between at least one pair of two adjacent sub-pixel areas is provided with a plurality of first recessed structures (Fig. 6, 24, ¶ [0036]) arranged in an array (Fig. 9); and a common layer (Fig. 6, 25, ¶ [0036]) located on one side of the pixel definition layer facing away from the base substrate, wherein the common layer covers the plurality of pixel definition portions and the plurality of first electrodes, and the common layer is provided with at least one second recessed structure (Fig. 6, portions of 25 in recesses 24) in an area corresponding to the at least one first recessed structures; a distance between a bottom end face of the first recessed structure and a first surface is equal to a distance between a surface of the first electrode facing away from the base substrate and the first surface, wherein the first surface is a surface of the base substrate facing the plurality of first electrodes (¶ [0048] teaches that when the depth D of recess 24 larger than or equal to 2 μm, leakage current can be reduced. In the embodiments of Figs. 3-4 & 6, it is shown that the depth D of recesses 24 can be both above or below the height of the anodes 16. The depth D of Xiong’s recesses 24 can only be either above, below, or at a same height as the height of Xiong’s anodes 16 on top of Xiong’s planarization layer 27. Therefore, it would have been obvious to try by one of ordinary skill in the art to have the depth D of Xiong’s recesses 24 be at a same height as Xiong’s anodes with a reasonable expectation of success. Further, the embodiments of Xiong Figs. 3 & 4 teaches the selective removal of portions of anode 16 in order to not interfere with the layers within recess 24); an orthographic projection of the first recessed structure on the base substrate is not in contact with the sub-pixel area (Figs. 3-4 & 6, Xiong’s recesses 24 do not vertically overlap with the space occupied by Xiong’s pixel regions 23, which are defined in-between adjacent sections of Xiong’s pixel definition layer 22.). However, Xiong does not explicitly teach that a space is provided between two adjacent first recessed structures in a column direction of the array, spaces in one column correspond to first recessed structures in another column adjacent to the one column, and a connecting line between a center of the space in the one column and a center of the corresponding first recessed structure in the another column adjacent to the one column are parallel to a row direction of the array. However, Bi is a pertinent art that teaches that a space (Fig. 11, space occupied by 615, ¶ [0054]) is provided between two adjacent first recessed structures (Spaces “A” in between photo spacers 615 in annotated Figure below. The spaces in-between Bi’s photo spacers in the plan view correspond to recesses in those photo spacers in the cross-sectional view (see spaces/recess in between photo spacers 215 in Figs. 3 & 6)) in a column direction of the array, spaces in one column correspond to first recessed structures in another column adjacent to the one column (see annotated figure below), and a connecting line between a center of the space in the one column and a center of the corresponding first recessed structure in the another column adjacent to the one column are parallel to a row direction of the array (Center of spaces A in between Bi’s photo spacers correspond to photo spacers in a different column in a horizontal direction ). PNG media_image1.png 638 440 media_image1.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the arrangement of Xiong’s recesses to be staggered according to the teaching of Bi (Fig. 11) in order to avoid color mixing (Bi ¶ [0105]). Regarding claim 3, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong teaches a barrier portion (Figs. 6 & 9, ¶ [0052] teaches portions of pixel definition layer 22 in between sub-pixels) located between two adjacent sub-pixel areas emitting light of different colors (Fig. 9, R + G, ¶ [0050]) is provided with a plurality of first recessed structures (Fig. 9, 24, ¶ [0052]). Regarding claim 4, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong teaches a barrier portion (Figs. 6 & 9, ¶ [0052] teaches portions of pixel definition layer 22 in between sub-pixels) located between two adjacent sub-pixel areas emitting light of a same color (Fig. 9, R, ¶ [0050]) is provided with at a plurality of first recessed structures (Fig. 9, 24, ¶ [0052]). Regarding claim 6, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong teaches the plurality of first recessed structures have a same depth (Fig. 6, D, ¶ [0048]). Regarding claim 7, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong teaches the plurality of first recessed structures have a same shape (Fig. 6). Regarding claim 8, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong modified by Bi teaches that the plurality of first recessed structures are arranged in a staggered manner (Spaces A in annotated Bi Fig. 11 above are arranged in a staggered manner) in a direction of a connecting line between the two adjacent sub-pixel areas. Regarding claim 9, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong teaches a light-emitting layer (Figs. 2A & 6, 253, ¶ [0038], the Examiner notes that light emitting layer 253 appears to be unlabeled in Fig. 6) located on the one side of the pixel definition layer facing away from the base substrate; wherein the common layer (Fig. 6, 25, ¶ [0036]) comprises a first common layer (Fig. 6, 251, ¶ [0038]) located between the light-emitting layer and the pixel definition layer, and a second common layer (Fig. 6, 252, ¶ [0038]) located on one side of the light- emitting layer facing away from the base substrate. Regarding claim 10, Xiong modified by Bi teaches the display substrate according to claim 9, and Xiong teaches that the plurality of first electrodes are anodes (Figs. 1 & 6, 16, ¶ [0033], the Examiner notes that anode 16 appears to be unlabeled in Fig. 6); the first common layer comprises a hole injection layer and/or a hole transport layer (Fig. 6, 251, ¶ [0038] teaches a hole transport layer); and the second common layer (Fig. 6, 252, ¶ [0038] teaches an electron transport layer) comprises an electron injection layer and/or an electron transport layer. Regarding claim 11, Xiong modified by Bi teaches the display substrate according to claim 1, and Xiong teaches a second electrode layer (Figs. 2A & 6, 254, ¶ [0038], the Examiner notes that cathode 254 appears to be unlabeled in Fig. 6) located on one side of the common layer (Fig. 6, 25, ¶ [0036]) facing away from the base substrate; wherein the second electrode layer is provided with a third recessed structure (Fig. 6, portions of 254 in recess 24) at a position corresponding to the second recessed structure (Fig. 6, portions of 25 in recesses 24). Regarding independent claim 12, Xiong teaches a display apparatus, comprising a display substrate, wherein the display substrate (Fig. 2A) comprises: a base substrate (Fig. 6, 21, ¶ [0038]) divided into a plurality of sub-pixel areas (Figs. 6 & 9, 23, ¶ [0036] teaches pixel regions 23 in-between adjacent sections of pixel definition layers 22); a first electrode layer (Figs. 1 & 6, 16, ¶ [0033], the Examiner notes that anode 16 appears to be unlabeled in Fig. 6) located on one side of the base substrate, wherein the first electrode layer comprises a plurality of first electrodes (Fig. 6, middle and right 16) located in the plurality of sub-pixel areas (Fig. 6, Xiong’s anodes 16 are at least partially located in Xiong’s pixel areas 23); a pixel definition layer (Fig. 6, 22, ¶ [0036]) located on one side of the first electrode layer facing away from the base substrate (Fig. 6), wherein the pixel definition layer comprises a plurality of pixel definition portions (Figs. 6 & 9, ¶ [0052] teaches portions of pixel definition layer 22 in between sub-pixels) configured for defining the plurality of sub-pixel areas, and a pixel definition portion located between at least one pair of two adjacent sub-pixel areas is provided with a plurality of first recessed structures (Fig. 6, 24, ¶ [0036]) arranged in an array (Fig. 9); and a common layer (Fig. 6, 25, ¶ [0036]) located on one side of the pixel definition layer facing away from the base substrate, wherein the common layer covers the plurality of pixel definition portions and the plurality of first electrodes, and the common layer is provided with at least one second recessed structure (Fig. 6, portions of 25 in recesses 24) in an area corresponding to the at least one first recessed structures; a distance between a bottom end face of the first recessed structure and a first surface is equal to a distance between a surface of the first electrode facing away from the base substrate and the first surface, wherein the first surface is a surface of the base substrate facing the plurality of first electrodes (¶ [0048] teaches that when the depth D of recess 24 larger than or equal to 2 μm, leakage current can be reduced. In the embodiments of Figs. 3-4 & 6, it is shown that the depth D of recesses 24 can be both above or below the height of the anodes 16. The depth D of Xiong’s recesses 24 can only be either above, below, or at a same height as the height of Xiong’s anodes 16 on top of Xiong’s planarization layer 27. Therefore, it would have been obvious to try by one of ordinary skill in the art to have the depth D of Xiong’s recesses 24 be at a same height as Xiong’s anodes with a reasonable expectation of success. Further, the embodiments of Xiong Figs. 3 & 4 teaches the selective removal of portions of anode 16 in order to not interfere with the layers within recess 24); an orthographic projection of the first recessed structure on the base substrate is not in contact with the sub-pixel area (Figs. 3-4 & 6, Xiong’s recesses 24 do not vertically overlap with the space occupied by Xiong’s pixel regions 23, which are defined in-between adjacent sections of Xiong’s pixel definition layer 22.). However, Xiong does not explicitly teach that a space is provided between two adjacent first recessed structures in a column direction of the array, spaces in one column correspond to first recessed structures in another column adjacent to the one column, and a connecting line between a center of the space in the one column and a center of the corresponding first recessed structure in the another column adjacent to the one column are parallel to a row direction of the array. However, Bi is a pertinent art that teaches that a space (Fig. 11, space occupied by 615, ¶ [0054]) is provided between two adjacent first recessed structures (Spaces “A” in between photo spacers 615 in annotated Figure below. The spaces in-between Bi’s photo spacers in the plan view correspond to recesses in those photo spacers in the cross-sectional view (see spaces/recess in between photo spacers 215 in Figs. 3 & 6)) in a column direction of the array, spaces in one column correspond to first recessed structures in another column adjacent to the one column (see annotated figure below), and a connecting line between a center of the space in the one column and a center of the corresponding first recessed structure in the another column adjacent to the one column are parallel to a row direction of the array (Center of spaces A in between Bi’s photo spacers correspond to photo spacers in a different column in a horizontal direction ). PNG media_image1.png 638 440 media_image1.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the arrangement of Xiong’s recesses to be staggered according to the teaching of Bi (Fig. 11) in order to avoid color mixing (Bi ¶ [0105]). Regarding claim 14, Xiong modified by Bi teaches the display substrate according to claim 12, and Xiong teaches a barrier portion (Figs. 6 & 9, ¶ [0052] teaches portions of pixel definition layer 22 in between sub-pixels) located between two adjacent sub-pixel areas emitting light of different colors (Fig. 9, R + G, ¶ [0050]) is provided with a plurality of first recessed structures (Fig. 9, 24, ¶ [0052]). Regarding claim 15, Xiong modified by Bi teaches the display substrate according to claim 12, and Xiong teaches a barrier portion (Figs. 6 & 9, ¶ [0052] teaches portions of pixel definition layer 22 in between sub-pixels) located between two adjacent sub-pixel areas emitting light of a same color (Fig. 9, R, ¶ [0050]) is provided with at a plurality of first recessed structures (Fig. 9, 24, ¶ [0052]). Regarding claim 17, Xiong modified by Bi teaches the display substrate according to claim 12, and Xiong teaches the plurality of first recessed structures have a same depth (Fig. 6, D, ¶ [0048]). Regarding claim 18, Xiong modified by Bi teaches the display substrate according to claim 12, and Xiong teaches the plurality of first recessed structures have a same shape (Fig. 6). Regarding claim 19, Xiong modified by Bi teaches the display substrate according to claim 12, and Xiong modified by Bi teaches that the plurality of first recessed structures are arranged in a staggered manner (Spaces A in annotated Bi Fig. 11 above are arranged in a staggered manner) in a direction of a connecting line between the two adjacent sub-pixel areas. Regarding claim 20, Xiong modified by Bi teaches the display substrate according to claim 12, and Xiong teaches a light-emitting layer (Figs. 2A & 6, 253, ¶ [0038], the Examiner notes that light emitting layer 253 appears to be unlabeled in Fig. 6) located on the one side of the barrier layer facing away from the base substrate; wherein the common layer (Fig. 6, 25, ¶ [0036]) comprises a first common layer (Fig. 6, 251, ¶ [0038]) located between the light-emitting layer and the barrier layer, and a second common layer (Fig. 6, 252, ¶ [0038]) located on one side of the light- emitting layer facing away from the base substrate. Cited Prior Art The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHYS P. SHEKER whose telephone number is (703)756-1348. The examiner can normally be reached Monday - Friday 7:30 am to 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.P.S./ Examiner, Art Unit 2813 /STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Oct 27, 2022
Application Filed
Jul 21, 2025
Non-Final Rejection — §103
Oct 20, 2025
Response Filed
Nov 21, 2025
Final Rejection — §103
Feb 26, 2026
Request for Continued Examination
Mar 02, 2026
Response after Non-Final Action
Mar 16, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Mar 10, 2026
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2y 5m to grant Granted Feb 03, 2026
Patent 12543436
DISPLAY PANEL AND PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE
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Patent 12527169
OLED DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
91%
With Interview (+5.8%)
3y 3m
Median Time to Grant
High
PTA Risk
Based on 48 resolved cases by this examiner. Grant probability derived from career allow rate.

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