DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/20/2025 has been entered.
Response to Arguments
Applicant's arguments of 11/20/2025 with respect to claims 1, 3-11, and 13-20 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 3, 4, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN107910352 A - hereinafter Li) in view of Tanada (US 20130248899 A1 – hereinafter Tanada) and Jang et al. (US 20210202675 A1 – hereinafter Jang).
Regarding independent claim 1, Li teaches:
(Currently Amended) A display substrate, comprising:
a substrate (10 – Fig. 4c – [0031] – “substrate 10”), having a display area
([0025] – “display area” – hereinafter ‘AA’) and a peripheral area ([0025] – “non-display area” – hereinafter ‘BB’) surrounding the display area (AA) ;
a plurality of initialization signal lines (100 – Fig. 2 – [0023] – “a plurality of
power lines 100 extending along the row direction”), in the display area (AA) of the substrate (10), wherein the plurality of initialization signal lines (100) extend in a first direction (row direction – Fig. 2 – [0023] – “a plurality of power lines 100 extending along the row direction” – this corresponds to the first direction, hereinafter ‘F1’);
an interlayer insulating layer (Fig. 4c – annotated, see below – [0035] – “the
first interlayer insulating layer and the second interlayer insulating layer” – hereinafter ‘IL’), on a side of the plurality of initialization signal lines (100) facing away from the substrate (10); and
a plurality of auxiliary signal lines (200 – Fig. 2 – [0023] – “a plurality of
compensation power lines 200”), on a side of the interlayer insulating layer (IL)
facing away from the substrate (10) and in the display area (AA), wherein the plurality of auxiliary signal lines (200) extend in a second direction ([0004] – “column direction” – hereinafter ‘F2’), and the first direction (F1) is different from the second direction (F2 – obvious that row and columns are different directions);
wherein intersections of the plurality of auxiliary signal lines (200) and the
plurality of initialization signal lines (100 – Fig. 2 – [0023] – “power lines 100” – these correspond to initialization signal lines) each has one first, the plurality of auxiliary signal lines (200) and the plurality of initialization signal lines (100) are electrically connected to each other through first vias (300) (300 – Fig. 4c – [0023] – “power lines 100 are electrically connected to the corresponding compensation power lines 200 through the vias 300”), and the first vias (300) run through the interlayer insulating layer (IL);
wherein the display substrate further comprises: a first auxiliary bus and a second auxiliary bus, in the peripheral area and extending in the first direction; wherein
the first auxiliary bus and the second auxiliary bus are connected at two ends of each auxiliary signal line respectively, and
the first auxiliary bus and the second auxiliary bus are electrically connected with the plurality of auxiliary signal lines respectively.
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Li does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Tanada teaches
wherein intersections of the plurality of auxiliary signal lines and the plurality
of initialization signal lines each has one first via (Tanada (US 20130248899 A1 – hereinafter Tanada) (tan (Fig. 2 – {[0034] – “a pixel portion 11 formed on a substrate 10 comprises current supply lines 12a to 12i arranged in columns. Wirings 13a to 13f are arranged so as to intersect with the current supply lines 12a to 12i arranged in columns, and the wirings 13a to 13f are connected to the current supply lines 12a to 12i at intersections of the wirings 13a to 13f and the current supply lines 12a to 12i. Further, the current supply lines 12a to 12i are connected to current input terminals 14”}, {(80 – Fig. 1A – [0028] – “current supply lines 76a to 76i, and connected to a second current input terminal 73 or 75 via a node 78 or 80” – this shows how a node connecting two wires is annotated in a figure} – therefore, in Fig. 2, each black dot is a node connecting each intersection of the lines).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the via at each intersection structure of Tanada into Li.
An ordinary artisan would have been motivated to use the know technique of Tanada in the manner set forth above to produce the predictable results of [0013] – “Drop in voltage can be suppressed in such a manner, and thus a display device in which display variations due to voltage drop are suppressed can be achieved.”
Li and Tanada do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Jang teaches
wherein the display substrate (100 – Fig. 12 – [0250] – “first substrate 100 can be referred to as a display substrate”) further comprises: a first auxiliary bus (Fig. 9C annotated, see below – [0075] – “closed loop line CLL” – a closed loop has a top portion and a bottom portion in the X direction, hereinafter ‘CLL-top’) and a second auxiliary bus (Fig. 9C annotated, see below – [0075] – “closed loop line CLL” – a closed loop has a top portion and a bottom portion in the X direction, hereinafter ‘CLL-bottom’), in the peripheral area ([0075] – “disposed at an edge portion of the substrate 10 to surround the display portion AA” – this describes the peripheral area) and extending in the first direction (X – Fig. 9C annotated, see below – [0061] – “first direction X”); wherein
the first auxiliary bus (CLL-top) and the second auxiliary bus (CLL-bottom) are connected at two ends of each auxiliary signal line (CVL – Fig. 9C – [0053] – “plurality of pixel common voltage lines CVL” – this is a signal line) respectively, and
the first auxiliary bus (CLL-top) and the second auxiliary bus (CLL-bottom) are electrically connected with the plurality of auxiliary signal lines (CVL – Fig. – [0077] – “The at least one closed loop line CLL according to an embodiment can be disposed to intersect with the other side of each of the plurality of pixel common voltage lines CVL disposed at the other edge portion of the substrate 10 and can be electrically connected to at least one of the other sides of the plurality of pixel common voltage lines CVL at the other edge portion of the substrate 10. In this case, one side and the other side of each of the plurality of pixel common voltage lines CVL can be electrically connected to the at least one closed loop line CLL”) respectively.
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the auxiliary bus structure
taught by Jang into Li and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of reducing static
electricity damaging the device as Jang states [0076] - "Accordingly, the at least one
closed loop line CLL can discharge static electricity, flowing in from the outside, to the
pixel common voltage pad CVP and/or the pixel common voltage line CVL, and thus,
can prevent a defect caused by the static electricity" and having redundant signal lines
in the event one of them is damaged.
Regarding claim 3, Li as modified by Tanada and Jang, teaches claim 1 from which claim 3 depends. Li further teaches
plurality of initialization signal lines (100).
Li and Tanada do not expressly disclose the other limitations of claim 3.
However, in an analogous art, Jang teaches
(Currently Amended) The display substrate according to claim 1
third auxiliary bus and a fourth auxiliary bus, in the peripheral area (BB) and
extending in the second direction (Y - Fig. 14 - [0061] - "second direction Y");
wherein
the third auxiliary bus and the fourth auxiliary bus are located at two ends
of each of the plurality of initialization signal lines respectively, and the third auxiliary bus and the fourth auxiliary bus are electrically connected with the plurality of initialization signal lines respectively ([0181] - "The light emitting display apparatus according to an embodiment of the present disclosure can further include a conductive metal line CML disposed between the at least one closed loop line CLL and the pad connection lines PCL 1 to PCL4" - multiple CLL is interpreted as third and fourth auxiliary bus that meets the description).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the third and fourth auxiliary
bus structure taught by Jang into Li and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 4, Li, as modified by Tanada, and Jang, teaches claim 3 from which claim 4 depends. Li and Tanada do not expressly disclose the limitations of claim 4.
However, in an analogous art, Jang teaches
(Original) The display substrate according to claim 3, wherein the third
auxiliary bus and the fourth auxiliary bus are in a same layer (11d - Fig. 4 - [0147]
- "at least one closed loop line CLL can be disposed on the passivation layer 11 d to
surround the display portion AA and can intersect with the pad connection lines PCL 1 to PCL4 at the pad part PP") as the plurality of initialization signal lines (PCL4).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the third and fourth auxiliary
bus structure taught by Jang into Li and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of simplifying
manufacturing and reducing cost by not adding additional and separate layers.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 11, Li, as modified by Tanada, and Jang, teaches claim 1 from which claim 11 depends. Li further teaches
(Previously Presented) A display apparatus ([0002] – “present
invention relates to the field of display technology, and in particular to an organic light emitting display panel and a display device”), comprising the display substrate (10 – Fig. 4c – [0031] – “substrate 10”) of claim 1.
Regarding claim 13, Li, as modified by Tanada and Jang, teaches claim 11 from which claim 13 depends. Li further teaches
plurality of initialization signal lines (100).
Li and Tanada do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Jang teaches
(Currently Amended) The display apparatus according to claim 11,
wherein the display substrate (10 - fig. 4 - [0053] - "substrate 10") further comprises:
a third auxiliary bus and a fourth auxiliary bus, in the peripheral area (BB)
and extending in the second direction (Y - Fig. 14 - [0061] - "second direction Y");
wherein
the third auxiliary bus and the fourth auxiliary bus are located at two ends
of each of the plurality of initialization signal lines respectively, and
the third auxiliary bus and the fourth auxiliary bus are electrically
connected with the plurality of initialization signal lines respectively ([0181] - "The
light emitting display apparatus according to an embodiment of the present disclosure
can further include a conductive metal line CML disposed between the at least one
closed loop line CLL and the pad connection lines PCL 1 to PCL4" - multiple CLL is
interpreted as third and fourth auxiliary bus that meets the description).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the third and fourth auxiliary
bus structure taught by Jang into Li and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 14, Li, as modified by Tanada and Jang, teaches claim 13 from which claim 14 depends. Li and Tanada do not expressly disclose the limitations of claim 14.
However, in an analogous art, Jang teaches
(Previously Presented) The display apparatus according to claim 13, wherein the third auxiliary bus and the fourth auxiliary bus are in a same layer (11d - Fig. 4 - [0147] - "at least one closed loop line CLL can be disposed on the passivation layer 11d to surround the display portion AA and can intersect with the pad connection lines PCL 1 to PCL4 at the pad part PP") as the plurality of initialization signal lines (PCL4).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the third and fourth auxiliary
bus structure taught by Jang into Li and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result as stated above in claim 4.
Claims 5-10 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Tanada, Jang, and Woo et al. (US 20210050536 A1 - hereinafter Woo).
Regarding claim 5, Li, as modified by Tanada and Jang, teaches claim 1 from which Claim 5 depends. Li and Tanada do not expressly disclose the limitations of claim 5.
However, in an analogous art, Jang teaches
at least one of the first auxiliary bus (CLL - Fig. 9c - [0075] - "closed loop line
CLL") and the second auxiliary bus is in a same layer ({11 - Fig. 4- [0117] - "circuit
layer 11" - this contains layers 11a, 11b, 11c, and 11d}, {[0204] - "conductive metal
line CML disposed in the buffer layer 11a"}, {[0124] - "The interlayer insulation layer 11c
can be disposed on the substrate 10 to cover the gate electrode GE and the active layer
ACT. The interlayer insulation layer 11c can electrically insulate (or isolate) the gate
electrode GE and the source/drain electrodes S01 and S02"}) as the driving gate (GE
- [0124] - "gate electrode GE").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the auxiliary bus structure
taught by Jang into Li and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of simplifying
manufacturing and reducing cost by not adding additional and separate layers.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Li, Tanada, and Jang do not expressly the other limitations of claim 5.
However, in an analogous art, Woo teaches
(Currently Amended) The display substrate (01) according to claim 1 (DA - Fig. 4- [0057] - "display area DA") further comprises a plurality of sub-pixels ([0057] - "The display area DA includes a plurality of pixels"); at least one of the plurality of sub-pixels ([0066] - "pixel in the display area DA" - Fig. 4 is a pixel) comprises a driving thin film transistor (Fig. 4 annotated, see below - [0077] - "thin film transistor'' – hereinafter '21'), a connecting electrode (CNE - Fig. 4 - [0087] - "connecting electrode CNE'') and a storage capacitor (Fig. 4 annotated, see below - [0077] - "storage capacitor'' - hereinafter '34');
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the driving thin film transistor (21) comprises:
a driving active layer (105 - Fig. 4 -[0075] - "semiconductor layer 105"),
on the substrate (101 - Fig. 4 - [0076] - "display substrate 101 ");
a driving gate (GE - Fig. 4 - [0077] - "gate electrode GE"), on a side of the driving active layer (105) facing away from the substrate (101);
a gate insulating layer (112 - Fig. 4- [0078] - "insulating layer 112"), on a side of the driving gate (GE) facing away from the substrate (101);
an interlayer dielectric layer (113 - Fig. 4 - [0080] - "insulating layer 113"), on a side of the gate insulating layer (112) facing away from the substrate (101); and
a driving source (SE - Fig. 4 - [0081] - "source electrode SE") and a driving drain (DE - Fig. 4- [0081] - "drain electrode DE"), on a side of the interlayer dielectric layer (113) facing away from the substrate (101);
the connecting electrode (CNE) is on a side of the driving source (SE) and the driving drain (DE) facing away from the substrate (101);
the storage capacitor (34) comprises a first capacitive electrode (CE1 - Fig.
4 - [0079] - "first electrode CE 1 of the storage capacitor'') and a second capacitive electrode (CE2- Fig. 4- [0079] - "second electrode CE2 of the storage capacitor''), the first capacitive electrode (CE1) is in a same layer (120 - Fig. 4- [0077] - "conductive layer 120 may include a gate electrode GE of a thin film transistor, a first electrode CE1 of a storage capacitor") as the driving gate (GE), and the second capacitive electrode (CE2) is arranged between the gate insulating layer (112) and the interlayer dielectric layer (113);
the plurality of initialization signal lines (SL - [0082] - "Although not shown in
the drawings, the third conductive layer 140 may further include a signal line disposed in
the pad area PA. The signal line may be disposed to overlap the connecting line of the
first conductive layer 120 in a thickness direction of the display substrate 101 or the
third direction DR3 and may be electrically connected to the connecting line through an
exposed part of the second insulating layer 112" - hereinafter 'SL', this is a signal line,
there are a plurality of pixels therefore a plurality of SL lines) are in a same layer (140 -
Fig. 4 - [0081] - "conductive layer 140 may include a source electrode SE, a drain
electrode, DE, and a high-potential voltage electrode ELVDDE") as the driving source
(SE) and the driving drain (DE);
the plurality of auxiliary signal lines (DL - Fig 4 - [0085] - "data line DL-this
is a signal line, there are a plurality of pixels therefore a plurality of DL lines) are in a
same layer (150 - Fig. 4- [0085] - "conductive layer 150 may include a data line DL, a
connecting electrode CNE, and a high-potential voltage line ELVDDL") as the
connecting electrode (CNE).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the display area structure
as taught by Woo into Li, Tanada, and Jang.
An ordinary artisan would have been motivated to use the known technique of
Woo in the manner set forth above to produce the predictable result of simplifying
manufacturing and reducing cost by not adding additional and separate layers.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 6, Li, as modified by Tanada, Jang, and Woo, teaches claim 5 from which claim 6 depends. Li, Tanada, and Jang, do not expressly disclose the limitations of claim 6.
However, in an analogous art, Woo teaches
(Original) The display substrate according to claim 5, further comprising: a
plurality of power signal lines (ELVDDL - Fig. 4 - [0085] - "conductive layer 150 may
include a data line DL, a connecting electrode CNE, and a high-potential voltage line
ELVDDL" - there are a plurality of pixels therefore a plurality of ELVDDL lines) in the
display area (DA); wherein:
the plurality of power signal lines (ELVDDL) extend in the second direction
(DR1 - Fig. 1 - [0058] - "direction DR1"); and
the power signal lines (ELVDDL) and the auxiliary signal lines (DL) are in a
same layer (150 - Fig. 4 - [0085] - "conductive layer 150 may include a data line DL, a
connecting electrode CNE, and a high-potential voltage line ELVDDL), and the power
signal lines (ELVDDL) and the auxiliary signal lines (DL) are arranged at intervals
(woo ([0057] - "The display area DA includes a plurality of pixels" - since the is a
plurality of pixel in the display area, they must be arranged at intervals).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the power and signal line
structure as taught by Woo into Li, Tanada, and Jang.
An ordinary artisan would have been motivated to use the known technique of
Woo in the manner set forth above to produce the predictable result as stated above in claim 5.
Regarding claim 7, Li, as modified by Tanada, Jang, and Woo, teaches claim 6 from which claim 7 depends. Li, Tanada, and Woo, do not expressly disclose the limitations of claim 7.
However, in an analogous art, Jang teaches
(Original) The display substrate according to claim 6, further comprising: a
first power bus (PL1 - Fig. 14 annotated, see below - [0293] - "driving power lines PL"
- hereinafter 'PL 1') and a second power bus (PL2 - Fig. 14 annotated, see below -
[0293] - "driving power lines PL" - hereinafter 'PL2'), in the peripheral area ([0075] -
"disposed at an edge portion of the substrate 10 to surround the display portion AA" -
this describes the peripheral area) and extending in the first direction (X - Fig. 14 -
[0061] - "first direction X");
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wherein:
the first power bus (PL1) and the second power bus (PL2) are located at
two ends (Fig. 14 shows this) of each power signal line respectively (PSL - Fig. 14
- [0293] - "power sharing lines PSL"); and
the first power bus (PL1) and the second power bus (PL2) are electrically
connected ([0293] - "power lines PL among the plurality of pixel driving power lines PL
can be connected to a plurality of power sharing lines PSL") with the plurality of
power signal lines (PSL) respectively.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the bus structure taught by
Jang into Li, Tanada, and Woo.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of suppling power
to the elements as required without having to make separate supply lines for each. This
results in reduced manufacturing costs.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 8, Li, as modified by Tanada, Jang, and Woo, teaches claim 7 from which claim 8 depends. Li, Tanada, and Woo, do not expressly disclose the limitations of claim 8.
However, in an analogous art, Jang teaches
(Original) The display substrate according to claim 7, wherein at least one
of the first power bus (PL1) and the second power bus (PL2) is in a same layer (11 - Figs. 17 and 19 - Fig. 17 shows PL in layer 11, Fig. 19 shows PSL in layer 11) as the plurality of power signal lines (PSL).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the bus structure taught by
Jang into Li, Tanada, and Woo.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of suppling power
to the elements as required without having to make separate supply lines for each. This
results in reduced manufacturing costs.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 9, Li, as modified by Tanada, Jang, and Woo, teaches claim 6 from which claim 9 depends. Li further teaches
the plurality of power signal lines and the plurality of power compensation lines
are electrically connected to each other through second vias, the second vias run through the interlayer insulating layer and the interlayer dielectric layer, and orthographic projections of the second vias on the substrate are located at intersections of orthographic projections of the plurality of power signal lines on the substrate and orthographic projections of the plurality of power compensation lines on the substrate ([0026] - "In a specific implementation, the number of vias corresponding to each row of power lines can be calculated and
determined through simulation, so that the resistance of different power lines connected
in parallel with the corresponding power compensation lines can be the same within the
allowable error range" - though not specific, this is the concept of connecting different
lines by using vias as connection paths).
Li, Tanada, and Woo do not expressly disclose
(Previously Presented) The display substrate according to claim 6, further
comprising: a plurality of power compensation lines in the display area and
extending in the first direction;
wherein:
the plurality of power compensation lines are in a same layer as the second
capacitive electrode;
the plurality of power signal lines and the plurality of power compensation
lines.
However, in an analogous art, Jang teaches
(Previously Presented) The display substrate according to claim 6, further
comprising: a plurality of power compensation lines (SPL - Fig. 14 - [0313] - "plurality of secondary power lines SPL") in the display area (AA - Fig. 1 - [0220] -
"display area AA") and extending in the first direction (SPL - Fig. 14 - [0314] -
"secondary power lines SPL can extend long in the second direction Y" - extend in the
second direction but connect and perform as described in the relative directions are
swapped);
wherein:
the plurality of power compensation lines (SPL) are in a same layer as the
second capacitive electrode ([0112] - "second capacitor electrode");
the plurality of power signal lines (PSL) and the plurality of power
compensation lines (SPL).
Jang does not expressly disclose that SPL and the second capacitor electrode
are in the same layer but it would be oblivious to do so to prevent additional
manufacturing costs from adding separate layers.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate power compensation lines
and the capacitor as taught by Jang into Li, Tanada, and Woo.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result as stated above in claim 8.
Regarding claim 10, Li, as modified by Tanada, Jang, and Woo, teaches claim 5 from which claim 10 depends. Li, Tanada, and Jang, do not expressly disclose the limitations of claim 10.
However, in an analogous art, Woo teaches
(Original) The display substrate according to claim 5, wherein at least one
of the plurality of sub-pixels ([0066] - "pixel in the display area DA" - Fig. 4 is a pixel)
further comprises:
a light-emitting diode (OLEO - Fig. 4 annotated, see below - [0090] - "organic
light-emitting diode ("OLEO")"), on a side of the connecting electrode (CNE - Fig. 4-
[0087] - "connecting electrode CNE'') facing away from the substrate (101 - Fig. 4 -
[0076] - "display substrate 101"); and
wherein the driving drain (DE - Fig. 4 - [0081] - "drain electrode DE"), the
connecting electrode (CNE) and the light-emitting diode (OLEO) are electrically
connected with each other in sequence (Fig. 4 shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate light emitting diode structure as taught by Woo into Li, Tanada, and Jang.
An ordinary artisan would have been motivated to use the known technique of
Woo in the manner set forth above to produce the predictable result as stated above in claim 8.
Regarding claim 15, Li, as modified by Tanada, Jang, teaches claim 12 from which claim 15 depends. Li, and Tanada do not expressly disclose the limitations of claim 15.
However, in an analogous art, Jang teaches
at least one of the first auxiliary bus (CLL - Fig. 9c - [0075] - "closed loop line
CLL") and the second auxiliary bus is in a same layer ({11 - Fig. 4- [0117] - "circuit
layer 11" - this contains layers 11 a, 11 b, 11 c, and 11 d}, {[0204] - "conductive metal
line CML disposed in the buffer layer 11 a"}, {[0124] - "The interlayer insulation layer 11c can be disposed on the substrate 10 to cover the gate electrode GE and the active layer ACT. The interlayer insulation layer 11 c can electrically insulate (or isolate) the gate electrode GE and the source/drain electrodes SO1 and SO2"}) as the driving gate (GE - [0124] - "gate electrode GE").
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the auxiliary bus structure
taught by Jang into Li, and Tanada.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of simplifying
manufacturing and reducing cost by not adding additional and separate layers.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Li, Tanada, and Jang do not expressly disclose the other limitations of claim 15.
However, in an analogous art, Woo teaches
(Previously Presented) The display apparatus according to claim 12, wherein the display area (DA - Fig. 4 - [0057] - "display area DA") further comprises a plurality of subpixels ([0057] - "The display area DA includes a plurality of pixels"); at least one of the plurality of sub-pixels ([0066] - "pixel in the display area DA" - Fig. 4 is a pixel) comprises a driving thin film transistor (Fig. 4 annotated, see below - [0077] - "thin film transistor" - hereinafter '21'), a connecting electrode (CNE - Fig. 4 - [0087] - "connecting electrode CNE'') and a storage capacitor (Fig. 4 annotated, see below - [0077] - "storage capacitor" - hereinafter '34');
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the driving thin film transistor (21) comprises:
a driving active layer (105 - Fig. 4 -[0075] - "semiconductor layer 105"),
on the substrate (101 - Fig. 4 - [0076] - "display substrate 101 ");
a driving gate (GE - Fig. 4 - [0077] - "gate electrode GE"), on a side of
the driving active layer (105) facing away from the substrate (101);
a gate insulating layer (112 - Fig. 4- [0078] - "insulating layer 112"), on
a side of the driving gate (GE) facing away from the substrate (101);
an interlayer dielectric layer (113 - Fig. 4 - [0080] - "insulating layer
113"), on a side of the gate insulating layer (112) facing away from the substrate (101); and
a driving source (SE - Fig. 4 - [0081] - "source electrode SE") and a
driving drain (DE - Fig. 4- [0081] - "drain electrode DE"), on a side of the interlayer dielectric layer (113) facing away from the substrate (101);
the connecting electrode (CNE) is on a side of the driving source (SE) and
the driving drain (DE) facing away from the substrate (101);
the storage capacitor (34) comprises a first capacitive electrode (CE1 - Fig.
4 - [0079] - "first electrode CE 1 of the storage capacitor'') and a second capacitive electrode (CE2- Fig. 4- [0079] - "second electrode CE2 of the storage capacitor''), the first capacitive electrode (CE1) is in a same layer (120 - Fig. 4 - [0077] - "conductive layer 120 may include a gate electrode GE of a thin film transistor, a first electrode CE1 of a storage capacitor") as the driving gate (GE), and the second capacitive electrode (CE2) is arranged between the gate insulating layer (112) and the interlayer dielectric layer (113);
the plurality of initialization signal lines (SL - [0082] - "Although not shown in
the drawings, the third conductive layer 140 may further include a signal line disposed in
the pad area PA. The signal line may be disposed to overlap the connecting line of the
first conductive layer 120 in a thickness direction of the display substrate 101 or the
third direction DR3 and may be electrically connected to the connecting line through an
exposed part of the second insulating layer 112" - hereinafter 'SL', this is a signal line,
there are a plurality of pixels therefore a plurality of SL lines) are in a same layer (140 -
Fig. 4 - [0081] - "conductive layer 140 may include a source electrode SE, a drain
electrode, DE, and a high-potential voltage electrode ELVDDE") as the driving source
(SE) and the driving drain (DE);
the plurality of auxiliary signal lines (DL - Fig 4 - [0085] - "data line DL-this
is a signal line, there are a plurality of pixels therefore a plurality of DL lines) are in a
same layer (150 - Fig. 4- [0085] - "conductive layer 150 may include a data line DL, a
connecting electrode CNE, and a high-potential voltage line ELVDDL") as the
connecting electrode (CNE).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the display area structure
as taught by Woo into Li, Tanada, and Jang.
An ordinary artisan would have been motivated to use the known technique of
Woo in the manner set forth above to produce the predictable result of simplifying
manufacturing and reducing cost by not adding additional and separate layers.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 16, Li, as modified by Tanada, Jang, and Woo, teaches claim 5 from which claim 16 depends. Li, Tanada, and Jang do not expressly disclose the limitations of claim 16.
However, in an analogous art, Woo teaches
(Previously Presented) The display apparatus according to claim 5, wherein the display substrate further comprises: a plurality of power signal lines (ELVDDL - Fig. 4 - [0085] - "conductive layer 150 may include a data line DL, a connecting electrode CNE, and a high-potential voltage line ELVDDL" - there are a plurality of
pixels therefore a plurality of ELVDDL lines) in the display area (DA); wherein:
the plurality of power signal lines (ELVDDL) extend in the second direction
(DR1 - Fig. 1 - [0058] - "direction DR1"); and
the power signal lines (ELVDDL) and the auxiliary signal lines (DL) are in a
same layer (150 - Fig. 4- [0085] - "conductive layer 150 may include a data line DL, a
connecting electrode CNE, and a high-potential voltage line ELVDDL), and the power
signal lines (ELVDDL) and the auxiliary signal lines (DL) are arranged at intervals
([0057] - "The display area DA includes a plurality of pixels" - since the is a
plurality of pixel in the display area, they must be arranged at intervals).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the power and signal line
structure as taught by Woo into Li, Tanada, and Jang.
An ordinary artisan would have been motivated to use the known technique of
Woo in the manner set forth above to produce the predictable result of simplifying
manufacturing and reducing cost by not adding additional and separate layers.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 17, Li, as modified by Tanada, Jang, and Woo, teaches claim 16 from which claim 17 depends. Li, Tanada, and Woo do not expressly disclose the limitations of claim 17.
However, in an analogous art, Jang teaches
(Previously Presented) The display apparatus according to claim 16, wherein the display substrate further comprises: a first power bus (PL1 - Fig. 14 annotated, see below - [0293] - "driving power lines PL" - hereinafter 'PL1 ') and a second power bus (PL2 - Fig. 14 annotated, see below - [0293] - "driving power lines PL" - hereinafter 'PL2'), in the peripheral area ([0075] - "disposed at an edge portion of the substrate 10 to surround the display portion AA" - this describes the peripheral area)
and extending in the first direction (X - Fig. 14 - [0061] - "first direction X");
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wherein:
the first power bus (PL1) and the second power bus (PL2) are located at
two ends (Fig. 14 shows this) of each power signal line respectively (PSL - Fig. 14
- [0293] - "power sharing lines PSL"); and
the first power bus (PL1) and the second power bus (PL2) are electrically
connected ([0293] - "power lines PL among the plurality of pixel driving power lines PL
can be connected to a plurality of power sharing lines PSL") with the plurality of
power signal lines (PSL) respectively.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the bus structure taught by
Jang into Li, Tanada, and Woo.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of suppling power
to the elements as required without having to make separate supply lines for each. This
results in reduced manufacturing costs.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 18, Li, as modified by Tanada, Jang, and Woo, teaches claim 17 from which claim 18 depends. Li, Tanada, and Woo do not expressly disclose the limitations of claim 18.
However, in an analogous art, Jang teaches
(Previously Presented) The display apparatus according to claim 17, wherein at least one of the first power bus (PL1) and the second power bus (PL2) is in a same layer (11 - Figs. 17 and 19 - Fig. 17 shows PL in layer 11, Fig. 19 shows PSL in layer 11) as the plurality of power signal lines (PSL).
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate the bus structure taught by
Jang into Li, Tanada, and Woo.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of suppling power
to the elements as required without having to make separate supply lines for each. This
results in reduced manufacturing costs.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 19, Li, as modified by Tanada, Jang, and Woo, teaches claim 16 from which claim 19 depends. Li further teaches
the plurality of power signal lines and the plurality of power compensation
lines are electrically connected to each other through second vias, the
second vias run through the interlayer insulating layer and the interlayer dielectric layer, and orthographic projections of the second vias on the substrate
are located at intersections of orthographic projections of the plurality of power
signal lines on the substrate and orthographic projections of the plurality of
power compensation lines on the substrate ([0026] - "In a specific implementation,
the number of vias corresponding to each row of power lines can be calculated and
determined through simulation, so that the resistance of different power lines connected
in parallel with the corresponding power compensation lines can be the same within the
allowable error range" - though not specific, this is the concept of connecting different
lines by using vias as connection paths).
Li, Tanada, and Woo do not expressly disclose the other limitations of claim 19.
However, in an analogous art, Jang teaches
(Previously Presented) The display substrate according to claim 6, further
comprising: a plurality of power compensation lines (SPL- Fig. 14 - [0313] -
"plurality of secondary power lines SPL") in the display area (AA - Fig. 1 - [0220] -
"display area AA") and extending in the first direction (SPL - Fig. 14 - [0314] -
"secondary power lines SPL can extend long in the second direction Y" - extend in the
second direction but connect and perform as described in the relative directions are
swapped); wherein:
the plurality of power compensation lines (SPL) are in a same layer as the
second capacitive electrode ([0112] - "second capacitor electrode");
the plurality of power signal lines (PSL) and the plurality of power
compensation lines (SPL).
Jang does not expressly disclose that SPL and the second capacitor electrode
are in the same layer but it would be oblivious to do so to prevent additional
manufacturing costs from adding separate layers.
Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate power compensation lines
and the capacitor as taught by Jang into Li, Tanada, and Woo.
An ordinary artisan would have been motivated to use the known technique of
Jang in the manner set forth above to produce the predictable result of suppling power
to the elements as required without having to make separate layers for each. This
results in reduced manufacturing costs.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 20, Li, as modified by Tanada, Jang, and Woo, teaches claim 15 from which claim 20 depends. Li, Tanada, and Jang do not expressly disclose the other limitations of claim 19.
However, in an analogous art, Woo teaches
(Previously Presented) The display apparatus according to claim 15, wherein at least one of the plurality of sub-pixels ([0066] - "pixel in the display area DA" - Fig. 4 is a pixel) further comprises:
a light-emitting diode (OLEO - Fig. 4 annotated, see below - [0090] - "organic
light-emitting diode ("OLEO")"), on a side of the connecting electrode (CNE - Fig. 4-
[0087] - "connecting electrode CNE'') facing away from the substrate (101 - Fig. 4 -
[0076] - "display substrate 101"); and
wherein the driving drain (DE - Fig. 4 - [0081] - "drain electrode DE"), the
connecting electrode (CNE) and the light-emitting diode (OLEO) are electrically
connected with each other in sequence (Fig. 4 shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before
the effective filing date of the claimed invention, to integrate light emitting diode
structure as taught by Woo into Li, Tanada, and Jang.
An ordinary artisan would have been motivated to use the known technique of
Woo in the manner set forth above to produce the predictable result of suppling power
to the elements as required without having to make separate layers for each. This
results in reduced manufacturing costs.
To do so would have merely been to apply a known technique to a known device
ready for improvement to yield predictable results, KSR lnt'I Co. v. Teleflex Inc., 550
U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Pertinent Art
For the benefits of the Applicant, US 20200381505 A1 and US 20180226437 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including an auxiliary bus and compensating power line structure.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897