DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Specification Objections
Applicant has amended the specification at issue and the previous objections have therefore been withdrawn.
Prior Art Rejections
Applicant's arguments filed 8/10/2026 have been fully considered.
Applicant asserts, with respect to independent claims 1 and 2, the prior art, either alone or in combination, does not teach or suggest all features of the independent claims, as amended. Notably, the amendments clarify features wherein the second storage data and the second input data are divisors of the second output data (instead of the previous recitation of second input data in allowable claim 3).
Examiner respectfully disagrees. The currently amended claim language is of a different scope than the language that was previously identified as allowable. The currently amended claim language is taught by Qin [0035], as the results of the multiplication of the LSBs of weight and activations would be divisors of the corresponding second output. Therefore, the rejections of claims 1 and 2 are maintained.
Applicant asserts new claims 15-20 are in condition for allowance.
Applicant’s arguments are persuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 20210263992 A1, hereinafter “Qin”) in view of Matsui (US 5904731 A, hereinafter “Matsui”, provided in IDS filed 2/13/2026).
As per claim 1, Qin teaches A semiconductor device comprising: a storage circuit (Qin: Fig. 6 elements 610-3,610-4);
an arithmetic circuit (Qin: Fig. 6 elements 630-650);
and a product-sum operation circuit (Qin: Fig. 6 elements 630-650), wherein the storage circuit comprises a first storage region and a second storage region (Qin: Fig. 6 elements 610-3,610-4), wherein the first storage region is configured to retain first storage data (Qin: Fig. 6 elements 610-3; [0034]), wherein the second storage region is configured to retain second storage data (Qin: Fig. 6 elements 610-4; [0034]), wherein the switching circuit is configured to output the first storage data or the second storage data to the product-sum operation circuit (Qin: [0035]),
wherein the product-sum operation circuit is configured to retain first output data obtained by arithmetic processing performed on the first input data and the first storage data selected by the switching circuit (Qin: [0035]), wherein the product-sum operation circuit is configured to add, to the first output data, second output data obtained by arithmetic processing performed on the second input data and the second storage data selected by the switching circuit (Qin: [0035]; wherein multiply-accumulate operations with MSB set of weight vectors are added with the results of multiply-accumulate with LSB set of weight vectors), and wherein the second storage data and the second input data are divisors of the second output data (Qin: [0035], the results of the multiplication of the LSBs of weight and activations would be divisors of the corresponding second output).
However, while Qin discloses a multiplexor to route activation and weight banks, Qin does not explicitly disclose the structure of the multiplexer. Thus, Qin does not teach and a control circuit, wherein the arithmetic circuit comprises a switching circuit wherein the control circuit is configured to output first input data or second input data to the product-sum operation circuit;
Matsui teaches and a control circuit (Matsui: Fig. 5 element 81; col 5 lines 61-63, wherein the referenced element performs all the recited functions), wherein the arithmetic circuit comprises a switching circuit (Matsui: Fig. 5 element 82; col 5 lines 63-65) wherein the control circuit is configured to output first input data or second input data to the product-sum operation circuit (Matsui: col 5 lines 61-63);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the multiplexor of Qin with the selectors of Matsui. One would have been motivated to combine these references because both references disclose selecting each operand for multiply-accumulate computation, and combining prior art elements according to known methods to yield predictable results (structure of the multiplexing function).
As per claim 3, Qin/Matsui further teaches The semiconductor device according to claim 1, further comprising a driver circuit configured to control writing and reading out of data to and from the first storage region and the second storage region (Matsui: Fig. 14 element 100; col 8 lines 33-34).
As per claim 5, Qin/Matsui further teaches The semiconductor device according to claim 1, wherein the product-sum operation circuit comprises a multiplier circuit, an adder circuit, and a register (Qin: Fig. 6 elements 630-650).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Qin/Matsui in view of Harada et al. (US 20180101359 A1, hereinafter “Harada”).
As per claim 6, Qin/Matsui further teaches The semiconductor device according to claim 1,
However, while Qin discloses logic-level circuity, Qin does not explicitly disclose the circuitry at a transistor level. Thus, Qin does not teach wherein the storage circuit comprises a memory cell comprising a first transistor, and wherein the first transistor comprises a semiconductor layer containing a metal oxide in a channel formation region.
Harada teaches wherein the storage circuit comprises a memory cell comprising a first transistor, and wherein the first transistor comprises a semiconductor layer containing a metal oxide in a channel formation region (Harada: [0205]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the logic-level of circuity of Qin with the transistors of Harada. One would have been motivated to combine these references because both references disclose circuitry computing multiply-accumulate, and the OS transistors enables performing the product-sum operation with high calculation accuracy (Harada: [0212]).
As per claim 7, Qin/Matsui/Harada further teaches The semiconductor device according to claim 6, wherein the metal oxide comprises In, Ga, and Zn (Harada: [0211]).
As per claim 8, Qin/Matsui further teaches The semiconductor device according to claim 1,
However, while Qin discloses logic-level circuity, Qin does not explicitly disclose the circuitry at a transistor level. Thus, Qin does not teach wherein the arithmetic circuit comprises a second transistor, and wherein the second transistor comprises a semiconductor layer containing silicon in a channel formation region.
Harada teaches wherein the arithmetic circuit comprises a second transistor, and wherein the second transistor comprises a semiconductor layer containing silicon in a channel formation region (Harada: [0617]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the logic-level of circuity of Qin with the transistors of Harada for at least the same reasons as discussed above for claim 6.
Claims 2, 9, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Qin in view of Matsui in further view of Kim et al. (US 20190189221 A1, hereinafter “Kim”).
As per claim 2, the claim is directed to a semiconductor device that implements the same or similar features as the semiconductor device of claim 1, and is therefore rejected for at least the same reasons therein.
Furthermore, while Qin discloses memory and arithmetic circuitry, Qin does not explicitly disclose the physical layout of the circuitry. Thus, Qin does not teach wherein a layer including the storage circuit is provided over a layer including the arithmetic circuit.
Kim teaches wherein a layer including the storage circuit is provided over a layer including the arithmetic circuit (Kim: [0132]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the logic-level of circuity of Qin with arrangement teachings of Kim. One would have been motivated to combine these references because both references disclose circuitry computing multiply-accumulate, and the structure of Kim effectively decreases an area occupying on a surface perpendicular to the stacking direction (Kim: [0133]).
As per claims 9, 11, the claims are directed to a semiconductor device that implements the same or similar features as the semiconductor device of claims 3, 5, respectively, and are therefore rejected for at least the same reasons therein.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Qin/Matsui/Kim in view of Harada.
As per claims 12-13, the claims are directed to a semiconductor device that implements the same or similar features as the semiconductor device of claims 6-8, respectively, and are therefore rejected for at least the same reasons therein.
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 4 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 4, 10, and 15, the prior art of record does not teach or suggest a combination as claimed
wherein the first storage data is weight data, wherein the second storage data is first subbias data, and wherein the second input data is second subbias data.
Qin discloses a vector-vector multiplication product unit wherein the weights and activations are stored in at least two SRAM banks each, and are selected for computation ([0034]-[0035]). Qin does not suggest any of the SRAM banks storing data corresponding to subbias data. Therefore, Qin does not teach or suggest a combination as claimed including the limitations identified above.
Matsui discloses a product-sum device wherein coefficients and input data are stored in at least two registers each, and are selected for computation (Fig. 5; col 5 lines 50-65), wherein the coefficients may be fractions (col 4 line3 5). Matsui does not suggest the coefficients and data corresponding to subbias data. Therefore, Matsui does not teach or suggest a combination as claimed including the limitations identified above.
Martin (US 20190147327 A1, hereinafter “Martin”) discloses a neuron engine selecting weight and input data based on sparsity and accumulating a bias after multiplication (Fig. 3; [0140]; [0173]). Martin does not suggest generating the bias with subbias data through the same multiplier. Therefore, Martin does not teach or suggest a combination as claimed including the limitations identified above.
Holm et al. (US 20210133542 A1, hereinafter “Holm”) discloses multiply-accumulate circuit receiving input feature map, weight, and bias (Fig. 3; [0128]), where the bias is merely added ([0130]). Holm does not suggest generating the bias with subbias data through the same multiplier. Therefore, Holm does not teach or suggest a combination as claimed including the limitations identified above.
Zaidy et al. (US 20210303358 A1, hereinafter “Zaidy”) discloses a vector-vector accelerator with a plurality of MAC circuits that accumulates or adds bias parameters (Fig.6; [0055]). Zaidy does not suggest generating the bias with subbias data through the same multiplier. Therefore, Zaidy does not teach or suggest a combination as claimed including the limitations identified above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
