DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant’s arguments with respect to claim 13 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 and 20 are rejected under 35 U.S.C. 103 as anticipated by Takenaka (US 2016/0134244).
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Fig. 2 of Takenaka annotated by the examiner for ease of reference.
Regarding claim 13, An amplifier circuit (Fig. 1) comprising:
an amplifier including a transistor (Tr1-Tr2), wherein a first terminal (source of Tr1) of the transistor is grounded (see Fig. 1); and
at least one neutralization circuit (C3-R4, col. 6, lines 3-29) connected between a second terminal (gate of Tr1) and a third terminal (drain of Tr2) of the transistor (Tr1-Tr2), wherein the at least one neutralization circuit (C3-R4) is configured to neutralize (neutralizes the effect of parasitic capacitance of the transistor Tr1-Tr2 as a shunt feedback, §0040) a feedback capacitance (The feedback element which are composed of a resistor in series with a capacitor, linearize the gain and increase the bandwidth of the amplifier, therefore, neutralizes the effect of propensity to oscillation due to unwanted excessive gain in low frequency end of the spectrum, which is a common knowledge in the art1) of the amplifier, and wherein the at least one neutralization circuit (C3-R4) includes a first transmission line (L1) a second transmission line (L2), a capacitor (C3) and a resistor (R4) while the first transmission line (L1), the second transmission line, the capacitor and the resistor being connected in series,
wherein a first end (A) of the first transmission line (L1) is connected to the third terminal of the transistor drain (of Tr2),
wherein a first end (C) of the second transmission line (L2) is connected to the second terminal of the transistor (gate of Tr1),
wherein a second end (B) of the first transmission line (L1) is connected to a first end of the Capacitor (C3) not the resistor as claimed,
wherein a second end of the resistor (R4) is connected to a first end of the capacitor (C3), and wherein a second end (D) of the second transmission line (L2) is connected to a second end of the resistor not the capacitor as claimed.
A person of ordinary skill in the art would find it obvious to swap the resistor and the capacitor their respective places in the series connection with the same exact effect as in current configuration and thereby it is well known that the position as claimed for C3 and R4 are equivalently met by Takenaka.
Claim 13 and 20 are rejected under 35 U.S.C. 103 as unpatentable over Mizutani (US7541873,) in view Takenaka.
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Fig. 1 of Mizutani annotated by the examiner for ease of reference.
Regarding claims 13 and 20, An amplifier circuit (Fig. 1) comprising:
an amplifier including a transistor (3), wherein a first terminal (source) of the transistor is grounded (see Fig. 1); and
at least one neutralization circuit (1 & 2 together, col. 6, lines 3-29) connected between a second terminal (gate) and a third terminal (drain) of the transistor, wherein the at least one neutralization circuit (1 & 2 together) is configured to neutralize (the transmission line 1 and the neutralization capacitor 2 together neutralizes the effect of feedback parasitic capacitance of the transistor, col. 6, lines 3-29) a feedback capacitance (a parasitic capacitance Cgd is generated between the input and output of the transistor 3) of the amplifier, and wherein the at least one neutralization circuit (1 & 2 together) includes a first transmission line (1) and a capacitor (2) connected in series.
Mizutani, however, is not explicit about a second transmission line and a resistor in series with the first transmission line and the capacitor as claimed.
Takenaka in a similar field of endeavor teaches a first transmission line (L1) a second transmission line (L2), a capacitor (C3) and a resistor (R4) while the first transmission line (L1), the second transmission line, the capacitor and the resistor being connected in series, while the first and second transmission lines provide a design symmetry for the placement of the resistor and capacitor combination in the feedback path provide the necessary frequency selective damping for linearization of gain.
Therefore, it would have been obvious to a person of ordinary skill in the art to implement the symmetrically arranged two transmission lines at two ends with a series resistor and capacitor feedback network between the gate and drain of the Mizutani transistor and thereby teaching all limitations of claim 13 and 20 for obvious reasons of gain linearization and wider bandwidth with a symmetrically arranged feedback network.
Claims 13, 15, 18, 20, 22 and 25 are rejected under 35 U.S.C. 103 as unpatentable over Lei et al. CN 105375886 B, a machine translation has been relied upon and a marked copy is attached herewith) in view of Takenaka.
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Fig. 1 of Lei et al. annotated by the examiner for ease of reference.
Regarding claims 13 and 20, An amplifier circuit (Fig. 1) comprising:
an amplifier including a transistor (MN), wherein a first terminal (source) of the transistor is grounded (see Fig. 1); and
at least one neutralization circuit (XM and C2 together) connected between a second terminal (gate) and a third terminal (drain) of the transistor, wherein the at least one neutralization circuit (capacitor 2) is configured to neutralize (, using two transmission line coupling effect combines neutralization capacitance C2 to form positive feedback, in the millimeter wave band, eliminates the negative feedback introduced by CGD, under the condition of not increasing the power consumption, and greatly improves the gain and does not adopt the technology, if the same gain then reduces the power consumption and is not limited with existing technology, transformer quality factor and self-resonance frequency. at the same time, the transmission line layout flexibility, compared by the coupling effect of the inductor and transformer can reduce the chip area and save the cost, par. 1 of p. 3 of the marked machine translation) a feedback capacitance (a parasitic capacitance CGD is generated between the input and output of the transistor MN) of the amplifier, and wherein the at least one neutralization circuit (XM and C2) includes a first transmission line (XM) and a capacitor (C2) connected in series (through VDD). And per claim 20, wherein the at least one neutralization circuit includes a first transmission line and a coupling line (XM) connected in series (through VDD).
Lei, however, is not explicit about a resistor in series with the first transmission line, the capacitor and the second transmission line as claimed.
Takenaka in a similar field of endeavor teaches a first transmission line (L1) a second transmission line (L2), a capacitor (C3) and a resistor (R4) while the first transmission line (L1), the second transmission line, the capacitor and the resistor being connected in series, while the first and second transmission lines provide a design symmetry for the placement of the resistor and capacitor combination in the feedback path provide the necessary frequency selective damping for linearization of gain.
Therefore, it would have been obvious to a person of ordinary skill in the art to implement the symmetrically arranged two transmission lines at two ends with a series resistor and capacitor feedback network between the gate and drain of the Lei transistor and thereby teaching all limitations of claim 13 and 20 for obvious reasons of gain linearization and wider bandwidth with a symmetrically arranged feedback network.
wherein per claim 22, the coupling line in Lei is connected between the first transmission line and the second transmission line (of XM).
Regarding claim 15, Lei also teaches two transmission lines (XM) with a capacitor in series.
Further per claim 18 and 25, Lei also teaches a bias circuit configured for bias application, wherein a transmission line of the bias circuit is also used as the first transmission line (XM) of the at least one neutralization circuit.
Claims 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over the resultant combination of Lei and Takenaka and further in view of Samoska et al. (“InP MMIC Chip Set for Power Sources Covering 80-170 GHz”, published in 12th International Symposium on Space Terahertz Technology, February 2001).
Regarding claims 14 and 21, Lei in view of Takenaka teaches all limitations of claims 13 and 20. The resultant combination also specifies that the transistor MN of the amplifier of Fig. 1 as a source grounded NMOS transistor and is not explicit about InP HEMT for the transistor 10. However, knowing the frequency of application between 60 GHz a person of ordinary skill in the art would find it obvious to look for a novel III-V HEMT transistors like InP with high fmax for such application.
In a similar field of endeavor Samoska teaches a Monolithic Millimeter-wave Integrated Circuit (MMIC) power amplifier, like Lei chip set, which provides high output-power sources for driving 100’s of GHz range using InAlAs/InGaAs/InP high electron mobility transistor (HEMT) process, and features transistors with fmax above 600 GHz. The HRL InP HEMT process has already demonstrated amplifiers in the 60-200 GHz range.
It will be obvious to a person of ordinary skill in the art to use such technology for Mitsusuke transistor to comfortably cover the frequency of operation with reasonable gain. Thereby the resultant amplifier would teach on the limitations of claim 2.
Claims 16-17, 19, 23-24, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Takenaka.
Regarding claims 19 and 26, Lei in view of Takenaka teaches all limitations of claims 13 and 20. Since Lei also teaches a 65 nm CMOS process, although not shown, it would be obvious to a person of ordinary skill in the art that the NMOS feedback miller capacitance as being neutralized by a neutralizing transmission line and capacitor combination, similar arrangement would be implemented for the complementary PMOS of the CMOS process as well and thereby teaching on two neutralization circuits arranged in parallel as recited in claim 19.
Lei further teaches regarding claims 16-17 and 23-24, a bias circuit configured (gate bias through resistor R1 and VDD for drain) for bias application, wherein a series resistor (R1) having a predetermined resistance value is arranged on a transmission line of the bias circuit. A person of ordinary skill in the art would find it obvious to include the gate bias circuit along with the drain bias supply VDD as a voltage divider so that one supply can provide bias to both drain and gate of the same transistor, which is a common practice in mobile devices for portability and single battery operation. Therefore, a person of ordinary skill would arrange with the neutralization circuit further including a resistor connected in series with the first transmission line and the coupling line to provide bias to the gate of the transistor and thereby teaches the limitations of claims 16-17 and 23-25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 Fig. 6 and associated discussion of Reddy et al., “The Design of Cascode, Shunt feedback Low Noise Amplifiers in 180nm Technology for WiMAX Applications,” International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 24 (2017) pp. 15957-15965.
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