Prosecution Insights
Last updated: April 19, 2026
Application No. 17/926,826

ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS

Non-Final OA §103§112
Filed
Nov 21, 2022
Examiner
NGUYEN, LAUREN
Art Unit
2871
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
5 (Non-Final)
54%
Grant Probability
Moderate
5-6
OA Rounds
3y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 54% of resolved cases
54%
Career Allow Rate
549 granted / 1007 resolved
-13.5% vs TC avg
Strong +36% interview lift
Without
With
+35.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
74 currently pending
Career history
1081
Total Applications
across all art units

Statute-Specific Performance

§103
63.0%
+23.0% vs TC avg
§102
30.3%
-9.7% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1007 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/16/2026 has been entered. Response to Amendment Applicant’s arguments filed 01/16/2026 have been fully considered but they are not persuasive. The applicant argues that none of the cited references teaches the limitation as amended in claim 1. The examiner respectfully disagrees. Maede et al. (figures 1-7 and 11) teaches wherein the plurality of spacing areas further comprises an auxiliary spacing area, the auxiliary spacing area is adjacent to a corner of a tetragon (between ML5, ML6, ML62 and ML63), formed by one of the plurality of first metal wires and one of plurality of the second metal wires of the net-like structure, and when the minimum distance between the orthographic projection of the common metal laver on the base substrate and the main spacing area is greater than or equal to a first distance, a minimum distance between an orthographic projection of respective one of the second metal wires on the base substrate and the main spacing area in the row direction is greater than or equal to the first distance (between ML5, ML6, ML62 and ML63), and wherein a size of the gap on the first metal wire in the row direction is equal to a size of two pixel units in the row direction (between M4, M6, ML62-ML63; figure 11). Claim Rejections - 35 USC § 112 Claims 1, 4-7, 10, 12-20 and 22-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specific limitation as presented in claim 1 “the common metal layer consists of a plurality of metal wires arranged in an intersecting manner the plurality of metal wires comprise a plurality of first metal wires extending in a row direction and a plurality of second metal wires extending in a column direction to forma net-like structure, at least one of the first metal wires wherein at least one of the plurality of metal wires is provided with a gap, and the main spacing area is disposed at or close to a center of an orthographic projection of the gap on the base substrate” is not supported by the originally filed application. As shown in figures 1 and 4 of the instant application, the metal wires comprise a few different lines extending in different directions. Appropriate correction is required. Being dependent on claim 1, claims 4-7, 10, 12-20 and 22-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (KR 20150057027) in view of Maede et al. (US 2017/0192279). Regarding claim 1, Ahn et al. (figures 5-6) discloses an array substrate configured for forming a display panel with a cell substrate and a plurality of spacers (CS), wherein the array substrate comprises a plurality of spacing areas, and a surface of respective one of the spacing areas facing the cell substrate is configured to be abutted against or to be disposed oppositely to a surface of respective one of the spacers facing the array substrate, and the plurality of spacing areas comprising a main spacing area; the array substrate comprises: a base substrate (SUB); an array of thin film transistors (T) disposed on a side of the base substrate, wherein the array of thin film transistors comprises a semiconductor layer (A); and a common metal layer (COM) disposed on a side of the array of thin film transistors away from the base substrate; wherein an orthographic projection of the common metal layer on the base substrate does not overlap with an orthographic projection of the semiconductor layer on the base substrate, and the main spacing area is disposed at or close to a center of an orthographic projection of the gap on the base substrate (figures 5-6); wherein the plurality of spacing areas further comprises an auxiliary spacing area, and a minimum distance between the orthographic projection of the common metal layer on the base substrate and the main spacing area is greater than or equal to a minimum distance between the orthographic projection of the common metal layer on the base substrate and the auxiliary spacing area (the distance between the upper portion of COM to CS and the distance between the lower portion of COM to CS); wherein the array substrate comprises a plurality of pixel units arrayed in the row direction and in the column direction. Ahn et al. discloses the limitations as shown in the rejection of claim 1 above. However, Ahn et al. is silent regarding the common metal layer comprises a plurality of metal wires arranged in an intersecting manner. Maede et al. (figures 1-7 and 11) teaches the common metal layer consists of a plurality of metal wires arranged in an intersecting manner the plurality of metal wires comprise a plurality of first metal wires extending in a row direction and a plurality of second metal wires extending in a column direction to forma net-like structure (figure 11; ML1-ML10and ML62-ML63; the wires can be extended in three different directions, xyz), at least one of the first metal wires wherein at least one of the plurality of metal wires is provided with a gap (between ML62 and ML63), and the main spacing area is disposed at or close to a center of an orthographic projection of the gap on the base substrate; wherein the plurality of spacing areas further comprises an auxiliary spacing area, the auxiliary spacing area is adjacent to a corner of a tetragon (between ML5, ML6, ML62 and ML63), formed by one of the plurality of first metal wires and one of plurality of the second metal wires of the net-like structure, and when the minimum distance between the orthographic projection of the common metal laver on the base substrate and the main spacing area is greater than or equal to a first distance, a minimum distance between an orthographic projection of respective one of the second metal wires on the base substrate and the main spacing area in the row direction is greater than or equal to the first distance (between ML5, ML6, ML62 and ML63), and wherein a size of the gap on the first metal wire in the row direction is equal to a size of two pixel units in the row direction (between M4, M6, ML62-ML63; figure 11). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer as taught by Maede et al. in order to dispose the spacers without causing a deterioration in display quality such as white balance. Regarding claim 22, Ahn et al. (figures 5-6) discloses wherein a distance between two of the plurality of second metal wires respectively adjacent to the main spacing area in the row direction is greater than or equal to a size of two pixel units in the row direction, and less than or equal to a size of three pixel units in the row direction (between M4, M6, ML62-ML63; CFB-CFR and CFG; figure 11). Regarding claim 23, Ahn et al. (figures 5-6) discloses wherein a distance from the auxiliary spacing area to the corner is equal to or less than a half of a dimension of one instance of the plurality of pixel units in the row direction (between ML5, ML6, ML62 and ML63; figure 11). Claims 5-6, 11-12, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. in view of Maede et al.; further in view of Morimoto et al. (US 2016/0238903). Regarding claim 5, Ahn et al. discloses the limitations as shown in the rejection of claim 1 above. However, Ahn et al. is silent regarding the limitation as presented in claim 5. Morimoto et al. (figures 1-4) teaches a hollowed hole is disposed at an intersection of the first metal wire and the second metal wire, and the auxiliary spacing area is located within a range of an orthographic projection of the hollowed hole on the base substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer as taught by Morimoto et al. in order to electrically connecting the common electrodes CE arranged in the second direction Y. In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to (?), since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167. Regarding claim 6, Morimoto et al. (figures 1-4) teaches a bent portion is disposed on the third metal wire and/or the fourth metal wire, and an orthographic projection of the bent portion on the base substrate partially surrounds the auxiliary spacing area (30 and 110). Regarding claim 11, Morimoto et al. (figures 1-4) teaches wherein the pixel unit comprising two domain areas divided by a boundary line of domain areas; wherein an orthographic projection of the first metal wire on the base substrate is located at a position of the boundary line of domain areas in the pixel unit (30 and 110). Regarding claim 12, Morimoto et al. (figures 1-4) teaches wherein a size of a gap on the seventh metal wire in the column direction is equal to a size of one pixel unit in the column direction (30 and 110). Regarding claim 13, Morimoto et al. (figures 1-4) teaches wherein a size of a gap on the second metal wire in the row direction is equal to a size of two pixel units in the column direction (30 and 110). Regarding claim 15, Morimoto et al. (figures 1-4) teaches wherein the array of thin film transistors further comprises a grid line metal layer (10 and 20) and a second insulating layer arranged in layer configuration on a side of the semiconductor layer close to the base substrate, the semiconductor layer is arranged on a side of the second insulating layer away from the base substrate, and the grid line metal layer comprises a plurality of grid lines extending along the row direction; the plurality of metal wires comprise a plurality of transverse metal wires extending along the row direction; and in the column direction, orthographic projections of the transverse metal wires on the base substrate is located within a range of orthographic projections of the grid lines on the base substrate, or the orthographic projections of the transverse metal wires on the base substrate covers the orthographic projections of the grid lines on the base substrate, or the orthographic projections of the transverse metal wires on the base substrate completely or partially overlaps with the orthographic projections of the grid lines on the base substrate. Regarding claim 16, Morimoto et al. (figures 1-4) teaches wherein the array of thin film transistors further comprises a data line metal layer disposed on a side of the semiconductor layer away from the base substrate, the data line metal layer comprising a plurality of data lines extending along the column direction; the plurality of metal wires comprises a plurality of vertical metal wires extending along the column direction (10 and 20), and each of vertical metal wires comprises a plurality of metal wire segments, wherein the plurality of metal wire segments are parallel to the plurality of data lines; and in the row direction, orthographic projections of the metal wire segments on the base substrate is located within a range of orthographic projections of the data lines on the base substrate, or the orthographic projections of the metal wire segments on the base substrate covers the orthographic projections of the data lines on the base substrate, or the orthographic projections of the metal wire segment on the base substrate completely or partially overlaps with the orthographic projections of the data lines on the base substrate. Regarding claim 17, Morimoto et al. (figures 1-4) teaches the cell substrate and the array substrate according to claim 1, and a liquid crystal layer and a plurality of spacers (40) disposed between the cell substrate and the array substrate; wherein the plurality of spacers are arranged on a surface of a side of the cell substrate close to the array substrate, for supporting the cell substrate and the array substrate, the surface of the respective one of the spacers facing the array substrate is abutted against or disposed oppositely to the surface of the respective one of the spacing areas facing the cell substrate. Regarding claim 18, Morimoto et al. (figures 1-4) teaches the display panel comprises a plurality of sub-pixels arrayed along a row direction and along a column direction, and the plurality of sub-pixels comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel (201); and the plurality of metal wires comprises a plurality of vertical metal wires extending along a column direction; wherein the main spacing area is arranged in the third color sub-pixel; the vertical metal wires are located between the third color sub-pixel and the first color sub-pixel which are adjacently arranged in the row direction, and/or the vertical metal wires are located between the first color sub-pixel and the second color sub-pixel which are adjacently arranged along the row direction. Regarding claim 19, Morimoto et al. (figures 1-4) teaches wherein the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel. Regarding claim 20, Morimoto et al. (figures 1-4) teaches a display apparatus, comprising the display panel according to claim 17. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. in view of Maede et al. and Ahn (US 2011/0263055); further in view of Sakurai et al. (US 2010/0157229). Regarding claim 14, Morimoto et al. (figures 1-4) teaches wherein the array substrate further comprises at least one of: a first transparent electrode layer disposed on a surface of a side of the common metal layer away from the base substrate (30 and 110); a planarization layer disposed between the array of thin film transistors and the common metal layer (109), wherein a material of the planarization layer is an organic insulating material (see at least paragraph 0072); and a first insulating layer disposed between the second transparent electrode layer and the common metal layer (111). However, Ahn et al. is silent regarding a second transparent electrode layer disposed between the planarization layer and the common metal layer and a first transparent electrode. Sakurai et al. (figures 3A-3B) teaches a second transparent electrode layer disposed between the planarization layer and the common metal layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer as taught by Sakura et al. in order to make the amount of light per pixel uniform even when the display screen is viewed at any angle. Therefore, a liquid crystal panel with a wide viewing angle can be realized. In addition, Ahn (figures 1-4) teaches wherein the array substrate further comprises a first transparent electrode layer disposed on a surface of a side of the common metal layer away from the base substrate (108A and 108B). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer and the transparent electrode layer as taught by Ahn in order to electrically connecting the common electrodes arranged in the second direction Y and achieve a multi-layer having a conductor layer and a reflectance reducing layer. In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first transparent electrode layer disposed on a surface of a side of the common metal layer away from the base substrate, since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167. Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. in view of Morimoto et al. and Maede et al.; further in view of Asakawa et al. (US 2013/0321752). Regarding claim 3, Ahn et al. discloses the limitations as shown in the rejection of claim 1 above. However, Ahn et al. is silent regarding wherein the minimum distance between the orthographic projection of the common metal layer on the base substrate and the auxiliary spacing area is greater than or equal to 12.5 microns. Asakawa et al. (figures 1-2) wherein the minimum distance between the orthographic projection of the common metal layer on the base substrate and the auxiliary spacing area is greater than or equal to 12.5 microns (between the adjacent pixel electrodes and the next slits; see at least paragraphs 0066-0067). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the distance as taught by Asakawa et al. in order to obtain a high transmittance over a wider range, and enhance the transmittance per pixel. One of ordinary skill in the art before the effective filing date of the claimed invention would recognize utilizing a value close to applicant's claimed range, since it has been held that where the general condition of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. Further, it has been held that a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap by are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of “about 1-5%” while the claim was limited to “more than 5%.” The court held that “about 1-5%” allowed for concentrations slightly above 5% thus the ranges overlapped.). Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of “having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium” as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium.). See MPEP § 2144.05. Regarding claim 7, Ahn et al. discloses the limitations as shown in the rejection of claim 3 above. However, Ahn et al. is silent regarding wherein the minimum distance between the orthographic projection of the common metal layer on the base substrate and the main spacing area is greater than or equal to 25 microns. Asakawa et al. (figures 1-2) wherein the minimum distance between the orthographic projection of the common metal layer on the base substrate and the main spacing area is greater than or equal to 25 microns (between the adjacent pixel electrodes and the next slits; see at least paragraphs 0066-0067). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the distance as taught by Asakawa et al. in order to obtain a high transmittance over a wider range, and enhance the transmittance per pixel. One of ordinary skill in the art before the effective filing date of the claimed invention would recognize utilizing a value close to applicant's claimed range, since it has been held that where the general condition of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. Further, it has been held that a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap by are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of “about 1-5%” while the claim was limited to “more than 5%.” The court held that “about 1-5%” allowed for concentrations slightly above 5% thus the ranges overlapped.). Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of “having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium” as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium.). See MPEP § 2144.05. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-97911. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN NGUYEN/ Primary Examiner, Art Unit 2871
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Prosecution Timeline

Nov 21, 2022
Application Filed
Sep 20, 2024
Non-Final Rejection — §103, §112
Dec 02, 2024
Response Filed
Dec 27, 2024
Final Rejection — §103, §112
Mar 28, 2025
Request for Continued Examination
Mar 31, 2025
Response after Non-Final Action
May 20, 2025
Non-Final Rejection — §103, §112
Aug 22, 2025
Response Filed
Oct 13, 2025
Final Rejection — §103, §112
Dec 15, 2025
Response after Non-Final Action
Dec 18, 2025
Applicant Interview (Telephonic)
Dec 22, 2025
Examiner Interview Summary
Jan 16, 2026
Request for Continued Examination
Feb 02, 2026
Response after Non-Final Action
Feb 06, 2026
Non-Final Rejection — §103, §112 (current)

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Expected OA Rounds
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Grant Probability
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3y 5m
Median Time to Grant
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