DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed March 16, 2026 have been entered an considered
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1C, Claims 7-9 in the reply filed on April 29, 2025 is acknowledged.
Claim 1-6 and 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 29, 2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shinno (US 20190363233 A1), in view of Wakita (JP 2010087453 A).
Regarding claim 7, Shinno teaches:
A micro light emitting diode chip [1, paragraph [0040-0042], Fig. 7A-7B, 9A-9B] integrated device [4, paragraph [0042-0043], Fig. 9A-9B], the micro light emitting diode chip [1, Fig. 7A-7B, 9A-9B] integrated device [4, Fig. 9A-9B], comprising:
a substrate [2, paragraph [0041-0042], Fig. 8A-9B] having a lower electrode [21, paragraph [0041-0042], Fig.8A-9B] having a main line part [21, Fig. 8A-9B] and a plurality of branch line parts [41-1, 41-2, 41-3, 41-4, 41-5, 41-6, paragraph [0041-0042], Fig. 8A-9B]
an upper electrode [22, paragraph [0041-0042], Fig. 8A-9B] as the upper layer of the lower electrode [21, Fig. 8A-9B],
a chip joining part [“bonding area”, corresponds to area above 41-1 to 41-6 and 42, paragraph [0045], Fig. 8A-9B] which is formed by an area including at least a part of the upper surface of each of the branch line parts [41-1 to 41-6, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B] and a part of the upper surface of the upper electrode [22, Fig. 8A-9B]; and
a lateral micro p-n light emitting diode chip [1, Fig. 7A-7B, 9A-9B] having a plurality of p-side electrodes [11-1, 11-2, 11-3, 11-4, 11-5, 11-6, paragraph [0041-0042], Fig. 7A-7B, 9A-9B] and an n-side electrode [12, paragraph [0041-0042], Fig. 7A-7B, 9A-9B] on one surface joined to the chip joining part [“bonding area”, corresponds to area above 41-1 to 41-6 and 42, paragraph [0045], Fig. 8A-9B],
the lateral micro p-n light emitting diode chip [1, Fig. 7A-7B, 9A-9B] comprising an n*-type semiconductor layer [not shown, paragraph [0005], [0068], Fig. 7A-7B], a light emitting layer [“active layer” not shown, paragraph [0005], Fig. 7A-7B] provided on the n+-type semiconductor layer and a p-type semiconductor layer [not shown, paragraph [0005], Fig. 7A-7B] provided on the light emitting layer, the n-side electrode [12, paragraph [0041-0042], Fig. 7A-7B] being provided on a part of the n+-type semiconductor layer which is not covered by the light emitting layer and the p-side electrodes [11-1 to 11-6, Fig. 7A-8B] being provided on the p-type semiconductor layer,
the upper electrode [22, Fig. 8A-9B] having a part parallel to the main line part [21, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B] which is provided such that the part passes through positions apart from the branch line parts [41-1 to 41-6, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B] and a branch line part [corresponds to protrusion in area of 40, Fig. 8A-9B] protruding from the part toward the main line part [21, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B] such that the branch line part [corresponds to protrusion in area of 40, Fig. 8A-9B] extends over a position near to the branch line parts [41-1 to 41-6, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B],
the number of the branch line parts [41-1 to 41-6, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B] being 3 to 10,
the lateral micro p-n light emitting diode chip [1, Fig. 7A-7B, 9A-9B] being joined to the chip joining part [“bonding area”, corresponds to area above 41-1 to 41-6 and 42, paragraph [0045], Fig. 8A-9B ] such that the p-side electrodes [11-1 to 11-6, Fig. 7A-7B, 9A-9B] and the n-side electrode [12, Fig. 7A-7B, 9A-9B] face the chip joining part [“bonding area”, corresponds to area above 41-1 to 41-6 and 42, paragraph [0045], Fig. 8A-9B], at least one of the p-side electrodes [11-1 to 11-6, Fig. 7A-7B, 9A-9B] and the branch line parts [41-1 to 41-6, Fig. 8A-9B] of the lower electrode [21, Fig. 8A-9B] being electrically connected each other and the n-side electrode [12, Fig. 7A-7B, 9A-9B] of the lateral micro p-n light emitting diode chip [1, Fig. 7A-7B, 9A-9B] and the branch line part [corresponds to protrusion in area of 40, Fig. 8A-9B] of the upper electrode [22, Fig. 8A-9B] being electrically connected each other.
Shinno does not teach:
A micro light emitting diode display.
a substrate having a lower electrode having a main line part and a plurality of branch line parts which are connected each other by a thin film fuse on one major surface,
the thin film fuse being provided in a gap between the main line part and each of the branch line parts,
the thin film fuse being used to cut off the branch line part to which the lateral micro p-n light emitting diode chip with defection is connected from the main line part.
Wakita teaches:
A micro light emitting diode display [100, paragraph [0077], Fig. 7]
a substrate [30, paragraph [0016], [0020], Fig. 1-2, 5, 7] having a lower electrode having a main line part [105, paragraph [0016], [0019], [0021], [0080], [0156], Fig. 7, 19] and a plurality of branch line parts [31, paragraph [0015-0016], [0018-0020], [0022], [0029], [0078], [0080], [0156], Fig. 7, 19] which are connected each other by a thin film fuse [104, paragraph [0019], [0021], [0080], [0156], Fig. 7, 19] on one major surface,
the thin film fuse [104, paragraph [0019], [0021], [0080], [0156], Fig. 7, 19] being provided in a gap between the main line part [105, paragraph [0016], [0019], [0021], [0080], [0156], Fig. 7, 19] and each of the branch line parts [31, paragraph [0015-0016], [0018-0020], [0022], [0029], [0078], [0080], [0156], Fig. 7, 19],
the thin film fuse [104, paragraph [0019], [0021], [0080], [0156], Fig. 7, 19] being used to cut off the branch line part [31, paragraph [0015-0016], [0018-0020], [0022], [0029], [0078], [0080], [0156], Fig. 7, 19] to which the lateral micro p-n light emitting diode chip [20, paragraph [0016-0017], [0025], [0040], [0078], Fig. 1-2, 5, 19] with defection is connected from the main line part [105, paragraph [0016], [0019], [0021], [0080], [0156], Fig. 7, 19].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wakita into the teachings of Shinno to include a micro light emitting diode display, a substrate having a lower electrode having a main line part and a plurality of branch line parts which are connected each other by a thin film fuse on one major surface, the thin film fuse being provided in a gap between the main line part and each of the branch line parts, the thin film fuse being used to cut off the branch line part to which the lateral micro p-n light emitting diode chip with defection is connected from the main line part, for the purpose of providing a display for the device to function on, disconnecting due to an overcurrent to protect the device, increase resistance value, if a non-lighting state occurs in some electrode regions, the other electrode regions are not adversely affected, and improving ease of inspection.
Regarding claim 8, Shinno and Wakita teach the micro light emitting diode display according to claim 7.
Shinno and Wakita disclose the above claimed subject matter.
However, Shinno does not teach:
The micro light emitting diode display according to claim 7, wherein the substrate has a plurality of circuit units which can be independently driven and the lower electrode and the upper electrode are formed for each of the circuit units.
Wakita teaches:
The micro light emitting diode display [100, paragraph [0077], Fig. 7], wherein the substrate [30, paragraph [0016], [0020], Fig. 1-2, 5, 7] has a plurality of circuit units [corresponds to where electrodes 31 and 32 overlap, Fig. 1, 7] which can be independently driven [paragraph [0080], [0156]] and the lower electrode [31, paragraph [0015-0016], [0018-0020], [0022], [0029], [0078], [0080], [0156], Fig. 1, 7] and the upper electrode [32, paragraph [0015-0016], [0019], [0022], [0078], [0080], Fig. 1, 7] are formed for each of the circuit units [corresponds to where electrodes 31 and 32 overlap, Fig. 1, 7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wakita into the teachings of Shinno and Wakita to include the micro light emitting diode display, wherein the substrate has a plurality of circuit units which can be independently driven and the lower electrode and the upper electrode are formed for each of the circuit units, for the purpose of providing a display for the device to function on, disconnecting due to an overcurrent to protect the device, increase resistance value, if a non-lighting state occurs in some electrode regions, the other electrode regions are not adversely affected, and improving ease of inspection.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shinno (US 20190363233 A1), in view of Wakita (JP 2010087453 A) as applied to claim 7 above, and further in view of Tso (US 20170092691 A1).
Regarding claim 9, Shinno and Wakita teach the micro light emitting diode display according to claim 7.
Shinno and Wakita disclose the above claimed subject matter.
However, Shinno does not teach:
The micro light emitting diode display, wherein the display is a color display.
Wakita teaches:
The micro light emitting diode display [100, Fig. 7, 19], wherein the display [100, Fig. 7, 19] is a color display [paragraph [0031], [0072]].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wakita into the teachings of Shinno and Wakita to include the micro light emitting diode display, wherein the display is a color display, for the purpose of providing a display for the device to function on, achieving a multi colored display, improving user experience.
Shinno and Wakita do not teach:
one pixel is formed by an area including more than three circuit units adjacent to each other.
Tso teaches:
one pixel [350, paragraph [0083], [0088], Fig. 3A-3B] is formed by an area including more than three circuit units [350A, 350B, 350C, 350D, paragraph [0083], [0085-0086], Fig. 3A-3B] adjacent to each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tso into the teachings of Shinno and Wakita to include one pixel is formed by an area including more than three circuit units adjacent to each other, for the purpose of achieving a multi colored display, high density of array, improving light quality, improving user experience, easy to manufacture.
Response to Arguments
Applicant’s arguments with respect to independent claim 7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 1-2, in remarks filed March 16, 2026 that the current prior art of record does not teach the amendments made to independent claim 7. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art, the amended limitations of independent claim 7 can be overcome by newly cited primary reference Shinno (US 20190363233 A1), in view of newly cited secondary source Wakita (JP 2010087453 A).
Applicant argues on pages 1-2, in remarks filed March 16, 2026 that dependent claims 8-9 were also amended, and depend on independent claim 7. Applicant argues that dependent claims 8-9 should now be in condition for allowance. Examiner disagrees with Applicant; the amendments to dependent claims 8-9 can be overcome by newly cited primary reference Shinno (US 20190363233 A1), in view of newly cited secondary sources Wakita (JP 2010087453 A) and Tso (US 20170092691 A1).
In summary, the amended limitations of independent claim 7 can be overcome by newly cited primary reference Shinno (US 20190363233 A1), in view of newly cited secondary source Wakita (JP 2010087453 A). The amendments to dependent claims 8-9 can be overcome by newly cited primary reference Shinno (US 20190363233 A1), in view of newly cited secondary sources Wakita (JP 2010087453 A) and Tso (US 20170092691 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID MICHAEL HELBERG whose telephone number is (571)270-1422. The examiner can normally be reached Mon.-Fri. 8am-5pm EST.
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/D.M.H./Examiner, Art Unit 2815 03/26/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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