DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on September 1, 2022 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C.101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1-17 are directed to a machine or an article of manufacture. Claims 18-25 are directed to a process.
With respect to claim(s) 1, 9, and 18:
2A Prong 1: The claim(s) recite(s) an abstract idea. Specifically:
generate a bitmask; (Mental process – A person can mentally generate (think of) a bitmask or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
generate a vector output based on the bitmask, wherein the vector output includes non-zero bit indices in a first portion of the vector output, and wherein the non-zero bit indices correspond to non-zero values in the bitmask, (Mental process – A person can mentally generate (think of) a vector based on the bitmask or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
generate an offset based on the bitmask, wherein the offset indicates a start position in the vector output for the non-zero bit indices; (Mental process – A person can mentally generate (think of) an offset based on the bitmask or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
If claim limitations, under their broadest reasonable interpretation, cover performance of the limitations as a mental process, but for the recitation of generic computer components, then the claim limitations fall within the mathematical or mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea.
2A Prong 2: The additional elements recited in the claim(s) do not integrate the abstract idea into a practical application, individually or in combination.
Additional elements:
(Claim 1) A computing system comprising (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 9) A semiconductor apparatus comprising (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 9) one or more substrates; and (Mere recitation of a generic computer component – see § MPEP 2106.05(b)(I))
(Claim 9) logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 1) a converter to (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 1) an index generator coupled to the converter, wherein the index generator includes logic coupled to one or more substrates, (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 1) a plurality of processing elements to operate on a plurality of input vectors based on the vector output and the offset. (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
Since the claim as a whole, looking at the additional elements individually and in combination, does not contain any other additional elements that are indicative of integration into a practical application, the claim is directed to an abstract idea.
2B: The claim(s) do(es) not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
(Claim 1) A computing system comprising (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 9) A semiconductor apparatus comprising (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 9) one or more substrates; and (Mere recitation of a generic computer component – see § MPEP 2106.05(b)(I))
(Claim 9) logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 1) a converter to (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 1) an index generator coupled to the converter, wherein the index generator includes logic coupled to one or more substrates, (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
(Claim 1) a plurality of processing elements to operate on a plurality of input vectors based on the vector output and the offset. (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.
With respect to claim(s) 2, 10, and 19:
2A Prong 1: The claim(s) recite(s) an abstract idea. Specifically:
partition the bitmask into a plurality of segments, (Mental process – A person can mentally partition a bitmask into segments or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
generate the vector output and the offset in parallel for the plurality of segments to obtain a plurality of vector outputs, and (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
combine the plurality of vector outputs into a final vector output, wherein the final vector output includes non-zero bit indices in a first portion of the final vector output, and wherein the non-zero bit indices in the first portion of the final vector output correspond to the non-zero values in the bitmask. (Mental process – A person can mentally combine vectors or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
Additionally, the claim(s) do not recite any new additional elements that would amount to an integration of the abstract idea into a practical application (individually or in combination) or significantly more than the judicial exception.
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
With respect to claim(s) 3, 11, and 20:
2A Prong 2: The additional elements recited in the claim(s) do not integrate the abstract idea into a practical application, individually or in combination.
Additional elements:
wherein the vector output further includes zeros in a second portion of the vector output. (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
2B: The claim(s) do(es) not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the vector output further includes zeros in a second portion of the vector output. (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
With respect to claim(s) 4, 12, and 21:
2A Prong 1: The claim(s) recite(s) an abstract idea. Specifically:
to generate the vector output (Mental process – A person can mentally generate a vector or by using a pen and paper as a physical aid – see MPEP § 2106.04(a)(2)(III))
2A Prong 2: The additional elements recited in the claim(s) do not integrate the abstract idea into a practical application, individually or in combination.
Additional elements:
a multiplexer chain to (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
2B: The claim(s) do(es) not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
a multiplexer chain to (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
With respect to claim(s) 5, 13, 22:
2A Prong 1: The claim(s) recite(s) an abstract idea. Specifically:
count a number of zeros in the bitmask. (Mental process – A person can mentally count number of zeros in a bitmask – see MPEP § 2106.04(a)(2)(III))
Additionally, the claim(s) do not recite any new additional elements that would amount to an integration of the abstract idea into a practical application (individually or in combination) or significantly more than the judicial exception.
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
With respect to claim(s) 6, 14, and 23:
2A Prong 1: The claim(s) recite(s) an abstract idea. Specifically:
(Claim 6 and 14) generate the offset. (Mental process – A person can mentally generate (think of) an offset or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
(Claim 23) offset is generated (Mental process – A person can mentally generate (think of) an offset or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
2A Prong 2: The additional elements recited in the claim(s) do not integrate the abstract idea into a practical application, individually or in combination.
Additional elements:
a plurality of adders (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
2B: The claim(s) do(es) not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
a plurality of adders (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
With respect to claim(s) 7, 15, and 24:
2A Prong 1: The claim(s) recite(s) an abstract idea. Specifically:
wherein the vector output and the offset are to be generated on a per bitmask iteration basis (Mental process – A person can mentally generate (think of) a vector and an offset on a per bitmask iteration basis or by using the physical aid of a pen and paper – see MPEP § 2106.04(a)(2)(III))
Additionally, the claim(s) do not recite any new additional elements that would amount to an integration of the abstract idea into a practical application (individually or in combination) or significantly more than the judicial exception.
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
With respect to claim(s) 8, 16, and 25:
2A Prong 2: The additional elements recited in the claim(s) do not integrate the abstract idea into a practical application, individually or in combination.
Additional elements:
bypass/bypassing a storage of the vector output and the offset. (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
2B: The claim(s) do(es) not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
bypass/bypassing a storage of the vector output and the offset. (Mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).)
Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible. Therefore, the claim is not patent eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 18, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FRUMKIN (US 20200342632 A1), hereafter FRUMKIN.
Regarding Claim 1:
FRUMKIN teaches:
A computing system comprising: a converter to generate a bitmask; (FRUMKIN [0056] teaches: "FIG. 1B shows a block diagram of an example processing system 100 including a processor-implemented compressor 10 (i.e., a converter) and a processor-implemented decompressor 20 for compressing and/or decompressing sparse matrix arrays." FRUMKIN [0057] teaches: "The compressor 10 (i.e., converter) may be configured to access the sparse matrix array data 104 from the memory 150 and compress (i.e., generate) the sparse matrix array data into a compressed (i.e., a bitmask), diagonal storage format 102 including for example a mask and non-zero values in diagonal order.")
an index generator coupled to the converter, […] (FRUMKIN [0056] teaches: "FIG. 1B shows a block diagram of an example processing system 100 including a processor-implemented compressor 10 (i.e., a converter) and a processor-implemented decompressor 20 (i.e., an index generator) for compressing and/or decompressing sparse matrix arrays." FRUMKIN [FIG. 1B] teaches the compressor (i.e., a converter) transmitting data (i.e., coupled to) the decompressor (i.e., an index generator). FRUMKIN [0057] teaches: "The compressor 10 may be configured to access the sparse matrix array data 104 from the memory 150 and compress the sparse matrix array data into a compressed, diagonal storage format 102 including for example a mask and non-zero values in diagonal order.")
[…] wherein the index generator includes logic coupled to one or more substrates, the logic to: (FRUMKIN [0056] teaches: "The compressor 10 and/or decompressor 20 (i.e., the index generator) may be provided in the form of a CPU and/or GPU that executes instructions stored in non-transitory memory (i.e., includes logic). In some other examples, the compressor 10 and/or decompressor 20 may be provided in hardware as part of a memory controller such as a cache controller operatively coupled between a cache memory and a CPU and/or GPU." FRUMKIN [0272] teaches: "In an embodiment, the PPU 300 is a multi-threaded processor that is implemented on one or more integrated circuit devices. [...] A thread (e.g., a thread of execution) is an instantiation of a set of instructions (i.e., logic) configured to be executed by the PPU 300." FRUMKIN [0314] teaches: "In an embodiment, the PPU 300 is embodied on a single semiconductor substrate." FRUMKIN [0318] teaches: "The exemplary system 500 may be configured to implement the methods disclosed in this application (e.g., methods shown in FIG. 5, 6, or 8). The processing system 500 includes a CPU 530, switch 555, and multiple PPUs 300 each and respective memories 304. The NVLink 310 provides high-speed communication links between each of the PPUs 300." Examiner's note" Under BRI, logic coupled to one or more substrates can be interpreted as the set of instructions executed by the PPU embodied in the substrate.)
generate a vector output based on the bitmask, wherein the vector output includes non-zero bit indices in a first portion of the vector output, and wherein the non-zero bit indices correspond to non-zero values in the bitmask, […] (FRUMKIN [0174] teaches: “The method includes, for each column
j
in
M
, forming a vector of length
S
(
j
)
of indices of rows with entry 1, let it be
R
j
,
i
,
i
=
0
,
…
,
S
j
-
1
(step 90).” FRUMKIN [0177] teaches: “The function
R
[
j
,
i
]
is computed for each column
j
of mask
M
independently. One column of
M
can be represented as a Byte.
R
for byte B returns a list of positions of ones in
B
. Since
k
=
Q
[
j
]
+
i
assumes values from 0 to 31 at most once,
R
[
j
,
i
]
can be represented as
I
d
x
[
k
]
(i.e., generate a vector output). It means that each of threads in the warp will compute
J
[
k
]
and
I
d
x
[
k
]
that are needed for assigning right values to A or AT.” FRUMKIN [0178] teaches: “
I
d
x
[
k
]
indicates the row number (i.e., vector output includes non-zero bit indices in a first portion of the vector output) of nonzero element
k
(i.e., and wherein the non-zero bit indices correspond to non-zero values in the bitmask) in D.” FRUMKIN [0133] teaches: “Using functions
S
and
Q
, a vector of length
S
(
j
)
is formed for each column
j
in the bitmask (i.e., based on the bitmask) providing indices of rows with non-zero elements.” Examiner’s note: Under BRI, a first portion of the vector output can be interpreted as
I
d
x
[
k
]
, which contains the row numbers (i.e., non-zero bit indices) of nonzero elements.)
generate an offset based on the bitmask, wherein the offset indicates a start position in the vector output for the non-zero bit indices-; (FRUMKIN [0133] teaches: “function
S
is the column sum of cyclically shifted bitmask,
S
k
is the number non-zeroes in k-th diagonal, and
Q
(
k
)
is a prefix sum of
S
provides the start of k-th diagonal in the array of matrix values
D
.” FRUMKIN [0173] teaches: “
Q
[
j
]
will be start of diagonal
j
in vector
D
(step 88).” FRUMKIN [0174] teaches: “The method includes, for each column
j
in
M
, forming a vector of length
S
(
j
)
of indices of rows with entry 1, let it be
R
j
,
i
,
i
=
0
,
…
,
S
j
-
1
(step 90).” FRUMKIN [0177] teaches: “The function
R
[
j
,
i
]
is computed for each column
j
of mask
M
independently. One column of
M
can be represented as a Byte.
R
for byte B returns a list of positions of ones in
B
. Since
k
=
Q
[
j
]
+
i
assumes values from 0 to 31 at most once,
R
[
j
,
i
]
can be represented as
I
d
x
[
k
]
.” Examiner’s note: The vector
R
[
j
,
i
]
is represented as
I
d
x
[
k
]
, where
k
=
Q
j
+
i
. FRUMKIN [0177] teaches that
Q
[
j
]
is used to compute the
k
position for a column
j
. Therefore,
Q
[
j
]
identifies the start position in
I
d
x
[
k
]
for the positions of ones in the bitmask for column
j
. Thus,
Q
[
j
]
teaches the claimed offset, and computing
Q
[
j
]
teaches generating the claimed offset.)
a plurality of processing elements to operate on a plurality of input vectors based on the vector output and the offset. (FRUMKIN [0191] teaches loading matrices A and B (i.e., a plurality of input vectors) from memory into threads (i.e., processing elements) to perform matrix multiply and accumulate (MMA) operations (i.e., to operate) to compute matrix
C
as
C
=
A
*
B
. FRUMKIN [0186] teaches: “FIGS. 10A and 10B show a plurality of threads receiving (i.e., a plurality of processing elements to operate) vector D of compacted nonzero values along each diagonal in turn, vector
I
d
x
[
k
]
(i.e., based on the vector output)
indicating row number of the element of D assigned to thread k, and vector
J
[
k
]
indicating diagonal number of the element of D assigned to thread k.” FRUMKIN [0111], [0133] and [0159] teaches that threads may receive a prefix sum of S (i.e., offset) that provides the start of the non-zero values in vector D of the diagonal in turn (vector D contains the compacted nonzero values along each of a succession of diagonals in turn.).)
Regarding Claim 7:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN further teaches:
wherein the vector output and the offset are to be generated on a per bitmask iteration basis. (FRUMKIN [0132] teaches: “In some example non-limiting implementations, the bitmask is pre-processed into a function
S
indicating number of non-zeros on each diagonal and function
Q
indicating start of diagonal, with simple bitwise summation operations.” FRUMKIN [0177] teaches: “The function
R
[
j
,
i
]
is computed for each column
j
of mask M independently. One column of M can be represented as a Byte. R for byte B returns a list of positions of ones in B. Since
k
=
Q
[
j
]
+
i
assumes values from 0 to 31 at most once,
R
[
j
,
i
]
can be represented as
I
d
x
[
k
]
. It means that each of threads in the warp will compute
J
[
k
]
and
I
d
x
[
k
]
that are needed for assigning right values to A or AT.” Examiner’s note: Both
I
d
x
[
k
]
(i.e., vector output) and
Q
(i.e., offset) are generated by processing each column
j
of mask M individually.)
Regarding Claim 18:
The claim recites similar limitations as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale.
Regarding Claim 24:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN as applied respectively above to claims 1 and 18, and further in view of BOETTCHER (US 20150212972 A1), hereafter BOETTCHER.
Regarding Claim 2:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN further teaches:
[…] generate the vector output and the offset in parallel for the plurality of segments to obtain a plurality of vector outputs, and (FRUMKIN [Abstract] teaches: “Parallel processing may also be used to more efficiently compress and/or decompress.” FRUMKIN [0155] teaches: “The parallel processing system may be configured to control execution of a plurality of thread blocks with a plurality of warps in each block. Each warp includes a plurality of threads (e.g., 32 threads).” FRUMKIN [0156] teaches: “[0156] Each thread can independently process and store data using the on-chip registers.” FRUMKIN [0186] teaches: “FIGS. 10A and 10B show a plurality of threads receiving vector D of compacted nonzero values along each diagonal in turn, vector
I
d
x
[
k
]
(i.e., the vector output)
indicating row number of the element of D assigned to thread k, and vector
J
[
k
]
indicating diagonal number of the element of D assigned to thread k.” FRUMKIN [0177] teaches: “The function
R
[
j
,
i
]
is computed for each column
j
of mask M independently. One column of M can be represented as a Byte (i.e., segment). R for byte B returns a list of positions of ones in B. Since
k
=
Q
[
j
]
+
i
assumes values from 0 to 31 at most once,
R
[
j
,
i
]
can be represented as
I
d
x
[
k
]
. It means that each of threads in the warp will compute
J
[
k
]
and
I
d
x
[
k
]
(i.e., generate the vector output […] in parallel for the plurality of segments to obtain a plurality of vector outputs) that are needed for assigning right values to A or AT.” Examiner’s note: Under BRI, the offset can be interpreted as
Q
[
j
]
. Additionally, FRUMKIN [Abstract] teaches compressing and decompressing in parallel. In order to compute
I
d
x
[
k
]
, the prefix sum
Q
(
j
)
must be computed first, and this process can be done in parallel for each column represented as a Byte in M. Therefore, under BRI, generate […] the offset in parallel can be interpreted as independently and in parallel computing the prefix sum of
S
, which is
Q
(
j
)
.)
However, FRUMKIN is not relied upon for teaching, but BOETTCHER teaches: partition the bitmask into a plurality of segments, […] (BOETTCHER [0019] teaches partitioning a vector into P groups of adjacent vector elements (i.e., plurality of segments). Examiner’s note: Under BRI, the bitmask can be interpreted as the vector being partitioned into P groups.)
combine the plurality of vector outputs into a final vector output, wherein the final vector output includes non-zero bit indices in a first portion of the final vector output, and wherein the non-zero bit indices in the first portion of the final vector output correspond to the non-zero values in the bitmask. (BOETTCHER [0019] teaches combining (i.e., combine) intermediate results form a vector operation into a final result vector (i.e., final vector output).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and BOETTCHER before them, to include BOETTCHER's vector partitioning and combining into final result vector in FRUMKIN's compression and decompression method. One would have been motivated to make such a combination in order to achieve balance between the desired the number of operations and desired performance (BOETTCHER [0082] and [0113]).
Regarding Claim 19:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale.
Claims 3, 6, 20 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN as applied respectively above to claims 1 and 18, and further in view of LIN (US 6781528 B1), hereafter LIN.
Regarding Claim 3:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN is not relied upon for teaching, but LIN teaches:
wherein the vector output further includes zeros in a second portion of the vector output. (LIN [Col 10, lines 1-14] and [Col 16, lines 38-47] teaches appending zeros (i.e., includes zeros) to a packed vector until filling up the space in the resulting vector. Specifically, LIN [Col 16, lines 38-47] teaches: “In scenario 2230, empty bit stream 2233 in vector vB is packed into vector vA which is in an underflow condition. Since the empty bit stream (a bit stream of a zero bit length) is used to indicate the end of a string of bit streams to be packed, bits of zeros are appended to bit stream 2231 to fill up the space in the resulting vector vD (2235), which is in an end condition, so that the packed bit segment can be stored away. When a vector is in an end condition, the process for packing a new string of bit streams can be started.” Examiner’s note: Under BRI, a second portion can be interpreted as the portion of zeros that has been appended to the resulting vD vector (i.e., vector output).)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and LIN before them, to include LIN's appending zeros to packed vectors in FRUMKIN’s compression and decompression method. Specifically, FRUMKIN computing
I
d
x
[
k
]
entries corresponding to the nonzero bit indices, as shown above with respect to claim 1. LIN teaches appending zeros to a resulting vector vD after packed data so that the packed bit segment can be stored away. Therefore, applying LIN’s appending of zeros to FRUMKIN’s generated
I
d
x
[
k
]
entries would produce a vector output having a first portion with nonzero bit indices and a second portion of appended zeros to fill up the remaining space. One would have been motivated to make such a combination in order to efficiently concatenate and pack bit streams of variable lengths into a continuous stream of bits (LIN [Col 15, lines 55-64]) and to fill the resulting vector vD with appended zeros so that the packed bit segment can be stored away (LIN [Col 16, lines 38-47]).
Regarding Claim 6:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN is not relied upon for teaching, but LIN teaches:
wherein the logic includes a plurality of adders to generate the offset. (LIN [Col 1, lines 34-45] and [Col 7, lines 36-57] teach adders 431-437 (i.e., plurality of adders) that increase by one if the bit value in a vector (vA) is zero and computes the zero run value (counts of consecutive zero elements immediately preceding a non-zero element) (i.e., offset), and then a multiplexer stores the computed zero run value in another vector (vD).)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and LIN before them, to include LIN's adders counting the zero bit values in a vector in FRUMKIN's compression and decompression method. One would have been motivated to make such a combination in order to efficiently concatenate and pack bit streams of variable lengths into a continuous stream of bits (LIN [Col 15, lines 55-64]).
Regarding Claim 20:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Regarding Claim 23:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 6 and is rejected for similar reasons as claim 6 using similar teachings and rationale.
Claims 4-5 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN as applied respectively above to claims 1 and 18, and further in view of OVSIANNIKOV (US 20200336154 A1), hereafter OVSIANNIKOV.
Regarding Claim 4:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN further teaches:
a multiplexer […] to generate the vector output. (FRUMKIN [0141] and [0111] teaches a multiplexer for generating the non-zero value vector.)
However, FRUMKIN is not relied upon for teaching, but OVSIANNIKOV teaches: wherein the logic includes a multiplexer chain to generate the vector […] (OVSIANNIKOV [0143] and [0101] teaches a plurality of multiplexers (i.e., multiplexer chain) accompanied with control logic. Additionally, OVSIANNIKOV [FIG. 6F] teaches a plurality of connected multiplexers 631. Furthermore, OVSIANNIKOV [0103] teaches that the multiplexer includes a zero bit mask generator that outputs a vector.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and OVSIANNIKOV before them, to include OVSIANNIKOV's multiplexer chains in FRUMKIN's compression and decompression method. One would have been motivated to make such a combination in order to efficiently permute data for packing and unpacking data in a parallel (OVSIANNIKOV [0056]).
Regarding Claim 5:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN is not relied upon for teaching, but OVSIANNIKOV teaches:
wherein to generate the offset, the logic is to count a number of zeros in the bitmask. (OVSIANNIKOV [0184] teaches counting the zero bits in the zero bit mask (i.e., number of zeros in the bitmask) to provide the offset into compressed data.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and OVSIANNIKOV before them, to include OVSIANNIKOV's counting the zero bits in the bit mask to provide the offset into compressed data in FRUMKIN's compression and decompression method. One would have been motivated to make such a combination in order to efficiently permute data for packing and unpacking data in a parallel (OVSIANNIKOV [0056]).
Regarding Claim 21:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale.
Regarding Claim 22:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale.
Claims 8 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN as applied respectively above to claims 1 and 18, and further in view of VALENTINE (US 20160188336 A1), hereafter VALENTINE.
Regarding Claim 8:
FRUMKIN teaches the elements of claim 1 as outlined above. FRUMKIN is not relied upon for teaching, but VALENTINE teaches:
wherein the logic is further to bypass a storage of the vector output and the offset. (VALENTINE [0076] teaches a bypass network that can bypass or forward just completed results that have not yet been written to the register file (i.e., storage) for new dependent "micro operations" (also called micro op or uops).)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and VALENTINE before them, to include VALENTINE's bypass network in FRUMKIN’s compression and decompression method. The
I
d
x
[
k
]
vector and
Q
can be the just completed results from VALENTINE. One would have been motivated to make such a combination in order to benefit from higher pipeline throughput and improved performance (VALENTINE [0044]).
Regarding Claim 25:
FRUMKIN teaches the elements of claim 18 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 8 and is rejected for similar reasons as claim 8 using similar teachings and rationale.
Claims 9, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN in view of BAGHSORKHI (US 20190042926 A1), hereafter BAGHSORKHI.
Regarding Claim 9:
The claim recites similar limitations as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale. Additionally, FRUMKIN teaches:
one or more substrates (FRUMKIN [0272] teaches a parallel processing unit (PPU) implemented in one or more integrated circuit devices. FRUMKIN [0314] teaches that the PPU is embodied on a single semiconductor substrate.)
However, FRUMKIN is not relied upon for teaching, but BAGHSORKHI teaches: wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (BAGHSORKHI [0071] teaches: “[…] logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic […].”)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN and BAGHSORKHI before them, to include BAGHSORKHI's logic coupled to one or more substrates in FRUMKIN's compression and decompression method. One would have been motivated to make such a combination in order to implement the method in an integrated circuit device (BAGHSORKHI [0049]).
Regarding Claim 15:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. Additionally, the claim recites similar limitations as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Regarding Claim 17:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. BAGHSORKHI further teaches:
wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. (BAGHSORKHI [0017] teaches "the logic 22 coupled to the one or more substrates 21 may include transistor channel regions that are positioned within the one or more substrates 21.")
Claims 10 rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN in view BAGHSORKHI as applied to claim 9 above, and further in view of BOETTCHER.
Regarding Claim 10:
FRUMKIN in view of and BAGHSORKHI teaches the elements of claim 9 as outlined above. FRUMKIN further teaches:
wherein the logic is further to: […] generate the vector output and the offset in parallel for the plurality of segments to obtain a plurality of vector outputs; (FRUMKIN [Abstract] teaches: “Parallel processing may also be used to more efficiently compress and/or decompress.” FRUMKIN [0155] teaches: “The parallel processing system may be configured to control execution of a plurality of thread blocks with a plurality of warps in each block. Each warp includes a plurality of threads (e.g., 32 threads).” FRUMKIN [0156] teaches: “[0156] Each thread can independently process and store data using the on-chip registers.” FRUMKIN [0186] teaches: “FIGS. 10A and 10B show a plurality of threads receiving vector D of compacted nonzero values along each diagonal in turn, vector
I
d
x
[
k
]
(i.e., the vector output)
indicating row number of the element of D assigned to thread k, and vector
J
[
k
]
indicating diagonal number of the element of D assigned to thread k.” FRUMKIN [0177] teaches: “The function
R
[
j
,
i
]
is computed for each column
j
of mask M independently. One column of M can be represented as a Byte (i.e., segment). R for byte B returns a list of positions of ones in B. Since
k
=
Q
[
j
]
+
i
assumes values from 0 to 31 at most once,
R
[
j
,
i
]
can be represented as
I
d
x
[
k
]
. It means that each of threads in the warp will compute
J
[
k
]
and
I
d
x
[
k
]
(i.e., generate the vector output […] in parallel for the plurality of segments to obtain a plurality of vector outputs) that are needed for assigning right values to A or AT.” Examiner’s note: Under BRI, the offset can be interpreted as
Q
[
j
]
. Additionally, FRUMKIN [Abstract] teaches compressing and decompressing in parallel. In order to compute
I
d
x
[
k
]
, the prefix sum
Q
(
j
)
must be computed first, and this process can be done in parallel for each column represented as a Byte in M. Therefore, under BRI, generate […] the offset in parallel can be interpreted as independently and in parallel computing the prefix sum of
S
, which is
Q
(
j
)
.)
However, FRUMKIN in view of BAGHSORKHI is not relied upon for teaching, but BOETTCHER teaches: partition the bitmask into a plurality of segments; (BOETTCHER [0019] teaches partitioning a vector into P groups of adjacent vector elements (i.e., plurality of segments). Examiner’s note: Under BRI, the bitmask can be interpreted as the vector being partitioned into P groups.)
combine the plurality of vector outputs into a final vector output, wherein the final vector output includes non-zero bit indices in a first portion of the final vector output, and wherein the non-zero bit indices in the first portion of the final vector output correspond to the non-zero values in the bitmask. (BOETTCHER [0019] teaches combining (i.e., combine) intermediate results form a vector operation into a final result vector (i.e., final vector output).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN, BAGHSORKHI, and BOETTCHER before them, to include BOETTCHER's vector partitioning and combining into final result vector in FRUMKIN and BAGHSORKHI's compression and decompression method. One would have been motivated to make such a combination in order to achieve balance between the desired the number of operations and desired performance (BOETTCHER [0082] and [0113]).
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN in view of BAGHSORKHI as applied to claim 9 above, and further in view of LIN.
Regarding Claim 11:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. FRUMKIN in view of BAGHSORKHI is not relied upon for teaching, but LIN teaches:
wherein the vector output further includes zeros in a second portion of the vector output. (LIN [Col 10, lines 1-14] and [Col 16, lines 38-47] teaches appending zeros (i.e., includes zeros) to a packed vector until filling up the space in the resulting vector. Specifically, LIN [Col 16, lines 38-47] teaches: “In scenario 2230, empty bit stream 2233 in vector vB is packed into vector vA which is in an underflow condition. Since the empty bit stream (a bit stream of a zero bit length) is used to indicate the end of a string of bit streams to be packed, bits of zeros are appended to bit stream 2231 to fill up the space in the resulting vector vD (2235), which is in an end condition, so that the packed bit segment can be stored away. When a vector is in an end condition, the process for packing a new string of bit streams can be started.” Examiner’s note: Under BRI, a second portion can be interpreted as the portion of zeros that has been appended to the resulting vD vector (i.e., vector output).)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN, BAGHSORKHI, and LIN before them, to include LIN's appending zeros to packed vectors in FRUMKIN and BAGHSORKHI’s compression and decompression method. Specifically, FRUMKIN computing
I
d
x
[
k
]
entries corresponding to the nonzero bit indices, as shown above with respect to claim 1. LIN teaches appending zeros to a resulting vector vD after packed data so that the packed bit segment can be stored away. Therefore, applying LIN’s appending of zeros to FRUMKIN’s generated
I
d
x
[
k
]
entries would produce a vector output having a first portion with nonzero bit indices and a second portion of appended zeros to fill up the remaining space. One would have been motivated to make such a combination in order to efficiently concatenate and pack bit streams of variable lengths into a continuous stream of bits (LIN [Col 15, lines 55-64]) and to fill the resulting vector vD with appended zeros so that the packed bit segment can be stored away (LIN [Col 16, lines 38-47]).
Regarding Claim 14:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. FRUMKIN in view of BAGHSORKHI is not relied upon for teaching, but LIN teaches:
wherein the logic includes a plurality of adders to generate the offset. (LIN [Col 1, lines 34-45] and [Col 7, lines 36-57] teach adders 431-437 (i.e., plurality of adders) that increase by one if the bit value in a vector (vA) is zero and computes the zero run value (counts of consecutive zero elements immediately preceding a non-zero element) (i.e., offset), and then a multiplexer stores the computed zero run value in another vector (vD).)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN, BAGHSORKHI, and LIN before them, to include LIN's adders counting the zero bit values in a vector in FRUMKIN and BAGHSORKHI's compression and decompression method. One would have been motivated to make such a combination in order to efficiently concatenate and pack bit streams of variable lengths into a continuous stream of bits (LIN [Col 15, lines 55-64]).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN in view of BAGHSORKHI as applied to claim 9 above, and further in view of OVSIANNIKOV.
Regarding Claim 12:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. FRUMKIN further teaches:
a multiplexer […] to generate the vector output. (FRUMKIN [0141] and [0111] teaches a multiplexer for generating the non-zero value vector.)
However, FRUMKIN in view of BAGHSORKHI is not relied upon for teaching, but OVSIANNIKOV teaches: wherein the logic includes a multiplexer chain to generate the vector […] (OVSIANNIKOV [0143] and [0101] teaches a plurality of multiplexers (i.e., multiplexer chain) accompanied with control logic. Additionally, OVSIANNIKOV [FIG. 6F] teaches a plurality of connected multiplexers 631. Furthermore, OVSIANNIKOV [0103] teaches that the multiplexer includes a zero bit mask generator that outputs a vector.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN, BAGHSORKHI, and OVSIANNIKOV before them, to include OVSIANNIKOV's multiplexer chains in FRUMKIN and BAGHSORKHI's compression and decompression method. One would have been motivated to make such a combination in order to efficiently permute data for packing and unpacking data in a parallel (OVSIANNIKOV [0056]).
Regarding Claim 13:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. FRUMKIN in view of BAGHSORKHI is not relied upon for teaching, but OVSIANNIKOV teaches:
wherein to generate the offset, the logic is to count a number of zeros in the bitmask. (OVSIANNIKOV [0184] teaches counting the zero bits in the zero bit mask (i.e., number of zeros in the bitmask) to provide the offset into compressed data.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN, BAGHSORKHI, and OVSIANNIKOV before them, to include OVSIANNIKOV's counting the zero bits in the bit mask to provide the offset into compressed data in FRUMKIN and BAGHSORKHI's compression and decompression method. One would have been motivated to make such a combination in order to efficiently permute data for packing and unpacking data in a parallel (OVSIANNIKOV [0056]).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over FRUMKIN in view of BAGHSORKHI as applied to claim 9 above, and further in view of VALENTINE.
Regarding Claim 16:
FRUMKIN in view of BAGHSORKHI teaches the elements of claim 9 as outlined above. FRUMKIN in view of BAGHSORKHI is not relied upon for teaching, but VALENTINE teaches:
wherein the logic is further to bypass a storage of the vector output and the offset. (VALENTINE [0076] teaches a bypass network that can bypass or forward just completed results that have not yet been written to the register file (i.e., storage) for new dependent "micro operations" (also called micro op or uops).)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FRUMKIN, BAGHSORKHI, and VALENTINE before them, to include VALENTINE's bypass network in FRUMKIN and BAGHSORKHI’s compression and decompression method. The
I
d
x
[
k
]
vector and
Q
can be the just completed results from VALENTINE. One would have been motivated to make such a combination in order to benefit from higher pipeline throughput and improved performance (VALENTINE [0044]).
Response to Arguments
Applicant's arguments filed on April 1, 2026 have been fully considered.
Applicant's arguments regarding the 35 U.S.C. 101 rejections of the previous office action have been fully considered but are not persuasive. Applicant argues:
“Claims 1-25 stand rejected under 35 U.S.C. § 101 because the claims are alleged directed to non-statutory subject matter. The Office has rejected the claims, alleging that "generate a bitmask," "generate a vector output," and "generate an offset" are directed to a "Mathematical calculation and/or mental process." The Office further alleges under Step 2A, Prong 2, that the additional elements merely recite generic computer components or add the words "apply it." Applicant respectfully disagrees.
The Office has erred by analyzing the claims at an impermissibly high level of generality, reducing specific technical steps to a generic 'abstract idea.' The claims are not directed to a mathematical calculation or a mental process. The claimed steps involve specific bit-level manipulations and structural data generation (e.g., a vector output with non-zero bit indices in a leftmost portion, and an offset indicating a start position) that the human mind is not equipped to perform in real-time. These are technical operations inextricably tied to computer hardware and architecture.
Even if the claims were considered to recite an abstract idea under Step 2A, Prong 1, the claims are eligible because they integrate the concept into a practical application under Step 2A, Prong 2. Ex parte Desjardins, Appeal No. 2024-000567 (PTAB September 26, 2025, Appeals Review Panel Decision) is binding precedent that prohibits ignoring specific claim limitations that integrate an abstract idea into a practical application. As stated in Desjardins, "Examiners and panels should not evaluate claims at such a high level of generality" such that potentially meaningful technical limitations are dismissed without adequate explanation. By equating the specific logic and data structures in the claims with generic computer components, the Examiner has ignored the technological reality of the invention and evaluated the claims at an impermissibly high level of generality.”
Examiner respectfully disagrees. Generating a bitmask involves creating zero and one indicators for positions of zero and non-zero values in data. For example, if the data is [0, 1, 0, 2], the corresponding bitmask would be [0, 1, 0, 1]. This can be performed entirely in the human mind or with pen and paper. Generating a vector output based on the bitmask involves listing positions indicated by ones in the bitmask. For example, the ones are located at indices [1, 3]. This can also be performed entirely in the human mind or with pen and paper. Generating the offset involves counting the number of zeros in the bitmask. For example, in bitmask [0, 1, 0, 1] there are two zeros, and the offset is 2. This can also be performed entirely in the human mind or with pen and paper.
Applicant’s analysis regarding real time operation is factually incorrect and addresses an unclaimed invention. None of the claims require performance within a specific amount of time or require a specific processing rate. Applicant does not define “real-time” in a way that excludes performance in the human mind or by a human with pen and paper. Without a time-limit or specific rate of processing, “real-time” does not distinguish the claimed limitations from mental processes or acts performed by a human with pen and paper. The additional limitations recited in the claim do not tie the abstract ideas to computer hardware or computer architecture. As explained in Step 2A Prong 2 and 2B for claims 1, 9, the additional elements are mere instructions to apply an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea – see MPEP 2106.05(f).
Applicant further argues:
“Under Enfish, LLC v. Microsoft Corp. and Desjardins, claims directed to an improvement in computer functionality are not abstract. The Specification explicitly describes the technical problems with prior art sparse matrix processing, such as high memory requirements and resource underutilization (e.g., paragraphs [0002], [0020], and [0028]). The claimed sparse index generator improves memory usage and avoids resource underutilization by generating the vector output and offset in a specific manner that enables hardware to scale depending on the number of non-zero elements. Furthermore, the present specification explains that the generation of the vector output and offset allows the system to bypass storage of the vector output and the offset entirely, avoiding a high penalty of area and underutilization of resources (see, e.g., paragraphs [0020] and [0028]).
The pending claims specifically reflect this non-abstract improvement to the internal operation of the computer. For example, the claims recite a specific data structure-a vector output wherein the non-zero bit indices are in a first portion of the vector output, and an offset indicating a start position in the vector output for the non-zero bit indices. Furthermore, certain claims (e.g., claims 8, 16, and 25) explicitly recite that the logic is further to bypass a storage of the vector output and the offset. The claims are directed to a specific implementation that improves how the computer stores and processes sparse matrices, rather than merely using a computer as a tool to perform an abstract idea.
In Desjardins, the Appeals Review Panel found claims eligible because they recited a specific method of training that resulted in a technological improvement (e.g., reduced storage, prevention of forgetting). Similarly, Applicant's claims recite specific steps of generating a vector output with non-zero bit indices in a first portion and an offset indicating a start position, which achieves the specific technical benefits of bypassing storage and reducing memory usage found in the Specification. Thus, like Desjardins and Enfish, the claims are directed to a nonabstract improvement in computer functionality.
Because the claims recite specific technical features that solve a computer-centric problem and improve the functioning of the computer itself, they integrate any alleged abstract idea into a practical application under Step 2A, Prong 2. Therefore, the claims are patent-eligible under 35 U.S.C. § 101. Applicant respectfully requests withdrawal of the 35 U.S.C. § 101 rejection.”
Examiner respectfully disagrees. The alleged improvement in computer functionality comes from omitting storage of the generated output vector and offset. The claims and specification do not describe bypassing storage as a change in how memory stores, reads, writes, or addresses information. The alleged processing benefit comes from using the generated vector output and offset to avoid processing zero values. Additionally, avoiding processing for zero values reduces the number of operations performed, but it does not change how the computer operates. Similarly, the alleged scaling of hardware depending on the number of non-zero values merely describes using the generated vector output and offset to decide how much processing should be assigned to existing hardware in the system, and does not constitute an improvement in how the hardware operates. Accordingly, the claims do not integrate the abstract ideas into a practical application.
Applicant's arguments regarding the 35 U.S.C. 103 rejections of the previous office action have been fully considered but are moot in view of the new grounds of rejection set forth in this Office Action. Claims 1 and 18 are now rejected under 35 U.S.C. 103 by FRUMKIN alone. Claim 9 is rejected under 35 U.S.C. 103 by FRUMKIN in view of BAGHSORKHI. References ZHANG and WANG have been removed from the rejection set.
Regarding claim 1, FRUMKIN [0178] teaches the generated vector output as
I
d
x
[
k
]
. Which contains the row numbers (i.e., non-zero bit indices) of nonzero elements, as shown in the 102 rejections above. Claim 9 has new grounds of rejections using FRUMKIN in view of BAGHSORKHI, as shown in the 102 rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alvaro S Laham Bauzo whose telephone number is (571)272-5650. The examiner can normally be reached Mon-Fri 7:30 AM - 11:00 AM | 1:00 PM - 5:30 PM ET.
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/A.S.L./Examiner, Art Unit 2146
/USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146
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