DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 08/03/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 08/03/2026 in reply to the final rejection mailed on 04/01/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 2 & 25 are cancelled, and Claims 32, 33, & 34 are added. Accordingly, pending in this Office action are claims 1, 3-10, 20-4, & 27-34.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4, 6, 7 & 33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 4, the limitation “wherein a sidewall of the metal bump is exposed to the recess” raises new matter issues in view of the amended limitation of Claim 1, “and wherein in a cross-section of the package, a bottommost surface of the solder region is in the recess and is higher than the metal bump.” The recess formed in Claim 1 laterally extends beyond edges of the metal bump. For the bottommost surface of the solder region to remain higher than the metal bump, there must not be a portion of the sidewall of the metal bump exposed to the recess. Otherwise, the solder would fill in and become lower than the metal bump.
Regarding Claim 6, the limitation “wherein the recess extends to the first top surface of the first dielectric layer, and wherein in the photolithography process, the first dielectric layer is not patterned” has similar issues to Claim 4. By having the recess extend to the first top surface of the first dielectric layer, a portion of recess is open for the solder region to have a bottommost surface below the metal bump.
Claim 7 is rejected as being dependent on Claim 6.
Regarding Claim 33, the limitation “wherein a portion of the photo-sensitive layer directly underlying the recess and comprises a fourth top surface lower the second top surface” raises new matter issues in view of the amended limitation of Claim 1, “and wherein in a cross-section of the package, a bottommost surface of the solder region is in the recess and is higher than the metal bump.” The recess formed in Claim 1 laterally extends beyond edges of the metal bump, and therefore portions of the photo-sensitive layer underlying the recess are formed. However, if the fourth top surface to be lower than the second top surface of the metal bump, then the bottommost surface of the solder region would no longer be higher than the metal bump. Applicant’s drawings (see, e.g., figs. 13, 14a-b, & 15) show both configurations, but do not show how the two limitations would exist without contradicting one another.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 31, & 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Hsieh (US 20150041985) and further in view of Yu (US 20150364386).
Regarding Claim 1, Yang (see, e.g., figs. 9a-9t) shows a method comprising:
forming a first package component (entire device of fig. 9s, hereinafter “P1”) comprising:
forming a first dielectric layer 32 (see, e.g., fig. 9h, para.0085) comprising a first top surface (topmost surface of 32);
forming a first conductive feature (see, e.g., figs. 9k-n), wherein the first conductive feature comprises:
a via 36 (lower portion beneath the topmost surface of 32, hereinafter “36v”) extending into the first dielectric layer;
and a metal bump 36 (upper portion above the topmost surface of 32, hereinafter “36b”) comprising a second top surface higher than the first top surface of the first dielectric layer,
wherein the via and the metal bump are formed in a same plating process (see, e.g., para.0088);
dispensing a photo-sensitive layer 40 (see, e.g., fig. 9o, para.0092),
wherein the photo-sensitive layer covers the metal bump (fig. 9o);
and performing a process to form a recess 40a (see, e.g., fig. 9p, para.0093) in the photo-sensitive layer and to reveal the metal bump 36b (top surface is revealed),
and wherein the photo-sensitive layer comprises a third top surface higher than the metal bump (top surface of 40 is above all of 36b);
and bonding a second package component 46 (see, e.g., fig. 9t, para.0097) to the first package component P1 to form a package (hereinafter “P1 & 46”),
wherein a solder region 54 (see, e.g., para.0098) extends into the recess to bond the metal bump to a second conductive feature 50 (see, e.g., para.0098) in the second package component 46
and wherein in a cross-section of the package, a bottommost surface of the solder region 54 is in the recess 40a and is higher than the metal bump 36b (bottommost surface of 54 is on top of 36b and is therefore higher than 36b).
Yang, however, fails to show
wherein the recess extends laterally beyond edges of the metal bump,
Hsieh (see, e.g., fig. 11, para.0134-0139), in a similar method to Yang, shows a configuration of an NSMD interconnect
wherein the recess 322 extends laterally beyond an edge of the metal bump 274,
Hsieh (see, e.g., para.0147) states the configuration of a NSMD interconnect would reduce the stress of the interconnection structure on which a solder is bonded to a metal pad.
The configuration of Hsieh is incorporated in the method of Yang.
Hsieh states the thickness T4 of the portion of the recess extending laterally beyond the edge 324 can be the same thickness and therefore at the same height as the metal bump 274. Therefore the limitation
“and wherein in a cross-section of the package, a bottommost surface of the solder region is in the recess and is higher than the metal bump” would still be shown when considering the configuration of Hsieh.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Hsieh in the method of Yang to reduce the stress of the interconnection structure on which a solder is bonded to a metal pad.
Yang, in view of Hsieh, however, fails to show,
performing a photolithography process to form the recess in the photo-sensitive layer
Yu (see, e.g., fig. 2, para.0030) teaches a photolithography process (light exposure) forming a on photo-sensitive layer 203 to expose a metal feature 113 would facilitate a safe process for forming a recess without harming the structure.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the photolithography process of Yu in the method of Yang, in view of Hsieh, to facilitate a safe process for forming a recess without harming the structure.
Regarding Claim 5, Yang (see, e.g., para.0078, para.0085), in view of Hsieh and further in view of Yu, shows the method of claim 1,
wherein the first dielectric layer 24 & 32 comprises an additional photo-sensitive layer 24 (see, e.g., para.0078)
Regarding Claim 31, Yang (see, e.g., figs. 9l-o, para.0089-0090), in view of Hsieh and further in view of Yu, shows the method of claim 1,
wherein the via and the metal bump are formed using a same plating mask 38 (see, e.g., figs. 9l-m, para.0089);
and wherein the method further comprises:
removing the plating mask to reveal a top surface of the first dielectric layer (in openings 38a, see, e.g., figs. 9m-n, para.0090),
wherein the photo-sensitive layer is formed after the plating mask is removed (see, e.g., fig. 9o),
and the photo-sensitive layer physically contacts the top surface of the first dielectric layer (see, e.g., fig. 9o)
Regarding the limitation, “removing the plating mask to reveal a top surface of the first dielectric layer,” Yang, in view of Yu, states openings 38a are formed as part of the plating mask 38 is removed and then layers 34 & 36 are removed, revealing a top surface of the first dielectric layer. Therefore, removing the plating mask contributes to revealing the top surface of the first dielectric layer and renders the limitation obvious.
Regarding Claim 32, Yang, in view of Hsieh (see, e.g., fig. 11) and further in view of Yu, shows the method of claim 1,
wherein at a time after the photolithography process is performed,
a portion of the photo-sensitive layer 40 (the portion of 40 is underneath the recess 40a in the same manner portion 324 is underneath the recess 322 in fig. 11 of Hsieh) is directly under and overlapped by the recess.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Hsieh (US 20150041985) & Yu (US 20150364386) and further in view of Kim (US 20190198354).
Regarding Claim 8, Yang, in view of Hsieh & Yu, shows the method of claim 1
Yang, in view of Hsieh & Yu, however, fails to show
further comprising, after the photo-sensitive layer is dispensed and before the photolithography process is performed, performing a planarization process on the photo-sensitive layer.
Kim (see, e.g., figs. 2b-d, para.0040-0042, para.0052), in a similar method to Yang, in view of Hsieh & Yu, shows a configuration wherein after dispensing photo-sensitive layer 124 and before a subsequent photolithography process, performing a planarization process would provide a uniform and level surface to reduce error in forming a recess.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Kim in the method of Yang, in view of Hsieh & Yu, to provide a uniform and level surface to reduce error in forming a recess.
Claims 9 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Hsieh (US 20150041985) & Yu (US 20150364386) and further in view of Kim (20190198354).
Regarding Claim 9, Yang, in view of Hsieh & Yu, shows the method of claim 1,
Yang, in view of Hsieh & Yu, however, fails to show
wherein at a time the photolithography process is started, the third top surface of the photo-sensitive layer comprises: a lower portion laterally offset from the metal bump;
and a higher portion directly over the metal bump,
wherein the higher portion is higher than the lower portion.
Kim (see, e.g., figs. 2a-b, para.0040-0041), in a similar method to Yang, in view of Hsieh & Yu, shows a configuration for spin-coating as a method for depositing a photo-sensitive layer on a plurality of metal bumps would provide excellent adherence and conformity to the space between the metal bumps.
Kim shows that when the photo-sensitive layer is formed
the third top surface of the photo-sensitive layer 124 comprises:
a lower portion (lower level of 124 between 123) laterally offset from the metal bump 123;
and a higher portion (higher level of 124 over 123) directly over the metal bump,
wherein the higher portion is higher than the lower portion.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Kim in the method of Yang, in view of Hsieh & Yu, to provide excellent adherence and conformity between metal bumps when forming the photo-sensitive layer.
Regarding Claim 10, Kim, in view of Hsieh &Yu and further in view of Kim, shows the method of claim 9,
wherein after the photolithography process is finished, the third top surface of the photo-sensitive layer 40 comprises a raised portion (the raised portion is the top surface of 40 that surrounds the recess as shown in figure the surface of 320 in fig. 11 of Hsieh, see, e.g., annotated figure 2) surrounding the recess,
and wherein the raised portion is a part of the higher portion (since the portion was formed from and through it).
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Yu (US 20150364386) and further in view of Hsieh (US 20150041985).
Regarding Claim 21, Yang (see, e.g., figs. 9a-9t) shows a method comprising:
forming a first package component (entire device of fig. 9s, hereinafter “P1”) comprising:
forming a conductive feature (see, e.g., figs. 9k-n) comprising:
forming a via 36 (lower portion beneath the topmost surface of 32, hereinafter “36v”) embedded in a dielectric layer 32 (see, e.g., fig. 9h, para.0085);
and forming a metal bump 36 (upper portion above the topmost surface of 32, hereinafter “36b”) protruding higher than a first top surface of the dielectric layer
wherein the via and the metal bump are formed in a same plating process (see, e.g., para.0088);
and a photo-sensitive structure 40 (see, e.g., fig. 9o, para.0092) extending from a lower level to a higher level,
wherein the lower level is lower than a second top surface of the metal bump (lower level of 40 is in direct contact with dielectric layer 32),
and the higher level is higher than the second top surface of the metal bump 32b (above the topmost surface of 32b, see, e.g., fig. 9s);
and wherein the photo-sensitive structure comprises a recess 40a, with the metal bump being in the recess;
wherein the photo-sensitive structure is joined to the metal bump (direct physical contact),
Yang, however, fails to show,
performing a coating and light-exposure process to form the photo-sensitive structure
Yu (see, e.g., fig. 2, para.0026, para.0030) teaches a photolithography process (light exposure & coating) forming the photo-sensitive structure 203 would facilitate a safe process for forming a recess without harming the structure.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the photolithography process of Yu in the method of Yang, to facilitate a safe process for forming a recess without harming the structure.
Yang, in view of Yu, however, fails to show
and plating and reflowing a solder region
wherein the solder region extends laterally beyond edges of the metal bump
and wherein a top surface of a lower portion of the photo-sensitive structure is overlapped by an edge part of the solder region
Hsieh (see, e.g., fig. 11, para.0134-0139), in a similar method to Yang, shows a configuration of an NSMD interconnect
wherein the solder region 326 extends laterally beyond an edge of the metal bump 274
and wherein a top surface of a lower portion 324 of the photo-sensitive 320 structure is overlapped by an edge part of the solder region 326
Hsieh (see, e.g., para.0147) states the configuration of a NSMD interconnect would reduce the stress of the interconnection structure on which a solder is bonded to a metal pad.
It would be obvious have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Hsieh in the method of Yang, in view of Yu, to reduce the stress of the interconnection structure on which a solder is bonded to a metal pad.
Yang, in view of Yu and further in view of Hsieh (see, e.g., fig. 3i, para.0057), also shows
and plating and reflowing a solder region 180.
Regarding Claim 22, Yang (see, e.g., para.0092), in view of Yu and further in view of Hsieh, shows the method of claim 21,
wherein the photo-sensitive structure 40 comprises a photo-sensitive material selected from the group consisting of polyimide, polybenzoxazole (PBO), and benzocyclobutene (BCB) (see, e.g., para.0092).
Regarding Claim 23, Yang (see, e.g., para.0085, para.0092), in view of Yu and further in view of Hsieh, shows the method of claim 22,
wherein both of the dielectric layer 32 and the photo-sensitive structure 40 comprise photo-sensitive materials (polyimide, see, e.g., para.0085, para.0092).
Regarding Claim 24, Yang (see, e.g., fig. 9o, para.0085, para.0092), in view of Yu and further in view of Hsieh, shows the method of claim 23,
wherein the dielectric layer 32 and the photo-sensitive structure 40 are formed of a same photo-sensitive material (see, e.g., para.0085, para.0092),
and are in contact with each other to form a distinguishable interface in between (see, e.g., fig. 9o).
Claims 27, 28, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Hsieh (US 20150041985) and further in view of Hando (US 20150366058).
Regarding Claim 27, Yang, (see, e.g., figs. 9a-9t) shows a method comprising:
forming a device die (see, e.g., fig. 9s) comprising:
forming a first photo-sensitive structure 32 (see, e.g., fig. 9h, para.0085);
forming a first metal bump 36 (underneath the left solder 54 of 46 shown in fig. 9t, hereinafter ” 36a”, see, e.g., para.0088) and a second metal bump 36 (underneath the right solder 54 of 46 shown in fig. 9t, hereinafter ” 36a”, see, e.g., para.0088) neighboring each other and extending higher than the first photo-sensitive structure (both above the top surface of 32, see, e.g., fig. 9s);
and forming a second photo-sensitive structure 40 (see, e.g., fig. 9o, para.0092) over and directly and physically contacting the first photo-sensitive structure 66 (between all elements of 36);
a first solder layer 54 (underneath the left bump 50 of 46 shown in fig. 9t, hereinafter ” 54a”, see, e.g., para.0088) and a second solder layer (underneath the right bump 50 of 46 shown in fig. 9t, hereinafter ” 54b”, see, e.g., para.0088) extending into a first recess 40a (above 36a, hereinafter “40a.1”, see, e.g., fig. 9p) and a second recess (above 36b, hereinafter “40a.2”), respectively, of the second photo-sensitive structure (see, e.g., fig. 9p),
wherein a portion of the second photo-sensitive structure 40 separates the first solder layer from the second solder layer (between 36a & 36b),
and wherein the first metal bump and the second metal bump are underlying a first upper portion of the first solder layer and a second upper portion of the second solder layer, respectively (see, e.g., fig. 9t);
and joining a package component 46 (see, e.g., fig. 9t, para.0097) to the device die comprising:
bonding a first conductive feature 50 (above 36a, hereinafter “50a”, see, e.g., para.0098) to the first metal bump through the first solder layer 54a ;
and bonding a second conductive feature 50 (above 36b, hereinafter “50b”, see, e.g., para.0098) to the second metal bump through the second solder layer 54b.
Yang, however, fails to show
plating the first solder layer and the second solder layer
Hsieh (see, e.g., fig. 3i, para.0057), in a similar method to Yang, teaches plating solder layers would an effective and efficient process for forming the solder layers.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the plating of Hsieh in the method of Yang to effective and efficient process for forming the first solder layer and second solder layer of Yang.
Yang, in view of Hsieh, however, fails to show
with the portion of the second photo-sensitive structure comprising a top surface that is higher than a top surface of the first solder layer,
Hando (see, e.g., figs. 1-2, para.0059-0060), in a similar method to Yang, in view of Hsieh, shows a configuration wherein
with the portion of the second structure 57 comprising a top surface (top surface of 57) that is higher than a top surface of the first solder layer (a top surface of the solder 80 is defined as the top surface of 80 directly below pillar 81 since the limitation does not require “topmost”),
Hando states the configuration of extending the column 81 further into the structure surrounding the metal bump would improve the bonding connection of the solder and the metal bump.
The configuration of Hando is incorporated into the method of Yang, in view of Hsieh.
Yang in view of Hsieh and further in view of Hando, shows
with the portion of the second photo-sensitive structure 40 comprising a top surface that is higher than a top surface (defined as the top surface of 36a directly beneath 50a that now protrudes into the first recess as shown in fig. 2 of Hando) of the first solder layer 54a ,
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Hando in the method of Yang, in view of Hsieh, to improve the bonding connection of the solder and the metal bump.
Regarding Claim 28, Yang, in view of Hsieh and further in view of Hando, shows the method of claim 27,
wherein the first solder layer is wider than the first metal bump
and wherein in a cross-sectional view of the device die, a bottommost point of the first solder layer is in contact with the first metal bump (see, e.g., fig. 9t).
Hsieh (see, e.g., fig. 11, para.0134-0139) shows a NSMD interconnect that shows
wherein the first solder layer 326 is wider than the first metal bump 274
and wherein in a cross-sectional, a bottommost point of the first solder layer is in contact with the first metal bump (see, e.g., fig. 11).
Hsieh (see, e.g., para.0147) states the configuration of a NSMD interconnect would reduce the stress of the interconnection structure on which a solder is bonded to a metal pad.
Hsieh states the thickness T4 of the portion of the recess extending laterally beyond the edge 324 can be the same thickness and therefore at the same height as the metal bump 274. Therefore the bottommost point of the first solder layer is in contact with the first metal point.
The configuration of fig. 11 of Hsieh for the method of Yang, in view of Hsieh and further in view of Hando, renders the claim obvious.
Regarding Claim 29, Yang, in view of Hsieh and further in view of Hando, shows the method of claim 27,
wherein after the joining, the second photo-sensitive structure comprises a lower portion directly underlying the first upper portion of the first solder layer ,
and wherein the lower portion has a top surface level with the first metal bump.
Hsieh (see, e.g., fig. 11, para.0134-0139) shows a NSMD interconnect that shows
wherein after the joining, the second photo-sensitive structure 320 comprises a lower portion 324 directly underlying the first upper portion of the first solder layer 326,
and wherein the lower portion has a top surface level with the first metal bump (level because of the thickness T4).
Hsieh (see, e.g., para.0147) states the configuration of a NSMD interconnect would reduce the stress of the interconnection structure on which a solder is bonded to a metal pad.
Hsieh states the thickness T4 of the portion of the recess extending laterally beyond the edge 324 can be the same thickness and therefore at the same height as the metal bump 274. Therefore lower portion has a top surface level with the first metal bump.
The configuration of fig. 11 of Hsieh for the method of Yang, in view of Hsieh and further in view of Hando, renders the claim obvious.
Claim 30 rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Hsieh (US 20150041985) & Hando (US 20150366058) and further in view of Kim (20190198354).
Regarding Claim 30, Yang, in view of Hsieh & Hando, shows the method of claim 27,
Yang, in view of Hsieh & Hando, however, fails to show
wherein the first photo-sensitive structure and the second photo-sensitive structure are formed of a same formation process
Kim (see, e.g., figs. 2a-b, para.0040-0041), in a similar method to Yang, in view of Hsieh & Hando, shows a configuration for spin-coating as a method for depositing a photo-sensitive structure on a plurality of metal bumps would provide excellent adherence and conformity to the space between the metal bumps during the initial deposition.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Kim in the method of Yang, in view of Hsieh & Hando, to provide excellent adherence and conformity between metal bumps w0hen forming the photo-sensitive layer.
Allowable Subject Matter
Claim 34 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, see page 6, filed 01/08/2026, with respect to the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ) rejection of Claim 21 have been fully considered and are persuasive. The 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ) rejection of Claim 21 has been withdrawn.
Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
