DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed July 8, 2025 has been entered. Claims 1-12 remain pending in the application. Applicant’s amendments to the claims have overcome each and every objection and 35 U.S.C. § 112 rejection previously set forth in the Non-Final Office Action mailed April 9, 2025.
Response to Arguments
Applicant’s arguments, see Pages 9-13, filed July 8, 2025, with respect to the rejections of claims 1-2 under 35 U.S.C. § 102 and § 103 have been fully considered and are persuasive. Specifically, that prior art reference Cai et al. (Patent Publication Number CN 112,187,192 A), as cited by applicant, hereafter referred to as Cai, fails to disclose a DC blocking capacitor coupled to the detection component. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously presented prior art reference Su et al. (Patent Publication Number US 2020/0067463 A1), hereafter referred to as Su. Examiner notes that applicant has amended the claims, and therefore this office action is made final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Su.
Regarding claim 1, Cai discloses:
A compensation circuit module (Cai, Fig. 3), comprising a variable resistor (Fig. 3, M2), a detection component (Fig. 3, R1 and C2) and a control component (Fig. 3, M1 and R2); wherein the detection component comprises at least one of a detector, a galvanometer, or a power meter (Page 5, Paragraph 7 [see English translation of Cai provided with previous Office Action for corresponding page and paragraph numbers]), and has a detection end (Fig. 3, see connection between R1 and C2), and is configured to detect a voltage swing of an input signal (Page 5, Paragraph 7); the control component is connected with the detection component (Fig. 3, see connection between M1, R1, and C2), and is configured to output a control signal according to the input signal detected by the detection component (Fig. 3, see drain of M1 which outputs signal to gate of M2); and the variable resistor is connected with an output end of the control component (Fig. 3, see connection between drain of M1 and gate of M2) and is configured to change a resistance connected to the power amplifier according to the control signal (Page 5, Paragraph 9 – Page 6, Paragraph 1), the resistance of the variable resistor connected to the power amplifier is configured to constitute a feedback resistance of the power amplifier (Page 5, Paragraph 9 – Page 6, Paragraph 1, line 1), wherein the feedback resistance is configured to increase when gain of the power amplifier decreases (Page 6, Paragraph 1, lines 3-8) and the increased feedback resistance is configured to keep the gain in a straight section of a gain change curve (Page 6, Paragraph 1, lines 7-8), but fails to disclose [the detection component] which is connected with a DC blocking capacitor of a power amplifier [and is configured to detect a voltage swing of an input signal] of the DC blocking capacitor.
However, Su teaches [the detection component] which is connected with a DC blocking capacitor of a power amplifier (Su, Fig. 2, see connection between Cf1 [similar to detection component capacitor of Cai] and Cblock1) [and is configured to detect a voltage swing of an input signal] of the DC blocking capacitor (Fig. 2, see Cblock1 between RFin and Cf1).
Cai and Su are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cai to incorporate the teachings of Su to incorporate the DC blocking capacitor of Su in the circuit of Cai, which would have the effect of blocking undesired DC signals to allow for appropriate biasing conditions for the power amplifier of Cai.
Regarding claim 2, Cai further discloses:
further comprising an isolation resistor (Cai, Fig. 3, RG), wherein the isolation resistor is connected with the output end of the control component (Fig. 3, see connection between RG and drain of M1), is connected with an input end of the variable resistor (Fig. 3, see connection between RG and gate of M2), and is configured to change the resistance of the variable resistor connected to the power amplifier according to the control signal (Fig. 3, see that signal from M1 passes through RG to reach M2) and a resistance of the isolation resistor (Fig. 3, see that resistance value of RG necessarily adjusts the signal flowing through it).
Regarding claim 3, Cai further discloses:
wherein the control component at least comprises a first sub-control component (Fig. 3, M1) and a second sub-control component (Fig. 3, R2); the first sub-control component is connected with the detection component (Fig. 3, see connection between M1, R1, and C2) and is configured to output a first control current proportional to the input signal according to the input signal of the DC blocking capacitor (Fig. 3, consider drain current of M1) and the second sub-control component is connected with a back end of the first sub-control component (Fig. 3, see connection between R2 and M1) and is configured to output a current control voltage inversely proportional to the first control current according to the first control current (Fig. 3, consider voltage at node A, determined by VA = VDD – R2*Id, and that Id is proportional to the first control current).
Regarding claim 4, Cai further discloses:
wherein a detector comprises the detection component and the first sub-control component (Cai, Fig. 3, R1, C2, and M1); the detection component of the detector is configured to detect the voltage swing of the input signal passing through the DC blocking capacitor (Page 5, Paragraph 7); and the detector is connected with a first control power supply to constitute the first sub-control component (Fig. 3, see connection between R1 and VB), and the first control power supply is configured to generate a first control voltage (Fig. 3, consider voltage at gate of M1); the detector is further configured to determine a power threshold according to the first control voltage (Fig. 3, consider threshold that activates transistor M1); according to the power threshold, the voltage swing that meets a preset condition is determined (Page 6, Paragraph 1, lines 2-4); according to the voltage swing that meets the preset condition, the first control current is output (Page 6, Paragraph 1, lines 2-5).
Regarding claim 6, Cai further discloses:
A power amplification assembly (Cai, Fig. 3), comprising a power amplifier (Fig. 3, PA) and a compensation circuit module according to claim 1 (see above), a feedback circuit (Fig. 3, Rf1 and C1), a feedback resistor of the feedback circuit (Fig. 3, Rf1) at least comprises a fixed resistor (Fig. 2, R3, Note: see optional resistor R3 in Fig. 2, not shown in Fig. 3) and the variable resistor (Fig. 3, M2) connected to the feedback circuit (Fig. 3, see Rf1 in feedback circuit across PA), the fixed resistor and the variable resistor are configured to constitute a feedback resistance of the power amplifier (Page 6, Paragraph 4); the feedback resistance is configured to increase when the gain of the power amplifier decreases (Page 6, Paragraph 1, lines 3-8) and the increased feedback resistance is configured to keep the gain in the straight section of the gain change curve (Page 6, Paragraph 1, lines 7-8), but fails to disclose wherein the power amplifier comprises a DC blocking capacitor arranged at a signal input end, a transistor, a bias circuit, a feedback circuit and a DC blocking capacitor arranged at a signal output end; and a first end of the feedback circuit is connected with the DC blocking capacitor at the signal input end, the bias circuit and a gate of the transistor; a second end of the feedback circuit is connected with the DC blocking capacitor at the signal output end and a drain of the transistor.
However, Su teaches wherein the power amplifier comprises a DC blocking capacitor arranged at a signal input end (Su, Fig. 2, Cblock1), a transistor (Fig. 2, M2), a bias circuit (Fig. 2, see components labeled “Bias circuit”), and a DC blocking capacitor arranged at a signal output end (Fig. 2, cblock2); and a first end of the feedback circuit is connected with the DC blocking capacitor at the signal input end (Fig. 2, see connection between cf1 and cblock1), the bias circuit (Fig. 2, see connection between cf1 and R1) and a gate of the transistor (Fig. 2, see connection between cf1 and gate of M2); a second end of the feedback circuit is connected with the DC blocking capacitor at the signal output end (Fig. 2, see connection between cf2 and cblock2) and a drain of the transistor (Fig. 2, see connection between cf2 and drain of M2).
Cai and Su are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cai to incorporate the teachings of Su to incorporate DC blocking capacitors, a bias circuit, and a transistor amplifier into the circuit of Cai, which would have the effect of blocking undesired DC signals to allow for appropriate biasing conditions for the power amplifier of Cai.
Regarding claim 7, Cai further discloses:
A compensation method (Cai, Fig. 3), utilizing the compensation circuit module according to claim 1 to compensate the gain of the power amplifier (see above), the compensation method comprising: detecting the input signal of the DC blocking capacitor by the detection component (Fig. 3, see connection between R1 and C2); and outputting the control signal by the control component according to the input signal of the DC blocking capacitor (Fig. 3, see signal at node A after passing through transistor M1), wherein, the control signal is configured to change the resistance connected to the power amplifier (Page 6, Paragraph 1, lines 3-6), the resistance of the variable resistor connected to the power amplifier and a fixed resistor constitute the feedback resistance (Page 6, Paragraph 1, lines 3-6, see also Page 6, Paragraph 4), wherein the feedback resistance is configured to increase when the gain of the power amplifier decreases (Page 6, Paragraph 1, lines 3-8), the increased feedback resistance is configured to keep the gain in the straight section of the gain change curve (Page 6, Paragraph 1, lines 7-8).
Regarding claim 8, Cai further discloses:
further comprising: outputting a first control current proportional to the input signal by a first sub-control component according to the input signal of the DC blocking capacitor (Fig. 3, consider drain current of M1); and outputting a current control voltage inversely proportional to the first control current by a second sub-control component according to the first control current (Fig. 3, consider voltage at node A, determined by VA = VDD – R2*Id, and that Id is proportional to the first control current).
Regarding claim 9, Cai further discloses:
further comprising: detecting and outputting a first control current by a detector (Fig. 3, consider drain current of M1), wherein the first control current is determined according to the voltage swing of the input signal of the DC blocking capacitor (Fig. 3, consider how gate signal of M1 affects drain current of M1); determining a power threshold according to a first control voltage (M3, consider threshold that activates transistor M1 based on signal at VB), and determining a power of the input signal according to the voltage swing of the input signal (Page 6, Paragraph 1, lines 3-4); outputting the first control current when a preset condition that the power of the input signal is greater than the power threshold is met (Page 6, Paragraph 1, lines 2-4), wherein the first control current is proportional to the power of the input signal (Page 6, Paragraph 1, lines 2-5).
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Su as applied to claims 3 and 7 above, respectively, and further in view of Fan et al. (Patent Number US 207,505,174 U), hereafter referred to as Fan, and Tsuda (Patent Publication Number JP 2004/274390 A), hereafter referred to as Tsuda.
Regarding claim 5, Cai fails to disclose:
wherein the second sub-control component at least comprises a voltage source, a voltage-controlled resistor, a second control power supply and a current mirror; wherein the current mirror is connected with the voltage-controlled resistor, and is configured to receive the first control current and mirror the first control current to the voltage-controlled resistor; the voltage-controlled resistor is connected with the second control power supply, and the second control power supply outputs a second control voltage, wherein the second control voltage is configured to control a resistance of the voltage-controlled resistor; and an output end of a current control voltage is arranged between the voltage-controlled resistor and the current mirror, and is configured to output the current control voltage, wherein a voltage value of the current control voltage is equal to a voltage value of the voltage source minus a product of the voltage-controlled resistor and the first control current.
However, Fan teaches wherein the second sub-control component at least comprises a voltage source (Fan, Fig. 7, VREF), a voltage-controlled resistor (Fig. 7, R2), and a current mirror (Fig. 7, see current mirrors formed from M5, M6, M9, and M10); wherein the current mirror is connected with the voltage-controlled resistor (Fig. 7, see connection between M10 and R2), and is configured to receive the first control current (Fig. 7, see current at drain of M5) and mirror the first control current to the voltage-controlled resistor (Fig. 7, see path from drain of M5 to R2); and an output end of a current control voltage (Fig. 7, VREF’) is arranged between the voltage-controlled resistor and the current mirror (Fig. 7, see VREF’ located between R2 and M10), and is configured to output the current control voltage (Fig. 7, see VREF’), wherein a voltage value of the current control voltage is equal to a voltage value of the voltage source minus a product of the voltage-controlled resistor and the first control current (Page 8, Paragraph 2, lines 16-17), but fails to teach a second control power supply, the voltage-controlled resistor is connected with the second control power supply, and the second control power supply outputs a second control voltage, wherein the second control voltage is configured to control a resistance of the voltage-controlled resistor.
However, Tsuda teaches a second control power supply (Tsuda, Fig. 2, see control voltage coupled to 21 and 25) the voltage-controlled resistor is connected with the second control power supply (see connection between control voltage and 25, see also Paragraph 45), and the second control power supply outputs a second control voltage (Paragraph 45, lines 1-2), wherein the second control voltage is configured to control a resistance of the voltage-controlled resistor (Paragraph 45, line 2).
Cai, Su, Fan, and Tsuda are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cai to incorporate the teachings of Fan to modify the second-sub control component of Cai to include the circuit of Fan, which would have the effect of increasing the precision of the control current measurement and to modify the resistor located between the power supply and the current mirror of Fan to be a voltage-controlled resistor based on a control signal, which would have the effect of allowing for fine-tuning of circuit parameters to increase performance (Tsuda, Paragraph 45).
Regarding claim 10, Cai fails to disclose:
further comprising: receiving a first control current and mirroring the first control current to a voltage-controlled resistor by a current mirror; outputting a second control voltage by a second control power supply, wherein the second control voltage is configured to control the resistance of the voltage-controlled resistor; and outputting the current control voltage by an output end of the current control voltage arranged between the voltage-controlled resistor and the current mirror, wherein the voltage value of the current control voltage is equal to the voltage value of a voltage source minus the product of the voltage-controlled resistor and the first control current.
However, Fan teaches further comprising: receiving a first control current and mirroring the first control current to a voltage-controlled resistor by a current mirror (Fan, Fig. 7, see signal to flow from drain of M5 to R2); and outputting the current control voltage (Fig. 7, see VREF’) by an output end of the current control voltage arranged between the voltage-controlled resistor and the current mirror (Fig. 7, see location of VREF’), wherein the voltage value of the current control voltage is equal to the voltage value of a voltage source minus the product of the voltage-controlled resistor and the first control current (Page 8, Paragraph 2, lines 16-17), but fails to teach outputting a second control voltage by a second control power supply, wherein the second control voltage is configured to control the resistance of the voltage-controlled resistor.
However, Tsuda teaches outputting a second control voltage by a second control power supply (Tsuda, Fig. 2, see control voltage coupled to 21 and 25), wherein the second control voltage is configured to control the resistance of the voltage-controlled resistor (Paragraph 45, line 2).
Cai, Su, Fan, and Tsuda are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cai to incorporate the teachings of Fan to modify the second-sub control component of Cai to include the circuit of Fan, which would have the effect of increasing the precision of the control current measurement and to modify the resistor located between the power supply and the current mirror of Fan to be a voltage-controlled resistor based on a control signal, which would have the effect of allowing for fine-tuning of circuit parameters to increase performance (Tsuda, Paragraph 45).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Su as applied to claim 7 above, and further in view of Wei et al. (Patent Publication Number US 2014/0218123 A1), hereafter referred to as Wei.
Regarding claim 11, Cai further discloses:
A device (Cai, Fig. 3), configured to implement operations of the compensation method according to claim 7 (see above), but fails to disclose comprising a memory and a processor [configured to implement compensation] by executing instructions stored in the memory.
However, Wei teaches comprising a memory (Wei, Fig. 7, 706) and a processor (Fig. 7, 704) [configured to implement compensation] by executing instructions stored in the memory (Paragraph 46, lines 4-7).
Cai, Su, and Wei are all considered to be analogous to the claimed invention because they are both in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cai to incorporate the teachings of Wei to include a memory and processor to implement the compensation method of Cai, which would have the effect of providing a known method for implementing the compensation method of Cai.
Regarding claim 12, Cai further discloses:
wherein the resistance of the variable resistor constitutes the feedback resistance of the power amplifier (Cai, Page 5, Paragraph 9-Page 6, Paragraph 1, line 1), and the gain of the power amplifier is compensated by adjusting the resistance of the variable resistor (Page 6, Paragraph 1, lines 1-7), to thereby stabilize the gain (Page 6, Paragraph 1, lines 6-7) and maintain linearity of transistor voltage input signal output characteristics of the power amplifier in a case of a large-amplitude signal input (Page 6, Paragraph 1, lines 3-8), while preventing nonlinear distortion of the power amplifier (Page 6, Paragraph 1, lines 6-8).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Darwish (Patent Publication Number US 2019/0280654 A1) discloses (Fig. 2) a gain controlling feedback loop for a power amplifier. Wu et al. (Patent Publication Number US 2015/0381123 A1) discloses (Fig. 3) a variable resistance transistor in a feedback loop of a power amplifier. Kawamura et al. (Patent Number JP 3,854,832 B2) discloses (Fig. 1) a variable resistance transistor to compensate the gain of a power amplifier. Kim et al. (Patent Number US 6,057,736 A) discloses (Fig. 2) a variable resistance feedback loop to compensate the gain of a power amplifier.
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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