METHOD AND APPARATUS FOR CODE BLOCK DIVISION

Application No. 17/929,299

• Filed: Sep 01, 2022
• Priority: Apr 15, 2015 — CN 201510179118.X
  • Apr 06, 2016 — nonprovisional of PCTCN2016078586
  • Oct 16, 2017 — continuation of 10/708,099
  • Jul 06, 2020 — continuation of 11/477,065
• Examiner: KANG, SUK JIN
• Art Unit: 2477
• Tech Center: 2400 — Computer Networks
• Assignee: ZTE Corporation
• OA Round: 5 (Non-Final)

Office Action

DETAILED ACTION
Applicant’s amendment and arguments filed May 22, 2026 is acknowledged.
Claims 1-15 are currently pending.

Information Disclosure Statement
The information disclosure statement submitted on May 22, 2026 has been considered by the Examiner and made of record in the application.

Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, and 9 of U.S. Patent No. 11,477,065 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are equivalent in scope and embodiment and are anticipated by the claims of the patent.
Instant Application (17/929,299)
U.S. Patent No. 10,708,099 B2
Claim 1
Claim 1
A method for code block division, comprising: dividing a Transfer Block (TB) having a length greater than a maximum information block length into two or more code blocks, wherein the maximum information block length is determined in accordance with a maximum number (Ncb) of Orthogonal Frequency Division Multiplexing (OFDM) symbols allowed to be occupied by each code block in a time domain; generating check data blocks by performing block encoding on the two or more code blocks; obtaining encoded code blocks by performing, for each of the two or more code block, the following operations: adding redundancy check (CRC) bits, performing channel encoding, and performing rate matching; deleting a part of bits at any position of each encoded code block and a part of bits at any position of each check data block; performing code block cascading on the encoded code blocks from which the part of bits are deleted, and on the check data blocks from which the part of bits are deleted, wherein the code block cascading is performed by: connecting in series bits of the encoded code blocks from which the part of bits has been deleted and bits of the check data blocks from which the part of bits has been deleted; and putting the check data blocks from which the part of bits has been deleted behind the encoded code blocks from which the part of bits has been deleted.
A method of code block division, comprising: determining a maximum information block length of a code block according to a plurality of division related parameters associated with a Transport Block (TB), wherein the plurality of division related parameters includes physical channel resource parameters that describe a number of symbols and a number of subcarriers associated with the TB, and a plurality of spectral efficiency parameters that describe encoding parameters for the TB, wherein the plurality of spectral efficiency parameters include a modulation scheme (M) of a transmission signal that includes the TB, a coding rate (R) of the TB, and a number (Nlayer) of spatial layers occupied by the transmission signal; and dividing the TB having a size greater than the maximum information block length into two or more code blocks, wherein a number of the two or more code blocks is determined according to the maximum information block length, the size of the TB, and a length of cyclic redundancy check (CRC) bits of each code block, wherein an information length of each of the two or more code blocks after the dividing the TB is determined according to a set of information block lengths supported by an encoder, the number of the two or more code blocks, the size of the TB and the length of the CRC bits of each code block.
Claim 2 is anticipated by claim 1 of the patent.
Claim 3 is anticipated by claim 1 of the patent.
Claim 4 is anticipated by claim 1 of the patent.
Claim 5 is anticipated by claim 2 of the patent.
Claim 6
Claim 5
A wireless communication apparatus, comprising: a processor configured to: divide a Transfer Block (TB) having a length greater than a maximum information block length into two or more code blocks, wherein the maximum information block length is determined in accordance with a maximum number (Ncb) of Orthogonal Frequency Division Multiplexing (OFDM) symbols allowed to be occupied by each code block in a time domain; generate check data blocks by performing block encoding on the two or more code blocks; obtain encoded code blocks by performing, for each of the two or more code block, the following operations: add redundancy check (CRC) bits, perform channel encoding, and perform rate matching; delete a part of bits at any position of each encoded code block and a part of bits at any position of each check data block; perform code block cascading on the encoded code blocks from which the part of bits are deleted, and on the check data blocks from which the part of bits are deleted, wherein the code block cascading is performed by the processor configured to: connect in series bits of the encoded code blocks from which the part of bits has been deleted and bits of the check data blocks from which the part of bits has been deleted; and put the check data blocks from which the part of bits has been deleted behind the encoded code blocks from which the part of bits has been deleted.
A wireless communication apparatus, comprising a processor configured to: determine a maximum information block length of a code block according to a plurality of division related parameters associated with a Transport Block (TB), wherein the plurality of division related parameters includes physical channel resource parameters that describe a number of symbols and a number of subcarriers associated with the TB, and a plurality of spectral efficiency parameters that describe encoding parameters for the TB, wherein the plurality of spectral efficiency parameters include a modulation scheme (M) of a transmission signal that includes the TB, a coding rate (R) of the TB, and a number (Nlayer) of spatial layers occupied by the transmission signal; and divide the TB having a size greater than the maximum information block length into two or more code blocks, wherein a number of the two or more code blocks is determined according to the maximum information block length, the size of the TB, and a length of cyclic redundancy check (CRC) bits of each code block, wherein an information length of each of the two or more code blocks after the TB is divided is determined according to a set of information block lengths supported by an encoder, the number of the two or more code blocks, the size of the TB and the length of the CRC bits of each code block.
Claim 7 is anticipated by claim 5 of the patent.
Claim 8 is anticipated by claim 5 of the patent.
Claim 9 is anticipated by claim 5 of the patent.
Claim 10 is anticipated by claim 2 of the patent.
Claim 11
Claim 9
A non-transitory computer readable storage media comprising instructions for code block division, wherein the instructions configure a processor to perform a method comprising: dividing a Transfer Block (TB) having a length greater than a maximum information block length into two or more code blocks, wherein the maximum information block length is determined in accordance with a maximum number (Ncb) of Orthogonal Frequency Division Multiplexing (OFDM) symbols allowed to be occupied by each code block in a time domain; generating check data blocks by performing block encoding on the two or more code blocks; obtaining encoded code blocks by performing, for each of the two or more code block, the following operations: adding redundancy check (CRC) bits, performing channel encoding, and performing rate matching; deleting a part of bits at any position of each encoded code block and a part of bits at any position of each check data block; performing code block cascading on the encoded code blocks from which the part of bits are deleted, and on the check data blocks from which the part of bits are deleted, wherein the code block cascading is performed by: connecting in series bits of the encoded code blocks from which the part of bits has been deleted and bits of the check data blocks from which the part of bits has been deleted; and putting the check data blocks from which the part of bits has been deleted behind the encoded code blocks from which the part of bits has been deleted.
A non-transitory computer readable storage media comprising instructions for code block division, wherein the instructions configure a processor to perform a method comprising: determining a maximum information block length of a code block according to a plurality of division related parameters associated with a Transport Block (TB), wherein the plurality of division related parameters includes physical channel resource parameters that describe a number of symbols and a number of subcarriers associated with the TB, and a plurality of spectral efficiency parameters that describe encoding parameters for the TB, wherein the plurality of spectral efficiency parameters include a modulation scheme (M) of a transmission signal that includes the TB, a coding rate (R) of the TB, and a number (Nlayer) of spatial layers occupied by the transmission signal; and dividing the TB having a size greater than the maximum information block length into two or more code blocks, wherein a number of the two or more code blocks is determined according to the maximum information block length, the size of the TB, and a length of cyclic redundancy check (CRC) bits of each code block, wherein an information length of each of the two or more code blocks after the dividing the TB is determined according to a set of information block lengths supported by an encoder, the number of the two or more code blocks, the size of the TB and the length of the CRC bits of each code block.
Claim 12 is anticipated by claim 9 of the patent.
Claim 13 is anticipated by claim 9 of the patent.
Claim 14 is anticipated by claim 9 of the patent.
Claim 15 is anticipated by claim 2 of the patent.

Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 6, and 11 of U.S. Patent No. 10,708,099 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are equivalent in scope and embodiment and are anticipated by the claims of the patent.
Instant Application (17/929,299)
U.S. Patent No. 10,708,099 B2
Claim 1
Claim 1
A method for code block division, comprising: dividing a Transfer Block (TB) having a length greater than a maximum information block length into two or more code blocks; generating check data blocks by performing block encoding on the two or more code blocks; obtaining encoded code blocks by performing, for each of the two or more code block, the following operations: adding redundancy check (CRC) bits, performing channel encoding, and performing rate matching; deleting a part of bits at any position of each encoded code block and a part of bits at any position of each check data block; performing code block cascading on the encoded code blocks from which the part of bits are deleted, and on the check data blocks from which the part of bits are deleted, wherein the code block cascading is performed by: connecting in series bits of the encoded code blocks from which the part of bits has been deleted and bits of the check data blocks from which the part of bits has been deleted; and putting the check data blocks from which the part of bits has been deleted behind the encoded code blocks from which the part of bits has been deleted.
A method for code block division, comprising: determining a maximum information block length according to a division related parameter; and dividing a Transport Block (TB) having a length greater than the maximum information block length into two or more code blocks; wherein an information length after code block division is less than the determined maximum information block length; wherein the determining the maximum information block length according to the division related parameter comprises: determining a reference information block length of a code block according to the division related parameter; and determining the maximum information block length according to the reference information block length and a hardware parameter; wherein dividing the TB having a length greater than the maximum information block length into two or more code blocks comprises dividing the TB having a length greater than the maximum information block length into two or more code blocks according to the division related parameter and the determined maximum information block length; wherein when the division related parameter comprises at least one of a physical channel resource parameter or a spectral efficiency parameter, the spectral efficiency parameter comprises any one or more of the following parameters: a modulation scheme (M) of a transmission signal, a coding rate (R) of a TB, and a number (Nlayer) of spatial layers occupied by the transmission signal, and the physical channel resource parameter comprises a number (Ntb) of Orthogonal Frequency Division Multiplexing (OFDM) symbols occupied by the TB in a time domain and a number (Nsubcarrier) of frequency-domain subcarriers occupied by the transmission signal; and wherein the determining the reference information block length comprises: determining the reference information block length (KR) of the code block according to the physical channel resource parameter and the spectral efficiency parameter.
Claim 2 is anticipated by claim 1 of the patent.
Claim 3 is anticipated by claim 1 of the patent.
Claim 4 is anticipated by claim 1 of the patent.
Claim 5 is anticipated by claim 4 of the patent.
Claim 6
Claim 6
A wireless communication apparatus, comprising: a processor configured to: divide a Transfer Block (TB) having a length greater than a maximum information block length into two or more code blocks; generate check data blocks by performing block encoding on the two or more code blocks; obtain encoded code blocks by performing, for each of the two or more code block, the following operations: add redundancy check (CRC) bits, perform channel encoding, and perform rate matching; delete a part of bits at any position of each encoded code block and a part of bits at any position of each check data block; perform code block cascading on the encoded code blocks from which the part of bits are deleted, and on the check data blocks from which the part of bits are deleted, wherein the code block cascading is performed by the processor configured to: connect in series bits of the encoded code blocks from which the part of bits has been deleted and bits of the check data blocks from which the part of bits has been deleted; and put the check data blocks from which the part of bits has been deleted behind the encoded code blocks from which the part of bits has been deleted.
An apparatus for code block division, comprising a hardware processor being configured to: determine a maximum information block length according to a division related parameter; and divide a Transport Block (TB) having a length greater than the maximum information block length into two or more code blocks; wherein an information length after code block division is less than the determined maximum information block length; wherein the maximum information block length according to the division related parameter is determined by: determining a reference information block length of a code block according to a division related parameter; and determining the maximum information block length according to the reference information block length and a hardware parameter; wherein the TB having a length greater than the maximum information block length is divided into two or more code blocks according to the division related parameter and the determined maximum information block length; and wherein when the division related parameter comprises at least one of a physical channel resource parameter or a spectral efficiency parameter, the spectral efficiency parameter comprises any one or more of the following parameters: a modulation scheme (M) of a transmission signal, a coding rate (R) of a TB, and a number (Nlayer) of spatial layers occupied by the transmission signal, and the physical channel resource parameter comprises a number (Ntb) of Orthogonal Frequency Division Multiplexing (OFDM) symbols occupied by the TB in a time domain and a number (Nsubcarrier) of frequency-domain subcarriers occupied by the transmission signal; and wherein the reference information block length (KR) of the code block is determined according to the physical channel resource parameter and the spectral efficiency parameter.
Claim 7 is anticipated by claim 6 of the patent.
Claim 8 is anticipated by claim 6 of the patent.
Claim 9 is anticipated by claim 6 of the patent.
Claim 10 is anticipated by claim 4 of the patent.
Claim 11
Claim 11
A non-transitory computer readable storage media comprising instructions for code block division, wherein the instructions configure a processor to perform a method comprising: dividing a Transfer Block (TB) having a length greater than a maximum information block length into two or more code blocks; generating check data blocks by performing block encoding on the two or more code blocks; obtaining encoded code blocks by performing, for each of the two or more code block, the following operations: adding redundancy check (CRC) bits, performing channel encoding, and performing rate matching; deleting a part of bits at any position of each encoded code block and a part of bits at any position of each check data block; performing code block cascading on the encoded code blocks from which the part of bits are deleted, and on the check data blocks from which the part of bits are deleted, wherein the code block cascading is performed by: connecting in series bits of the encoded code blocks from which the part of bits has been deleted and bits of the check data blocks from which the part of bits has been deleted; and putting the check data blocks from which the part of bits has been deleted behind the encoded code blocks from which the part of bits has been deleted.
A non-transitory computer readable storage media comprising instructions for code block division, wherein the instructions configure a processor to perform a method comprising: determining a maximum information block length according to a division related parameter; and dividing a Transport Block (TB) having a length greater than the maximum information block length into two or more code blocks; wherein an information length after code block division is less than the determined maximum information block length; wherein the maximum information block length according to the division related parameter is determined by: determining a reference information block length of a code block according to a division related parameter; and determining the maximum information block length according to the reference information block length and a hardware parameter; wherein the TB having a length greater than the maximum information block length is divided into two or more code blocks according to the division related parameter and the determined maximum information block length; and wherein when the division related parameter comprises at least one of a physical channel resource parameter or a spectral efficiency parameter, the spectral efficiency parameter comprises any one or more of the following parameters: a modulation scheme (M) of a transmission signal, a coding rate (R) of a TB, and a number (Nlayer) of spatial layers occupied by the transmission signal, and the physical channel resource parameter comprises a number (Ntb) of Orthogonal Frequency Division Multiplexing (OFDM) symbols occupied by the TB in a time domain and a number (Nsubcarrier) of frequency-domain subcarriers occupied by the transmission signal; and wherein the reference information block length (KR) of the code block is determined according to the physical channel resource parameter and the spectral efficiency parameter.
Claim 12 is anticipated by claim 11 of the patent.
Claim 13 is anticipated by claim 11 of the patent.
Claim 14 is anticipated by claim 11 of the patent.
Claim 15 is anticipated by claim 4 of the patent.

Response to Arguments
Applicant’s arguments, filed May 22, 2026, with respect to the rejection(s) of claim(s) 1-15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, arguments with respect to the rejection of claims 1-15 on the ground of non-statutory double patenting have been fully considered but they are not persuasive and therefore maintained.

Conclusion
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/Suk Jin Kang/
Examiner, Art Unit 2477
August 3, 2026

Prosecution Timeline

• Sep 01, 2022: Application Filed
• Jan 15, 2025: Non-Final Rejection mailed — §103
• Feb 06, 2025: Response Filed
• Mar 24, 2025: Final Rejection mailed — §103
• Apr 21, 2025: Response after Non-Final Action
• Jun 16, 2025: Request for Continued Examination
• Jun 20, 2025: Response after Non-Final Action
• Aug 12, 2025: Non-Final Rejection mailed — §103
• Nov 11, 2025: Response Filed
• Feb 24, 2026: Non-Final Rejection mailed — §103
• May 22, 2026: Response Filed
• Aug 05, 2026: Non-Final Rejection mailed — §103 (current)