DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 12/4/25, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goss (US 11016880) in view of WYSOCZANSKI (US 20190095107).
With respect to claim 1, the Goss reference teaches an apparatus, comprising:
a controller associated with a memory device, (e.g. fig. 1, network controller 106; and column 2, line 30-41, where one or more network controller 106 can be hardware or software based and provide data request processing and distribution to the various connected data storage devices 102) wherein the controller is configured to cause the apparatus to:
assign a memory block of a memory system as a special function block configured with a first portion for storing information associated with a first function associated with operating of the memory system and a second portion for storing information associated with a second function associated with operating the memory system; (column 4, line 56 to column 5, line 3, where there a correlation between the logical addresses of various blocks and the physical addresses at which the various blocks are stored (e.g., die set, die, plane, garbage collection unit (GCU), EB, page, bit offset, etc.) [i.e. a GCU and memory block are analogous]; and the reverse directory 174 contents may be written as part of the data writing process to each GCU, such as in the form of a header or footer along with the data being written. Generally, the reverse directory 174 provides an updated indication of how many of the data blocks (e.g., MUAs) are valid (e.g., represent the most current version of the associated data); and see fig. 7, step 242; and column 9, line 54 to column 10, line 4, where if data and/or a PBA [physical block address] is determined as hot in decision 240, step 242 assigns the incoming, or existing data, to a different GCU to satisfy a hot/cold ratio set by the disturb strategy)
write a first set of information to the first portion of the memory block based at least in part on assigning the memory block as the special function block, the first set of information associated with the first function of the memory system; (column 4, line 56 to column 5, line 3, the reverse directory 174 contents may be written as part of the data writing process to each GCU, such as in the form of a header or footer along with the data being written. Generally, the reverse directory 174 provides an updated indication of how many of the data blocks (e.g., MUAs) are valid (e.g., represent the most current version of the associated data) [where part of the GCU is used for data, and other for a header or footer to store metadata about the GCU] and
write a second set of information to the second portion of the memory block based at least in part on assigning the memory block as the special function block, the second set of information associated with the second function of the memory system. (column 4, line 56 to column 5, line 3, the reverse directory 174 contents may be written as part of the data writing process to each GCU, such as in the form of a header or footer along with the data being written. Generally, the reverse directory 174 provides an updated indication of how many of the data blocks (e.g., MUAs) are valid (e.g., represent the most current version of the associated data) [where part of the GCU is used for data, and other for a header or footer to store metadata about the GCU])
However, the Goss reference does not explicitly teach the special function block is for storage of functional data and not for storage of data received from a host system, the special function block. (emphasis added)
The WYSOCZANSKI reference teaches it is conventional to have the special function block be for storage of functional data and not for storage of data received from a host system, the special function block. (paragraph 68, where the corresponding data is written to its respectively determined block 808. For example, an SSD may assign each of the plurality of classes, e.g. user data, dynamic metadata, and static metadata, to different blocks (i.e. erase units) of the SSD; and paragraph 34, where metadata (either static or dynamic) is an internal state of the caching software configured for caching write requests, i.e. the I/O requests containing metadata write requests are never sent directly by the user/application, although in the case of dynamic metadata requests, may be a byproduct of a user I/O request.)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Goss reference to have the special function block be for storage of functional data and not for storage of data received from a host system, the special function block., as taught by the WYSOCZANSKI reference.
The suggestion/motivation for doing so would have been to have caching software that is configured to similarly tag internally generated metadata requests (either static or dynamic) and issue the appropriately tagged metadata requests to the SSD. (WYSOCZANSKI, paragraph 33)
Therefore it would have been obvious to combine the Goss and WYSOCZANSKI references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determine whether the first portion of the memory block is full of information based at least in part on writing the first set of information to the first portion of the memory block; and indicate that the memory block is ready for a memory management operation based at least in part on determining that the first portion of the memory block is full of information. (Goss, column 5, line 44 to 54, where GCUs that are approaching the time at which a garbage collection operation may be suitable, such as after the GCU has been filled with data and/or has reached a certain aging limit, etc., may be selected for evaluation on the basis that it can be expected that a garbage collection operation may be necessary in the relatively near future)
With respect to claim 3, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: perform the memory management operation on the memory block that transfers valid data stored in the memory block to a target block and erases the memory block based at least in part on indicating that the memory block is ready for the memory management operation. (Goss, column 5, line 64 to column 6, line 8, where a garbage collection operation can include accessing the forward map and/or reverse directory 172, 174 to identify the still valid data blocks, the reading out and temporary storage of such blocks in a local buffer memory, the writing of the blocks to a new location such as in a different GCU, the application of an erasure operation to erase each of the erasure blocks in the GCU, the updating of program/erase count metadata to indicate the most recent erasure cycle, and the placement of the reset GCU into an allocation pool awaiting subsequent allocation and use for the storage of new data sets)
With respect to claim 4, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 3, wherein performing the memory management operation is further configured to cause the apparatus to: transfer the valid data stored in the first portion of the memory block and the second portion of the memory block to the target block; and erase the first portion of the memory block and the second portion of the memory block based at least in part on transferring the valid data to the target block. (Goss, column 5, line 64 to column 6, line 8, where a garbage collection operation can include accessing the forward map and/or reverse directory 172, 174 to identify the still valid data blocks, the reading out and temporary storage of such blocks in a local buffer memory, the writing of the blocks to a new location such as in a different GCU, the application of an erasure operation to erase each of the erasure blocks in the GCU, the updating of program/erase count metadata to indicate the most recent erasure cycle, and the placement of the reset GCU into an allocation pool awaiting subsequent allocation and use for the storage of new data sets)
With respect to claim 5, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 4, wherein the controller is further configured to cause the apparatus to: increment an erase counter for the memory block based at least in part on erasing the memory block. (Goss, column 5, line 64 to column 6, line 8, where a garbage collection operation can include accessing the forward map and/or reverse directory 172, 174 to identify the still valid data blocks, the reading out and temporary storage of such blocks in a local buffer memory, the writing of the blocks to a new location such as in a different GCU, the application of an erasure operation to erase each of the erasure blocks in the GCU, the updating of program/erase count metadata to indicate the most recent erasure cycle, and the placement of the reset GCU into an allocation pool awaiting subsequent allocation and use for the storage of new data sets)
With respect to claim 6, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: perform a wear-leveling operation on a plurality of blocks of the memory system based at least in part on an erase count associated with each block of the plurality of blocks based at least in part on writing the first set of information or the second set of information. (Goss, column 5, line 64 to column 6, line 8, where a garbage collection operation can include accessing the forward map and/or reverse directory 172, 174 to identify the still valid data blocks, the reading out and temporary storage of such blocks in a local buffer memory, the writing of the blocks to a new location such as in a different GCU, the application of an erasure operation to erase each of the erasure blocks in the GCU, the updating of program/erase count metadata to indicate the most recent erasure cycle, and the placement of the reset GCU into an allocation pool awaiting subsequent allocation and use for the storage of new data sets [i.e. the erase count is taken into consideration for the placement of data])
With respect to claim 7, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the first function or the second function of the memory system that is associated with the special function block comprises storing data for power loss events, storing journaling data, storing error control information, storing small-chunk single-level cell data, storing data associated with replay-protected memory blocks, or any combination thereof. (Goss, column 5, lines 33-43, where mismatches can arise due to a variety of factors such as incomplete writes, unexpected power surges or disruptions that prevent a full writing of the state of the system, etc. Regardless, the control circuit can expend the resources as available to proactively update the metadata. In some embodiments, an exception list 180 may be formed as a data structure in memory of GCUs that have been found to require further evaluation. In this way, the GCUs can be evaluated later at an appropriate time for resolution, after which the corrected GCUs can be placed on the verified list in the table of verified GCUs (TOVG) 178)
With respect to claim 8, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the first portion of the memory block comprises a first quantity of planes of the memory block, and the second portion of the memory block comprises a second quantity of planes of the memory block. (Goss, column 6, lines 55-64, where a GCU is a logical construct that does not, necessarily, correlate with the physical location of data. That is, the LBA of a GCU can be in different planes, die, and pages of one or more data storage devices. However, the representation of the repository 192 in FIG. 5 corresponds with LBA assigned to GCUs in correlation with the physical location associated with the LBA. In yet, GCU can consist of physical data locations in multiple different planes, die, and pages, as conveyed by the increasing page/die count towards the bottom of the repository 192)
With respect to claim 9, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the first portion of the memory block comprises two planes of the memory block, and the second portion of the memory block comprises four planes of the memory block. (Goss, column 6, lines 55-64, where a GCU is a logical construct that does not, necessarily, correlate with the physical location of data. That is, the LBA of a GCU can be in different planes, die, and pages of one or more data storage devices. However, the representation of the repository 192 in FIG. 5 corresponds with LBA assigned to GCUs in correlation with the physical location associated with the LBA. In yet, GCU can consist of physical data locations in multiple different planes, die, and pages, as conveyed by the increasing page/die count towards the bottom of the repository 192 [i.e. a GCU and its portions can correspond to multiple planes])
With respect to claim 10, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the memory block comprises a virtual block. (Goss, column 4, line 56 to column 5, line 3, where there a correlation between the logical addresses of various blocks and the physical addresses at which the various blocks are stored (e.g., die set, die, plane, garbage collection unit (GCU), EB, page, bit offset, etc.))
With respect to claim 11, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein: the first portion of the memory block comprises two or more planes. (Goss, column 6, lines 55-64, where a GCU is a logical construct that does not, necessarily, correlate with the physical location of data. That is, the LBA of a GCU can be in different planes, die, and pages of one or more data storage devices. However, the representation of the repository 192 in FIG. 5 corresponds with LBA assigned to GCUs in correlation with the physical location associated with the LBA. In yet, GCU can consist of physical data locations in multiple different planes, die, and pages, as conveyed by the increasing page/die count towards the bottom of the repository 192 [i.e. a GCU can correspond to multiple planes])
With respect to claim 12, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 11, wherein: the second portion of the memory block comprises two or more planes. (Goss, column 6, lines 55-64, where a GCU is a logical construct that does not, necessarily, correlate with the physical location of data. That is, the LBA of a GCU can be in different planes, die, and pages of one or more data storage devices. However, the representation of the repository 192 in FIG. 5 corresponds with LBA assigned to GCUs in correlation with the physical location associated with the LBA. In yet, GCU can consist of physical data locations in multiple different planes, die, and pages, as conveyed by the increasing page/die count towards the bottom of the repository 192 [i.e. a GCU can correspond to multiple planes])
With respect to claim 13, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 1, wherein the memory block comprises six planes, the first portion comprises two planes of the six planes and the second portion comprises four planes of the six planes. (Goss, column 6, lines 55-64, where a GCU is a logical construct that does not, necessarily, correlate with the physical location of data. That is, the LBA of a GCU can be in different planes, die, and pages of one or more data storage devices. However, the representation of the repository 192 in FIG. 5 corresponds with LBA assigned to GCUs in correlation with the physical location associated with the LBA. In yet, GCU can consist of physical data locations in multiple different planes, die, and pages, as conveyed by the increasing page/die count towards the bottom of the repository 192 [i.e. a GCU can correspond to multiple planes])
With respect to claim 14, the combination of Goss and WYSOCZANSKI references teaches the apparatus of claim 13, wherein storing data for power loss events and storing data associated with replay-protected memory blocks utilize the first portion of the memory block, and storing journaling data, storing error control information, and storing small-chunk single-level cell data utilize the second portion of the memory block. (Goss, column 5, lines 33-43, where mismatches can arise due to a variety of factors such as incomplete writes, unexpected power surges or disruptions that prevent a full writing of the state of the system, etc. Regardless, the control circuit can expend the resources as available to proactively update the metadata. In some embodiments, an exception list 180 may be formed as a data structure in memory of GCUs that have been found to require further evaluation. In this way, the GCUs can be evaluated later at an appropriate time for resolution, after which the corrected GCUs can be placed on the verified list in the table of verified GCUs (TOVG) 178)
Claims 15-20 are the non-transitory computer-readable medium implementation of claims 1-14, and rejected under the same rationale as shown in the rejections above.
Claims 21-25 are the method implementation of claims 1-14, and rejected under the same rationale as shown in the rejections above.
3. ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS
Rejections - USC 112(a)/(b)
Applicant's arguments (see pages 8-9 of the remarks) and amendments with respect to claims have been considered, and are persuasive. Therefore, the rejection has been withdrawn.
4. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 103
Applicant's arguments (see pages 9-12 of the remarks) and amendments with respect to claims have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of WYSOCZANSKI reference as shown in the rejections above.
5. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137