DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 21 are objected to because of the following informalities: the term “the processor cache tiers” should be “processor cache tiers”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the terms: "a first tier of memory” and “a second tier of memory". However these terms already appear in claim 1, therefore it is unclear if these are referring to the same tiers as claim 1 or two new tiers in addition to the ones in claim 1. For purposes of examination, the examiner is considering them the same two tiers as described in claim 1.
Claims 18-20 are rejected by virtue of their dependence on a rejected base claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, 16-19, 21 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aguilera et al. (2023/0033029).
Consider claim 1, Aguilera et al. discloses an apparatus for managing memory of a computer system, the apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to: obtain first information on accesses to at least one of a first tier of memory and a second tier of memory within a memory hierarchy of the computer system from a page table, the first and second tiers of memory being below the processor cache tiers of the memory hierarchy, the first tier of memory having a higher memory performance than the second tier of memory; obtain second information on accesses to at least one of the first tier of memory and the second tier of memory from logged processor events related to the accesses to the first tier of memory and the second tier of memory; and select one or more memory pages to be moved between the first tier of memory and the second tier of memory based on the first and second information on the accesses to at least one of the first tier of memory and the second tier of memory (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses a multi-tiered system with two tiers of memory with different performance characteristics. Page tables and destination tables are disclosed which can include a present and dirty/change bit that is used in the migration decision process. Performance information is also logged such as access frequency that is used in the migration decision process. Data can be migrated in both directions.).
Consider claim 2, Aguilera et al. discloses the apparatus according to claim 1, wherein the first tier of memory is dynamic random-access memory-based memory ([0012]).
Consider claim 3, Aguilera et al. discloses the apparatus according to claim 1, wherein the second tier of memory is one or persistent memory, non-volatile memory express-based memory, and compute express link-based memory ([0012]).
Consider claim 7, Aguilera et al. discloses the apparatus according to claim 1, wherein the first information on the accesses is based on the respective access bits and dirty bits stored in the page table (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses page tables and destination tables are disclosed which can include a present and dirty/change bit that is used in the migration decision process.).
Consider claim 8, Aguilera et al. discloses the apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to move a memory page between the second tier of memory and the first tier of memory based on the selection (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses migrating memory pages between tiers.).
Consider claim 9, Aguilera et al. discloses the apparatus according to claim 8, wherein the machine-readable instructions comprise instructions to select the one or more memory pages to be moved between the first tier of memory and the second tier of memory based on at least one of an access frequency of the one or more memory pages, a memory access latency of accesses to the one or more memory pages and a processor cache hit or miss rate of accesses to the one or more memory pages (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses migrating memory pages between tiers based on access frequency.).
Consider claim 16, Aguilera et al. discloses the apparatus according to claim 1, wherein the first information and the second information on the accesses relate to accesses of a specific computer program being executed by the computer system (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049]).
Consider claim 17, Aguilera et al. discloses a computer system comprising a first tier of memory, a second tier of memory and the apparatus according to claim 1 (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], this claim is rejected in the same manner as claim 1.).
Consider claim 18, Aguilera et al. discloses a computer system comprising the computer system according to claim 17, wherein the first tier of memory is dynamic random access memory based memory ([0012]).
Consider claim 19, Aguilera et al. discloses a computer system comprising the computer system according to claim 17, wherein the second tier of memory is one or persistent memory, non-volatile memory express-based memory, and compute express link-based memory ([0012]).
Consider claim 21, Aguilera et al. discloses a method for managing memory of a computer system, the method comprising: obtaining first information on accesses to at least one of a first tier of memory and a second tier of memory within a memory hierarchy of the computer system from a page table, the first and second tiers of memory being below the processor cache tiers of the memory hierarchy, the first tier of memory having a higher memory performance than the second tier of memory; obtaining second information on accesses to at least one of the first tier of memory and the second tier of memory from logged processor events related to the accesses to the first tier of memory and the second tier of memory; and selecting one or more memory pages to be moved between the first tier of memory and the second tier of memory based on the first and second information on the accesses to at least one of the first tier of memory and the second tier of memory (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses a multi-tiered system with two tiers of memory with different performance characteristics. Page tables and destination tables are disclosed which can include a present and dirty/change bit that is used in the migration decision process. Performance information is also logged such as access frequency that is used in the migration decision process. Data can be migrated in both directions.).
Consider claim 22, Aguilera et al. discloses a non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method of claim 21 (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], this claim is rejected in the same manner as claim 21.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6, 10, 11, 14, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aguilera et al. (2023/0033029) as applied to claims 1, 8 above, and further in view of Madan et al. (US 2022/0092724).
Consider claim 4, Aguilera et al. discloses tracking and maintaining information based on the performance of memory pages in the tier memory system to determine the movement of memory pages between the tiers, but Aguilera et al. does not specifically describe tracking hits and misses and the latency associated with them and therefore does not alone teach: “wherein the logged processor events comprise information on processor cache hits or misses occurring during accesses to the first tier of memory and the second tier of memory.”. However Madan et al. is directed to a system with memories that have different characteristics, where the hit/miss rate is tracked and used to determine where data should be stored based on the latency ramifications (Madan et al. abstract, [0017], [0025], [0033], [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. with the hit/miss rate tracking of Madan et al. because doing so allows for a better performance to cost trade off for the system (Madan et al.: background).
Consider claim 5, Aguilera et al. discloses tracking and maintaining information based on the performance of memory pages in the tier memory system to determine the movement of memory pages between the tiers, but Aguilera et al. does not specifically describe tracking hits and misses and the latency associated with them and therefore does not alone teach: “wherein the logged processor events comprise information on a latency of accesses to memory pages stored in at least one of the first tier of memory and the second tier of memory.”. However Madan et al. is directed to a system with memories that have different characteristics, where the hit/miss rate is tracked and used to determine where data should be stored based on the latency ramifications (Madan et al. abstract, [0017], [0025], [0033], [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. with the hit/miss rate tracking of Madan et al. because doing so allows for a better performance to cost tradeoff for the system (Madan et al.: background).
Consider claim 6, Aguilera et al. in view of Madan et al. discloses the apparatus according to claim 5, wherein the information on the latency of the accesses to the memory pages reflects cache hits or misses occurring during accesses to at least one of the first tier of memory and the second tier of memory (Madan et al. abstract, [0017], [0025], [0033], [0035]).
Consider claim 10, Aguilera et al. discloses the apparatus according to claim 8, wherein the machine-readable instructions comprise instructions to select a memory page to be moved from the second tier of memory to the first tier of memory if the first and second information on the accesses indicate the access frequency to the memory page is higher than an access frequency of at least some other memory pages (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses migrating memory pages between tiers based on access frequency.). As for the limitation: “and the processor cache miss rate of accesses to the memory page is higher than a pre-defined cache miss threshold.”. Madan et al. is directed to a system with memories that have different characteristics, where the hit/miss rate is tracked and used to determine where data should be stored based on the latency ramifications (Madan et al. abstract, [0017], [0025], [0033], [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. with the hit/miss rate tracking of Madan et al. because doing so allows for a better performance to cost tradeoff for the system (Madan et al.: background).
Consider claim 11, Aguilera et al. discloses the apparatus according to claim 8, wherein the machine-readable instructions comprise instructions to select a memory page to be moved from the second tier of memory to the first tier of memory if the first and second information on the accesses indicate the access frequency to the memory page is higher than an access frequency of at least some other memory pages (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Aguilera et al. discloses migrating memory pages between tiers based on access frequency.). As for the limitation: “and the memory access latency of accesses to the memory page is higher than a pre-defined latency threshold.”. Madan et al. is directed to a system with memories that have different characteristics, where the hit/miss rate is tracked and used to determine where data should be stored based on the latency ramifications (Madan et al. abstract, [0017], [0025], [0033], [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. with the hit/miss rate tracking of Madan et al. because doing so allows for a better performance to cost tradeoff for the system (Madan et al.: background).
Consider claim 14, Aguilera et al. discloses tracking and maintaining information based on the performance of memory pages in the tier memory system to determine the movement of memory pages between the tiers, but Aguilera et al. does not specifically describe tracking hits and misses and the latency associated with them and therefore does not alone teach: “wherein the machine-readable instructions comprise instructions to configure a processor of the computer system to log at least one of a memory access latency of accesses to memory pages and a processor cache hit or miss rate of accesses to memory pages.”. However Madan et al. is directed to a system with memories that have different characteristics, where the hit/miss rate is tracked and used to determine where data should be stored based on the latency ramifications (Madan et al. abstract, [0017], [0025], [0033], [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. with the hit/miss rate tracking of Madan et al. because doing so allows for a better performance to cost tradeoff for the system (Madan et al.: background).
Consider claim 15, Aguilera et al. in view of Madan et al. discloses the apparatus according to claim 14, wherein the machine-readable instructions comprise instructions to configure the processor of the computer system to log at least one of the memory access latency of accesses to memory pages and the processor cache hit or miss rate of accesses to memory pages for a specific computer program being executed by the computer system (Madan et al. abstract, [0017], [0025], [0033], [0035]).
Consider claim 20, Aguilera et al. discloses tracking and maintaining information based on the performance of memory pages in the tier memory system to determine the movement of memory pages between the tiers, but Aguilera et al. does not specifically describe tracking hits and misses and the latency associated with them and therefore does not alone teach: “wherein the computer system comprises a processor, the machine-readable instructions of the apparatus comprising instructions to configure the processor of the computer system to log at least one of a memory access latency of accesses to memory pages and a processor cache hit or miss rate of accesses to memory pages.”. However Madan et al. is directed to a system with memories that have different characteristics, where the hit/miss rate is tracked and used to determine where data should be stored based on the latency ramifications (Madan et al. abstract, [0017], [0025], [0033], [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. with the hit/miss rate tracking of Madan et al. because doing so allows for a better performance to cost tradeoff for the system (Madan et al.: background).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aguilera et al. (2023/0033029) as applied to claim 1 above, and further in view of “Subpage Migration in Heterogeneous Memory Systems”, Henceforth referred to as Adavally et al.
Consider claim 12, Aguilera et al. discloses tracking and maintaining information based on the performance of memory pages in the tier memory system to determine the movement of memory pages between the tiers, but Aguilera et al. does not specifically describe the use of subpages and a moving subpages worth of data and therefore does not alone teach: “wherein a first subset of the memory pages of the memory have a first smaller page size and a second subset of the memory pages of the memory have a second larger page size, the machine-readable instructions comprising instructions to determine a sparseness of accesses to the memory pages having the second larger page size, to split a memory page having the second larger page size into a plurality of memory pages having the first smaller page size based on the sparseness of accesses to the memory page, and to select at least one of the plurality of memory pages having the first smaller page size to be moved between the first tier of memory and the second tier of memory.”. However, Adavally et al. describes a tiered memory system with difference performance characteristics that use huge page sizes and track which parts of the pages are hot and only move the subpages that are hot (abstract, 1. Introduction, 2.3 Motivation for Subpage Migration).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Aguilera et al. to include huge page sizes and split them into subpages for page migration because Adavally et al. discloses that huge pages have the advantage of reducing the size of system tables and the disadvantages of huge pages such as increased migration overhead can be reduced by using subpages (abstract, 1. Introduction, 2.3 Motivation for Subpage Migration).
Consider claim 13, Aguilera et al. in view of Adavally et al. discloses the apparatus according to claim 12, wherein the decision on whether to split the memory page having the second larger page size and the selection of the at least one memory page is based on the first and second information on the accesses (abstract, Fig. 1, [0012], [0013], [0019], [0024], [0025], [0027]-[0030], [0035] and [0049], Adavally et al.: abstract, 1. Introduction, 2.3 Motivation for Subpage Migration).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139