DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the claims
The arguments received on June 30, 2026 have been acknowledged and entered. Claim 1 is amended. Claims 13-20 were previously allowed. Thus, claims 1-12 are currently pending.
Response to Arguments
Applicant’s arguments filed June 30, 2026 with respect to claims 1-12 under 35 U.S.C. 103 have been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Heyward et al. (US 5,654,988, hereinafter referred to as “Heyward”) in view of Noha et al. (US 2005/0086406 A1, hereinafter referred to as “Noha”) and Buckler et al. (US 2015/0109028 A1, hereinafter referred to as “Buckler”).
Regarding claim 1, Heyward teaches a method comprising:
determining whether a real-time interrupt (RTI) pulse is undetected or detected during a monitor window associated (Fig. 6, interrupt acceptance units 614) with a first clock domain (col. 9, lines 6-11: this acceptance of skew variance provided by the synchronization pulse ensures that signals from the interrupt controller clock domain are seen on a particular clock edge when synchronized to the bus clock domain, even if the interrupt controller clock and the bus clock are out of phase internally, note that “the interrupt controller clock domain” reads on “a first clock domain”);
if the RTI pulse is undetected (col. 9, lines 6-11: out of phase internally), generating an interrupt request (IRQ) pulse (col. 8, lines 36-37: the IRQ message contains all necessary information for identifying the IRQ source and its priority) at a time that is determined in the first clock domain (col. 9, lines 6-11: this acceptance of skew variance provided by the synchronization pulse ensures that signals from the interrupt controller clock domain are seen on a particular clock edge when synchronized to the bus clock domain, even if the interrupt controller clock and the bus clock are out of phase internally, note that the above feature of “interrupt controller clock domain are seen a particular clock edge” reads on “at a time is determined in the first clock domain).
Further, Heyward teaches if the RTI pulse is detected, i) generating an IRQ pulse at a first time-offset from the detected RTI pulse, wherein the RTI pulse is based on the second clock domain, ii) determining the predicted next RTI time based on the measured time difference between the detected RTI pulse and the prior RTI pulse, iii) establishing, at a second time-offset from the IRQ pulse, a stop-monitor window during which RTI and sensor data are not accepted and, upon expiration of the stop-monitor window, establishing an RTI monitor window for monitoring the subsequent RTI pulse and the concomitant sensor data, wherein the RTI monitor window is centered about the predicted next RTI time and iv) checking for the subsequent RTI pulse or the concomitant sensor data within the RTI monitor window, wherein the RTI monitor window terminates early upon detection of valid concomitant sensor data, and wherein, if the subsequent RTI pulse is not detected, a periodic IRQ generated at a fixed frequency of the first clock domain is used for a subsequent cycle. See MPEP 2111.04 states that “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.”
Heyward does not specifically teach dynamically adaptive window associated with a first clock domain, wherein a temporal position of the dynamically adaptive monitor window is updated based on a measured time difference between a detected pulse, a prior pulse, and in real time, centering the window on a predicted next pulse time to synchronize with a second clock domain. .
However, Noha teaches dynamically adaptive window associated with a first clock domain, wherein a temporal position of the dynamically adaptive monitor window is updated based on a measured time difference between a detected pulse and a prior pulse (para. [0006]: dynamically adjust the temporal offset; para. [0023]: The clock-retardation unit is configured to dynamically cause the second clock-signal to have a target time-domain offset relative to the first clock-signal; para. [0026]: these selected amounts are each less than a difference between the target time-domain offset between the first and second clock signals; para. [0040]: a target time-domain offset between the first and second clock-signals by changing a delay-line setting of the second delay-line upon detection of a window of opportunity during which the second clock-signal is in a stable state, note that the above feature of “dynamically adjust the temporal offset” in para. [0006], “difference between the target time-domain offset between the first and second clock signals” in para. [0026], and “offset between the first and second clock-signals by changing a delay-line setting of the second delay-line upon detection of a window of opportunity” in para. [0040] reads on “dynamically adaptive window associated with a first clock domain, wherein a temporal position of the dynamically adaptive monitor window is updated based on a measured time difference between a detected pulse and a prior pulse”).
Heyward and Noha are both considered to be analogous to the claimed invention because they are in the same filed of system using timing window. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the dynamically adaptive window such as is described in Noha into Heyward, in order to allow a timer module to be provided for generating interrupts to a system including a microcontroller that provides a real-time interrupt using a dedicated real-time interrupt clock signal (Noha, para. [0006]).
Heyward and Noha do not specifically teach in real time, centering the window on a predicted next pulse time to synchronize with a second clock domain.
However, Buckler teaches in real time (para. [0027]: a continuous measurement system; para. [0028]: continuous frequency and detection interval measurement circuits), centering the window on a predicted next pulse time (para. [0025]: a continuous frequency measurement mechanism for use with predictive synchronizers; para. [0028]: predicted tclock to synchronize with a second clock domain (para. [0028]: current rclock phase input) (para. [0028]: FIG. 1 illustrates a predictive synchronizer system that implements continuous frequency and detection interval measurement circuits…FIG. 2 illustrates an even/odd periodic synchronizer that may be used with embodiments of a continuous measurement synchronizer system 100…A multiplexer 206 and selection circuit 208 allows the receiver to select the most recently written register that is safe to sample at the end of the current receive clock (rclock) cycle. This selection is based on the predicted tclock phase at the end of the current rclock phase input to the selection circuit 208. The selected data is then output from latch 206 as receive data(rdata) synchronized to the receive clock rclock, Note that the above feature of “a continuous frequency measurement mechanism for use with predictive synchronizers” in para. [0025] and “predicted tclok ” and “current rclock phase input” in para. [0028] reads on “window,” “predicted next pulse,” and “second clock domain,” respectively).
Heyward and Buckler are both considered to be analogous to the claimed invention because they are in the same filed of predictive synchronization. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the centering the window on a predicted next pulse time to synchronize with a second clock domain in real time such as is described in Buckler into Heyward, in order to continuously measure frequencies in different clock domains of a system by measuring a ratio of the frequency of a transmit clock domain to a receive clock domain over a number of clock cycles(Bucker, para. [0007]).
Regarding claim 8, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward and Buckler do not specifically teach that the periodic interrupt request pulse is generated by a free-running timer in the first clock domain independent of detection of real-time interrupt pulses.
However, Noha teaches that the periodic interrupt request pulse is generated by a free-running timer in the first clock domain independent of detection of real-time interrupt pulses (para. [0006]: a timer module is provided for generating interrupts to a system including a microcontroller that provides a real-time interrupt using a dedicated real-time interrupt clock signal… A plurality of interrupt generation units each have an input receiving the current count of the free running counter; para. [0009]: For operating systems that require periodic time intervals; para. [0019]: three interrupt generation units IGU0, IGU1 and IGU2, each of which has an input connected to the output of the free running counter FRC, note that the above feature of “the periodic interrupt request pulse is generated by a free-running…an input receiving the current count of the free running counter” in para. [0006], “periodic time intervals” in para. [0009], and “an input connected to the output of the free running counter FRC” in para. [0019] reads on “the periodic interrupt request pulse is generated by a free-running timer in the first clock domain independent of detection of real-time interrupt pulses”).
Heyward and Noha are both considered to be analogous to the claimed invention because they are in the same filed of system using timing window. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the periodic interrupt request pulse such as is described in Noha into Heyward, in order to allow a timer module to be provided for generating interrupts to a system including a microcontroller that provides a real-time interrupt using a dedicated real-time interrupt clock signal (Noha, para. [0006]).
Claims 2-7 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Heyward in view of Noha, Buckler, and Chelmins et al. (US 9,423,426 B1, hereinafter referred to as “Chelmins”).
Regarding claim 2, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach that the method is performed by an input/output (I/O) interface.
However, Chelmins teaches that the method is performed by an input/output (I/O) interface (col. 2, lines 37-39: The system also includes a circuit board configured to interface with the inertial measurement unit, the oscillator, an external trigger pulse, and the main processor ).
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the an input/output (I/O) interface such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 3, Heyward in view of Noha and Buckler teaches all the limitation of claim 2. Heyward, Noha, and Buckler do not specifically teach that the I/O interface is an inertial measurement unit interface.
However, Chelmins teaches that the I/O interface is an inertial measurement unit interface (col. 2, lines 37-39: The system also includes a circuit board configured to interface with the inertial measurement unit, the oscillator, an external trigger pulse, and the main processor).
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the inertial measurement unit interface such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 4, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach that the second clock domain is in a sensor device.
However, Chelmins teaches that the second clock domain is in a sensor device (col. 2, lines 3-7: The circuit board may provide sampling and communication abilities that allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors to be synchronized closely in time; col. 3, lines 51-54: In between receiving these time stamps, and when such a time stamp is unavailable, clock drift may occur between the inertial device and other devices in the navigation system). The above feature of “various navigation sensors “ in col. 2, lines 3-7 and “clock drift may occur between the inertial device and other devices in the navigation system” in col. 3, lines 51-54 reads on “the second clock domain is in a sensor device.”
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the second clock domain such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 5, Heyward in view of Noha, Buckler, and Chelmins teaches all the limitation of claim 4. Heyward, Noha, and Buckler do not specifically teach that the first clock domain is in a processor system configured to receive the IRQ pulse.
However, Chelmins teaches that the IRQ pulse (col. 2, lines 3-7: The circuit board may provide sampling and communication abilities that allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors to be synchronized closely in time; col. 7, lines 9-12: The microcontroller RESET line also serves as an external interrupt request (IRQ) input). The above feature of “an external trigger pulse” in col. 2, lines 3-7 and “serves as an external interrupt request (IRQ) input” in col. 7, lines 9-12 reads on “the IRQ pulse.”
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the IRQ pulse such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 6, Heyward in view of Noha, Buckler, and Chelmins teaches all the limitation of claim 5. Heyward, Noha, and Buckler do not specifically teach that the processor system is a field programmable gate array (FPGA).
However, Chelmins teaches that the processor system is a field programmable gate array (FPGA) (col.12, lines 10-13: a module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, graphics processing units, or the like).
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the field programmable gate array (FPGA) such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 7, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach that the time determined in the first clock domain is based on a system clock having a fixed frequency.
However, Chelmins teaches that the time determined in the first clock domain is based on a system clock having a fixed frequency (col. 6, lines 27-31: A CB3-3I-18M4320™ oscillator 250 operates at 18.432 MHz and provides 50 parts-per-million (ppm) stability to the clock of microcontroller 260. This particular frequency was chosen in this embodiment since the frequency is less than the maximum bus frequency (20 MHz) of microcontroller 260).
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the time determined in the first clock domain such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 9, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach further comprising providing the IRQ pulse to a processor system and providing the sensor data to the processor system substantially when the processor system receives the IRQ pulse.
However, Chelmins teaches further comprising providing the IRQ pulse to a processor system (col. 2, lines 3-7: the circuit board may provide sampling and communication abilities that allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors to be synchronized closely in time; col. 3, lines 41-47: when synchronizing with a radiometric system, a time stamp is periodically received. The radiometric system can often provide a synchronization pulse or time stamp that represents a given instant in time when the radiometric navigation information was transmitted or processed by the system or local radiometric receiver. For instance, for GPS, the time stamp may be received at a rate of 1 pulse per second (“PPS”); col. 7, lines 9-12: the microcontroller RESET line also serves as an external interrupt request (IRQ) input); the above feature of “an external trigger pulse (i.e., IRQ pulse)” in col. 2, lines 3-7, “provide a synchronization pulse or time stamp (i.e., IRQ pulse) that represents a given instant in time” in col. 3, lines 41-47, and “interrupt request (IRQ) input” in col. 7, lines 9-12 reads on “providing the sensor data to the processor system substantially when the processor system receives the IRQ pulse;” and
providing the sensor data to the processor system when the processor system receives the IRQ pulse (col. 2, lines 3-7: The circuit board may provide sampling and communication abilities that allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors to be synchronized closely in time; col. 3, lines 41-47: when synchronizing with a radiometric system, a time stamp is periodically received. The radiometric system can often provide a synchronization pulse or time stamp that represents a given instant in time when the radiometric navigation information was transmitted or processed by the system or local radiometric receiver. For instance, for GPS, the time stamp may be received at a rate of 1 pulse per second (“PPS”); col. 7, lines 9-12: The microcontroller RESET line also serves as an external interrupt request (IRQ) input). The above feature of “an external trigger pulse (i.e., IRQ pulse)” in col. 2, lines 3-7, “the radiometric navigation information (e.g. sensor data) was transmitted or processed by the system (e.g. processor system)” in col. 3, lines 41-47, and “interrupt request (IRQ) input” in col. 7, lines 9-12 reads on “providing the sensor data to the processor system substantially when the processor system receives the IRQ pulse.”
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the providing the IRQ pulse to a processor system and providing the sensor data to the processor system such as are described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 10, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach further comprising: responsive to detecting the subsequent RTI pulse or the concomitant sensor data outside the RTI monitor window, discarding at least one of the following: (i) the subsequent RTI pulse, and (ii) the concomitant sensor data.
However, Chelmins teaches further comprising: responsive to detecting the subsequent RTI pulse or the concomitant sensor data outside the RTI monitor window, discarding at least one of the following: the subsequent RTI pulse, and the concomitant sensor data (col. 2, lines 3-7: The circuit board may provide sampling and communication abilities that allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors to be synchronized closely in time; col. 3, lines 51-54: In between receiving these time stamps, and when such a time stamp is unavailable, clock drift may occur between the inertial device and other devices in the navigation system; col. 9, lines 23-31: SCI_ISR: The SCI_ISR routine receives command bytes from the navigation processor. These command bytes are used by the IRQ_ISR subroutine to decide how to collect data. When ‘g’ is received (“go”), data is collected and transmitted continuously at 500 Hz. When ‘d’ is received (“data”), data is collected and transmitted over the next 1 second only. When ‘o’ is received (“one”), only a single block of data is collected and transmitted. Any other character will disable data collection and transmission as soon as possible ). The above feature of “an external trigger pulse” in col. 2, lines 3-7, “data is collected and transmitted over the next 1 second only,” “only a single block of data is collected and transmitted,” and “any other character will disable data collection” in col. 9, lines 23-31 reads on “RTI monitor window for when the subsequent RTI pulse and the concomitant sensor data are prevented from being monitored or provided to a processor system.”
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the (i) the subsequent RTI pulse, and (ii) the concomitant sensor data such as are described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 11, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach further comprising transferring the concomitant sensor data into a buffer within the first time-offset.
However, Chelmins teaches further comprising transferring the concomitant sensor data into a buffer (col. 7, lines 9-12: see claim 1 above; col. 11, lines 30-31: see above col. 11, lines 37-40: The microcontroller provides buffering and parallel operation for the USB transmission, which eliminates the time cost of SPI reads. This saves 40 μsec per each of 8 reads, or about 320 μse) within the first time-offset (col. 3, lines 51-54: see claim 1 above; col 4, lines 16-23: see claim 1 above).
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the transferring the concomitant sensor data into a buffer such as is described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, Col. 3, lines 36-38).
Regarding claim 12, Heyward in view of Noha and Buckler teaches all the limitation of claim 1. Heyward, Noha, and Buckler do not specifically teach the first time-offset, the second time-offset, and the time span for monitoring the subsequent RTI pulse and the concomitant sensor data occur sequentially occur between consecutive IRQ pulses.
However, Chelmins teaches the first time-offset (col. 2, lines 3-7; col. 3, lines 41-46), the second time-offset (col. 3, lines 51-54; col 4, lines 16-23; col. 7, lines 9-12; col. 11, lines 30-31), and the time span for monitoring the subsequent RTI pulse and the concomitant sensor data occur sequentially occur between consecutive IRQ pulses (col. 2, lines 3-7: The circuit board may provide sampling and communication abilities that allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors to be synchronized closely in time; col. 3, lines 41-47: when synchronizing with a radiometric system, a time stamp is periodically received. The radiometric system can often provide a synchronization pulse or time stamp that represents a given instant in time when the radiometric navigation information was transmitted or processed by the system or local radiometric receiver. For instance, for GPS, the time stamp may be received at a rate of 1 pulse per second (“PPS”); col. 9, lines 24-28:These command bytes are used by the IRQ_ISR subroutine to decide how to collect data. When ‘g’ is received (“go”), data is collected and transmitted continuously at 500 Hz. When ‘d’ is received (“data”), data is collected and transmitted over the next 1 second only. When ‘o’ is received (“one”), only a single block of data is collected and transmitted). The above feature of “allow the IMU to be sampled at precise time intervals based on an external trigger pulse, which enables various navigation sensors” in col. 2, lines 3-7, “a time stamp is periodically received” in col. 3, lines 41-47, and “data is collected and transmitted over the next 1 second only. When ‘o’ is received (“one”), only a single block of data is collected and transmitted” in col. 9, lines 24-28 reads on “the time span for monitoring the subsequent RTI pulse and the concomitant sensor data occur sequentially occur between consecutive IRQ pulses.”
Heyward and Chelmins are both considered to be analogous to the claimed invention because they are in the same filed of circuit using clock. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the first time-offset and the time span for monitoring the subsequent RTI pulse and the concomitant sensor data occur sequentially occur between consecutive IRQ pulses such as are described in Chelmins into Heyward, in order to facilitate more effective time synchronization of an device with other devices (Chelmins, col. 3, lines 36-38).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dally (US 8,428,207 B1) teaches a system and method provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SANGKYUNG LEE/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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