DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 2-3B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 22 is objected to because of the following informalities:
In lines 6-7 the Examiner suggests inserting –configured—between “common-source” and “devices. Appropriate correction is required.
Claim 23 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 11. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilson et al. (US Pub. No. 20170093403).
a) regarding claim 1:
Wilson et al. discloses a stacked voltage domain level shifting circuit (321 in Figure 3 and Figure 7C/ 322 in Figure 3 and Figure 7D/521 in Figure 5 and Figure 8C) comprising:
a storage cell (N1 and N2 in Figure 7C/; and P1 and P2 in Figure 7D/N1,N4,P2,P4 in Figure 8A and paragraphs [0064] and [0069]); and
control drivers (301 and 721/302 and 731/311 and 851) powered by a mid-range supply rail (Vdd/2) of the stacked voltage domain level shifting circuit, the control drivers coupled to drive common-source configured devices (P1 and P2 in Figure 7C/N1 and N2 in Figure 7D/N2 and N5 in Figure 8A and paragraph [0064] and [0069]) coupled to storage nodes of the storage cell.
b) regarding claim 2:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the mid-range supply rail (Vdd/2) powers positive supply terminals of the control drivers (302 and 731).
c) regarding claim 3:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the mid-range supply rail (Vdd/2) powers negative supply terminals of the control drivers (301 and 721).
d) regarding claim 4:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the common-source configured devices comprise a pair of pull-up PFETs (P1 and P2 in Figure 7C).
e) regarding claim 5:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the common-source configured devices comprise a pair of pull-down NFETs (N1 and N2 in Figure 7D).
f) regarding claim 6:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the storage cell comprises a pair of cross-coupled inverters (N1,N4,P2,P4 in Figure 8A and paragraphs [0064] and [0069]).
g) regarding claim 7:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the stacked voltage domain level shifting circuit (322 in Figure 3 and Figure 7D) is configured to shift signals from a first voltage domain (Vdd/2 to ground) to a second voltage domain (Vdd to Vdd/2) higher than the first voltage domain (paragraph [0051]).
h) regarding claim 8:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the stacked voltage domain level shifting circuit (321 in Figure 3 and Figure 7C) is configured to shift signals from a first voltage domain (Vdd to Vdd/2) to a second voltage domain (Vdd/2 to ground) lower than the first voltage domain (paragraph [0051]).
i) regarding claim 9:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the storage cell comprises cross-coupled PFETs (P1 and P2 in Figure 7D).
j) regarding claim 10:
Wilson et al. discloses the stacked voltage domain level shifting circuit of claim 1, wherein the storage cell comprises cross-coupled NFETs (N1 and N2 in Figure 7C).
k) regarding claim 19:
Wilson et al. discloses a method for shifting a signal from a first voltage level to a second voltage level (321 in Figure 3 and Figure 7C/ 322 in Figure 3 and Figure 7D), the method comprising:
transitioning a pair of stored values at storage nodes (Z and Z̅) of a storage cell (N1 and N2 in Figure 7C/; and P1 and P2 in Figure 7D) of a stacked voltage domain level shifting circuit;
operating a pair of inverters (301 and 721/302 and 731) with a supply voltage provided from a mid-range supply rail (Vdd/2) of the stacked voltage domain level shifting circuit; and
driving gates of common-source configured devices (P1 and P2 in Figure 7C/N1 and N2 in Figure 7D) coupled to the storage nodes (Z and Z̅) with outputs of the inverters (301 and 721/302 and 731).
l) regarding claim 20:
Wilson et al. discloses the method of claim 19, wherein the mid-range supply rail (Vdd/2) powers a positive supply terminal of the inverters (302 and 731).
m) regarding claim 21:
Wilson et al. discloses the method of claim 19, wherein the mid-range supply rail (Vdd/2) powers a negative supply terminal of the inverters (301 and 721).
Allowable Subject Matter
Claims 11-17 are allowed.
Claim 22 would be allowable if rewritten or amended to overcome the objections set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to disclose or make obvious a stacked voltage domain level shifting circuit further comprising: a pair of cascoded transistors interposed between the storage nodes and the common-source configured device pair, along with all the other limitations as required by claims 11 and 22.
Response to Arguments
Applicant's arguments filed 10/20/2025 have been fully considered but they are not persuasive.
In response the drawings objections it is noted that no new drawings were submitted with the amendments filed 10/20/2025.
The Applicants argue that, “To the best of the Applicant’s understanding, the rejection seems to rely on obviating the distinction recited in the Claims between the bit storing cell and the common source devices coupled to the storage nodes of the bit storing cell. More specifically, the rejection appears to be treating transistors Pl and P2 or N1 and N2 of the cross-coupled inverters in the Wilson circuits to read on both the bit storing cell and the common source devices coupled to the storage nodes of the bit storing cell. The Applicant respectfully asserts that obviating this distinction is not a reasonable interpretation of the language of the Applicant's Claims. It is also an interpretation that does not comport with the Applicant's drawings and Specification.”
The Examiner respectfully disagrees. In paragraphs [0043]-[0044] and Figures 3A and 3B the Applicant defined a “storage cell” 302 as a cross-coupled pair (PMOS transistors M2 and M3 in Figure 3A; and NMOS transistors M2 and M3 in Figure 3B). This is the definition of a storage cell that was used in the claim interpretation. Thus it should be clear that Wilson et al. discloses a storage cell (i.e. N1 and N2 in Figure 7C are a cross-coupled pair matching the definition of a storage cell provided by the Applicant) that is separate from the common-source configured devices (i.e. P1 and P2 in Figure 7C). Therefore the rejection under 35 USC 102(a)(1) has been maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick O'Neill whose telephone number is (571)270-1677. The examiner can normally be reached Monday- Friday 9AM-5PM EST.
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/PATRICK O NEILL/Primary Examiner, Art Unit 2842