DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
Applicant is advised that should claim 1 be found allowable, claim 16 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 10, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (previously cited CN112203440A) in view of Jang (previously cited KR 20030047088 A) and Hirata (US2007/0074902A1).
Regarding claims 1 and 16, Chen discloses (limitations not disclosed are crossed out):
A method of manufacturing a component carrier, the method comprising:
laser drilling a blind hole (113, Fig. 2; see [0019] and [0020]) in a layer stack; and
subsequently extending the blind hole to a through hole
wherein the method comprises extending the blind hole to the to produce a through hole
wherein the backside electrically conductive layer structure (111) has a larger overhang than a frontside electrically conductive layer structure (112) of the layer stack,
Chen also discloses filling the through hole with a filling medium (electroplating copper 115), as in claim 7, as well as the lack of an offset between a center of the through hole at a frontside and a center of the through hole at a backside of the layer stack, as in claim 10. However, Chen does not disclose the specific manner of forming the through hole, the newly-added limitations pertaining to electrically conductive layer structure thickness variation, nor the further details of claims 3-5, 8, 9 and 11-13.
Jang discloses the claimed invention as follows (refer to the first full paragraph on second page of translation; limitations not disclosed by Jang are crossed out):
Claim 1. A method of manufacturing a component carrier, the method comprising:
laser drilling (see [37] and Fig. 8(c)) a blind hole (105, Fig. 8(d)) in a layer stack (structure of Fig. 8(a)); and
subsequently extending the blind hole to a through hole (105, Fig. 8(f)) by etching (see [38]), wherein
the method comprises laser drilling the blind hole in the layer stack only from one side of the layer stack (see Fig. 8(c)),
wherein the method comprises extending the blind hole to produce a through hole by etching in a region of the blind hole simultaneously at two opposing exposed surface portions of a backside electrically conductive layer structure of the layer stack on an electrically insulating layer structure of the layer stack (see Fig. 8(e) and [38]),
.
Claim 2. The method according to claim 1, wherein the method comprises laser drilling through1 the frontside electrically conductive layer structure (102a; see Fig. 8(b)) of the layer stack and into at least part of an electrically insulating layer structure (101) of the layer stack.
Claim 3. The method according to claim 1, wherein the method comprises forming a window in the frontside electrically conductive layer structure (102a, Fig. 8(b); see [36]) of the layer stack by etching, and thereafter laser drilling (Figs. 8(c) and 8(d); see [37]) through the window into at least part of the electrically insulating layer structure.
Claim 4. The method according to claim 1, wherein the method comprises laser drilling through the entire electrically insulating layer structure of the layer stack up to the backside electrically conductive layer structure of the layer stack as a stop layer. See [37].
Claim 5. The method according to claim 4, wherein the method comprises, after said laser drilling through the entire electrically insulating layer structure up to the backside electrically conductive layer structure, forming a window in the backside electrically conductive layer structure by etching (see Figs. 8(e) and 8(f); see [38]).
Claim 7. The method according to claim 1,
Claim 8. The method according to claim 7,
Claim 9. The method according to claim 7,
Claim 10. The method according to claim 1, comprising at least one of the following features:
wherein the method comprises laser drilling the blind hole using at least one of a carbon dioxide laser and an ultraviolet laser (see “CO2 laser (104)” in [37]);
wherein, before etching, at least one of the frontside electrically conductive layer structure and the backside electrically conductive layer structure of the layer stack has a thickness of not more than 20 µm;
wherein, after etching, at least one of the frontside electrically conductive layer structure and the backside electrically conductive layer structure of the layer stack has a thickness in a range from 1 µm to 7 µm;
wherein the etching comprises a first etching process for removing surface metal material followed by a second etching process enhancing surface roughness, wherein the first etching process comprises a desmear process and/or the second etching process comprises a flash etching process;
wherein the method comprises forming the through hole without a lateral offset between a center of the through hole on the frontside and a center of the through hole on the backside of the layer stack (see [39]);
wherein the method comprises filling the through hole in the layer stack with an electrically conductive filling medium without bridge plating, wherein the layer stack has a thickness below 80 µm.
Claim 11. The method according to claim 1, wherein the method comprises
protecting at least part of an exterior surface of at least one of the frontside electrically conductive layer structure at the frontside of the layer stack and the backside electrically conductive layer structure at the backside of the layer stack by a protection structure (“resist” in [36]) at least during the etching, and
patterning the protection structure before the etching (see “exposure, development” in [36]).
Claim 12. The method according to claim 1,
Claim 13. The method according to claim 12, comprising at least one of the following features:
Claim 16. A method of manufacturing a component carrier, the method comprising: laser drilling (see [37] and Fig. 8(c)) a blind hole (105, Fig. 8(d)) in a layer stack (structure of Fig. 8(a)); and
subsequently extending the blind hole to a through hole (105, Fig. 8(f)) by etching (see [38]), wherein
the method comprises laser drilling the blind hole in the layer stack only from one side of the layer stack (see Fig. 8(c)),
wherein the method comprises extending the blind hole to the through hole by etching in a region of the blind hole simultaneously at two opposing exposed surface portions of a backside electrically conductive layer structure of the layer stack on an electrically insulating layer structure of the layer stack (see Fig. 8(e) and [38]),
Chen teaches the holes can be formed using lasers (see [0022]). However, Chen teaches that laser drilling through copper requires high-power lasers, which can vaporize substances when processing the copper, which can affect the optical lens of the laser generator, thereby affecting performance (see [27]). Such problems are avoided by using the process disclosed by Jang (see [42]). In view of the combined teachings of Jang and Chen, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the process of Chen so that the through holes through the conductive layers and through the insulating layer are formed using the process taught by Jang, for the advantages disclosed by Jang, such as avoiding contamination of the optical lens. Regarding the small hole 114, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that the patterning to delimit the area to be etched would have been modified accordingly, to ensure the lower hole 114 is still formed small.
Regarding the newly added limitations, it is known in the art to form the copper foils on a double-sided copper-clad laminate, for use in manufacturing a circuit board, having the same thickness. For example, Hirata discloses a double-sided copper laminated plate consisting of an epoxy-based insulation layer and copper foils with a thickness of 12 µm laminated on both sides thereof, by electrolytic nickel plating treatment (corresponding to FIG. 1(a); see [0131]). Given the two significant digits of the value “12”, it is understood the value an vary between 11.5 µm and 12.5 µm, such that, a maximum possible variation between upper and lower copper foils is (12.5/11.5-1)*100 = ~8.7%.
In view of the further teachings of Hirata, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to apply the teachings of Chen as modified in view of Jang to use a laminate stack in which the frontside and backside electrically conductive structures have a same thickness, such as 12 µm, as a matter of choosing a conventional conductive layer value, with predictable results. It should be noted the current claim language does not clarify at which point in the process the thickness variation must meet the specific requirements.
Claim(s) 8, 9, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Jang and Hirata, further in view of Rivett (previously-cited EP0189975A1).
Cheng as modified in view of Jang and Hirata discloses the claimed invention except for filling the through hole at least partially with a filling medium by electroless plating to form a seed layer and electroplating on the seed layer, as claimed in claims 8 and 9. Modified Chen also does not discloses forming at least one electrically conductive trace based on at least one of a frontside electrically conductive layer structure and a backside electrically conductive layer structure, and at least one of the following features: a) the method comprises forming the at least one electrically conductive trace by patterning at least one of the frontside electrically conductive layer structure and the backside electrically conductive layer structure, by etching simultaneously with the extending of the blind hole to the through hole by etching; and b) the method comprises plating the at least one electrically conductive trace simultaneously with at least partially filling the through hole by the plating.
Rivett shows it is known in the art to form a seed layer (20, Figs. 4 and 6) on the walls of a through hole by electroless plating (col. 2, Ins. 17-21) and thereafter electroplating (24, 26, 28, Fig. 6; see col. 2, Ins. 27-35) to partially fill the through hole with a conductive medium, thereby forming a plated through hole electrically connecting two conductive layers.
In view of the teachings of Rivett, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form a seed layer by electroless plating inside the through hole, followed by the electroplating, to thereby form the electroplated material 115.
Rivett also shows it is known to pattern the two conductive layers (compare Fig. 1 and Fig. 3) to thereby form conductor patterns, such as trace 18 in Fig. 3, prior to plating the through hole. When the through hole is electrolessly-plated, the trace is also simultaneously electrolessly-plated (compare Figs. 3 and 4; see col. 2, Ins. 17-21).
In view of the teachings of Rivett, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to pattern the conductive layers 111 and 112 of modified Chen, prior to the electroless plating, to define circuit layers including traces, followed by electroless plating of the entire substrate, masking while leaving exposed areas to be electroplated, then electroplating to form a plated layer, including in through holes, whereby the electroless layer that was covered by the mask can be removed. One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to do so, as a choice among conventional printed circuit board fabrication techniques for patterning conductive layers and plating of through holes, with predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US5242540A teaches subjecting a copper foil-clad circuit board substrate comprising an electrically insulating support overlaid on one or both sides with a copper foil having an average thickness of 12 µm or more to etching with a copper-etching solution thereby to reduce the thickness of the copper foil on at least one side of the insulating support to 10 to 80% of its original thickness with the thickness variation of the remaining etched copper foil being within +/- 1.0 µm of the desired thickness.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIVIUS R CAZAN whose telephone number is (571)272-8032. The examiner can normally be reached Monday - Friday noon-8:30 pm ET.
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
1 The laser drilling into the insulating layer structure occurs through the conductive layer 102a, since the laser 104 passes through the opening in the conductive layer. See Fig. 8(c).
Prosecution Insights