DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 4, 2026 has been entered.
Response to Amendment
The amendment filed February 4, 2026 has been entered. Claims 21-40 remain pending in this application.
The amendment to the abstract, drawings, and claims have overcome the objections to the abstract, drawings, and claims, and the rejection to the claims under 35 U.S.C. 112, as presented in the prior office action mailed December 4, 2025.
Priority
Applicant’s claim for the benefit of prior-filed application 17/230,490, now issued as US 11,467,988 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 112(a) as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 17/230,490, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
Claims 23 and 32 recite, using claim 23 for example language, “delay forwarding of memory requests corresponding to the given memory fetch granule until all memory requests corresponding to the given memory fetch granule have been received”.
Claims 23 and 32 do not clarify what “all memory requests corresponding to the given memory fetch granule” refers to – whether all memory requests for all time, during a time window, before a threshold is reached, etc. Upon review of the instant and parent specification, the process described in [0044-0047] and the embodiment described in [0050] provide different embodiments for determining when to stop accumulating requests – with [0045] determining if the size of the new memory request is larger than a memory fetch granule, [0045] determining if a threshold amount of time has elapsed while waiting for a subsequent memory request, and [0047] determining if the accumulated amount of data reaches a memory fetch granule size. However, the claims recite “all memory requests corresponding to the memory fetch granule” with no limitation, and so the entire scope must be sufficiently described in the specification. A review of the specifications show that the broadest reasonable scope of the claims is not described in the specifications.
Claims 26 and 35 recite, using claim 25 for example language, “wherein the received memory request is not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been received”.
Claims 26 and 35 do not recite how the system determines whether all memory requests have been received, nor do they define a threshold for consideration/receiving of memory requests corresponding to the memory fetch granule. Upon review, the instant specification and the parent application specification generally discuss arbitration, and in the instant application, an example is shown in [0050] where a request is selected only if an entire memory fetch granule has been received, which is close to the claim language. Notably, this is sufficient to demonstrate possession of the claimed invention of similar claims such as claim 27. However, claims 26/35 recite a broader scope than claim 27, as they recite “all memory requests corresponding to the memory fetch granule”, with no limitation on size or timing, and as such the example of [0050], while providing possession of an example embodiment, is not considered sufficient for demonstrating possession of the entire breadth of the claims.
Consequently, claims 23, 26, 32, and 35 are examined with an effective filing date of December 21, 2022, and all other pending claims are examined with an effective filing date of April 14, 2021.
Claim Objections
Claims 29 and 39 are objected to because of the following informalities:
Claim 29 recites “the memory requests corresponding to the given memory fetch granule”, but should recite “the plurality of received memory requests corresponding to the given memory fetch granule” for consistency with claim 21,
Claim 39 recites “the agent”, but should recite “the one or more agents” for consistency with claim 37.
Appropriate correction is required.
Claim Interpretation
MPEP 2111.04(II) provides that “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.”
Claim 30 recites “if the received memory request is not a last memory request of a plurality of received memory requests…. Continue sending… individual ones of the plurality of received memory requests…”.
The act of continuing to send individual memory requests of the plurality of received memory requests is explicitly contingent on the received memory request not being a last memory request of a plurality of received memory requests. This condition is not recited as required within the broadest reasonable interpretation of the claim, and as such, neither is the act of continuing to send the individual memory requests.
Claim 33 recites “forwarding the received memory request… responsive to the received memory request winning arbitration amongst a plurality of pending memory requests”.
The act of forwarding the received memory request is explicitly contingent on the received memory request winning arbitration”. This condition is not recited as required within the broadest reasonable interpretation of the claim, and as such, the act of forwarding the received memory request is not required either.
Claim 34 recites “responsive to the received memory request winning arbitration, memory requests other than memory requests corresponding to the memory fetch granule are not eligible to win arbitration”.
The limitation regarding arbitration eligibility of other memory requests is explicitly contingent on the received memory request winning arbitration. This condition is the same as in claim 33, which was not required in the broadest reasonable interpretation of the claim, nor does claim 34 recite a limitation that requires the condition. Therefore, the condition is still not required in the broadest reasonable interpretation of the claim, and so the limitation regarding other memory requests’ arbitration is not required within the broadest reasonable interpretation of the claim.
Examiner notes that if applicant does not seek to have these limitations be interpreted as contingent limitations, two potential amendments are possible: either remove the language that identifies the limitations as contingent on a condition, or recite additional limitations requiring the performance of the condition.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 23, 26, 32, and 35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 23 and 32 recite, using claim 23 for example language, “delay forwarding of memory requests corresponding to the given memory fetch granule until all memory requests corresponding to the given memory fetch granule have been received”.
Examiner first notes that the subject matter of claims 23 and 32 are first recited in the preliminary amendment filed July 17, 2023, and so the analysis of written description requirement does not include a presumption for an adequate written description, as these are not the originally filed claims, see MPEP 2163(I)(A) and (B).
Claims 23 and 32 do not clarify what “all memory requests corresponding to the given memory fetch granule” refers to – whether all memory requests for all time, during a time window, before a threshold is reached, etc. Upon review of the instant specification, the process described in [0044-0047] and the embodiment described in [0050] provide different embodiments for determining when to stop accumulating requests – with [0045] determining if the size of the new memory request is larger than a memory fetch granule, [0045] determining if a threshold amount of time has elapsed while waiting for a subsequent memory request, and [0047] determining if the accumulated amount of data reaches a memory fetch granule size. However, the claims recite “all memory requests corresponding to the memory fetch granule” with no limitation, and so the entire scope must be sufficiently described in the specification, therefore resulting in a written description issue.
Examiner notes that an amendment describing “all memory requests corresponding to the memory fetch granule” in a manner commensurate with Fig. 6 would sufficiently establish possession and address this rejection.
Claims 26 and 35 recite, using claim 25 for example language, “wherein the received memory request is not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been received”.
Examiner first notes that the subject matter of claims 26 and 35 are first recited in the preliminary amendment filed July 17, 2023, and so the analysis of written description requirement does not include a presumption for an adequate written description, as these are not the originally filed claims, see MPEP 2163(I)(A) and (B).
Examiner also notes that due to the breadth of the claims, claims 26 and 35 do not recite how the system determines whether all memory requests have been received, nor do they define a threshold for consideration/receiving of memory requests corresponding to the memory fetch granule. Upon review, the instant specification generally discuss arbitration, with an example is shown in [0050] where a request is selected only if an entire memory fetch granule has been received, which is close to the claim language. Notably, this is sufficient to demonstrate possession of the claimed invention of similar claims such as claims 23 and 27. However, this contrasts with the broader claim language of claims 26/35, as they recite “all memory requests corresponding to the memory fetch granule”, with no limitation on size or timing, and as such the example of [0050], while providing possession of an example embodiment, is not considered sufficient for demonstrating possession of the entire breadth of the claims, meriting a written description rejection.
Examiner notes that an amendment to clarify eligibility based on a size threshold similar to what is recited in claim 27 would sufficiently establish possession and address this rejection.
Claims 23, 26, 32, and 35 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for a scope where “all memory requests corresponding to the given memory fetch granule have been received” is narrowed according to a size/time threshold, see [0044-0047,0050] of the specification and compare with claim 27, does not reasonably provide enablement for the broadest reasonable interpretation of “all memory requests corresponding to the given memory fetch granule has been received”. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the invention commensurate in scope with these claims.
Examiner identifies the breadth of the claims and the amount of direction provided by the inventor to be the Wands factors to support an enablement rejection.
As discussed in the written description rejection above, claims 23 and 32 recite the broad scope to “delay forwarding of memory requests corresponding to the given memory fetch granule until all memory requests corresponding to the given memory fetch granule have been received” and claims 26 and 35 recite the broad scope that “the received memory request is not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been received”. For both pairs of claims, the breadth of the claim language is specifically focused on the limitation “all memory requests corresponding to the memory fetch granule” common to both claims. The claim language in and of itself does not provide for a limit on what “all memory requests” refers to, whether it is a time window or a size threshold (where the size threshold is supported in the specification at [0050], and both a time window/size threshold are described in [0044-0047]). As such, “all memory requests” can reasonably be interpreted to mean “all memory requests corresponding to the memory fetch granule” for all time some other metric besides the accumulation size threshold/time windows as described.
Such a breadth of claim would require some disclosure in the specification on how this breadth of “all memory requests” affects delaying forwarding as recited in claims 23/32 and the arbitration eligibility in claims 26/35.
As noted above, the specification at [0044-0047] provides an example where subsequent memory requests are compared to a time window or a cumulative size of data for the memory fetch granule, and the specification at [0050] disclose an example where the RT request is only selected when the entire MFG is filled, i.e. – the MFG has accumulated requests to meet the MFG size. However, this only enables one embodiment. No discussion is found in the specification to suggest how, given open-ended reading of “all memory requests”, a determination could be made when all memory requests are received to determine to stop delaying forwarding or to determine arbitration eligibility.
As such, the specification fails to enable the full scope of claims 23, 26, 32, and 35 as required by the enablement requirement.
An amendment to the claims similar to what is suggested to address the written description issue would also address the enablement issue, as it would narrow the scope to focus on what is already described in the specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 24-27 and 30-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24 recites “the received memory request”, but this now lacks proper antecedent basis, as parent claim 21 has been amended to recite both “a received memory request” and “a plurality of received memory requests”, so claim 24 is now indefinite for failing to specify which of the received memory requests is referred to in the claim language. For the purpose of examination, it is assumed that claim 21 recites “a first received memory request”/”the first received memory request” to refer to the individual received memory request, and that claim 24 also recites “the first received memory request”.
Claims 25 and 26 are rejected for dependence on claim 24.
Examiner also notes that claims 25 and 26 feature the same issue as claim 24 regarding “the received memory request” with the same suggestion for amendment.
Claim 27 recites “the memory requests”, but this lacks proper antecedent basis, as there are multiple memory requests recited between claim 21 and claim 27 that could provide antecedent basis, where the claim limitation does not specify which term to draw antecedent basis from. For the purpose of examination, it is assumed this recites “the accumulated memory requests”
Claims 30 and 37 recite, using claim 30 for example language, “a sequentially addressable portion of memory having a size corresponding to the access granularity”, but “the access granularity” now lacks proper antecedent basis as this is now the first time the phrase is recited in the claims. For the purpose of examination, it is assumed the phrase instead recites “an access granularity”.
Claims 31-36 and 38-40 are rejected for dependence on claims 30 and 37, respectively.
Claim 33 recites “the received memory request”, but this now lacks proper antecedent basis, as parent claim 31 has been amended to recite both “a received memory request” and “a plurality of received memory requests”, so claim 33 is now indefinite for failing to specify which of the received memory requests is referred to in the claim language. For the purpose of examination, it is assumed that claim 30 recites “a first received memory request”/”the first received memory request” to refer to the individual received memory request, and that claim 34 also recites “the first received memory request”.
Claim 35 is rejected for dependence on claim 34.
Examiner also notes that claims 35 features the same issue as claim 34 regarding “the received memory request” with the same suggestion for amendment.
Claim 36 recites “the memory requests”, but this lacks proper antecedent basis, as there are multiple memory requests recited between claim 30 and claim 36 that could provide antecedent basis, where the claim limitation does not specify which term to draw antecedent basis from. For the purpose of examination, it is assumed this recites “the accumulated memory requests”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 29, 33, and 34 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 29 recites “wherein the memory requests corresponding to the given memory fetch granule identify sequential physical addresses”. Claim 21 has been amended to recite “the received memory request targeting a portion of a given memory fetch granule identifying a sequentially addressable portion of memory”. As such, claim 21 already recites where memory requests that target a given memory fetch granule identify sequentially addressable portions of memory, i.e. a sequential physical address, as the memory is a physical memory. Claim 29 therefore fails to further limit the subject matter of claim 21, meriting this rejection.
Claims 33 and 34 are identified to recite limitations that are identified to be contingent, and further where the conditions are not required in the broadest reasonable interpretation of the claim, see the section on claim interpretation above. As such, the limitations of claims 33 and 34 are not required within the broadest reasonable interpretation of the claim, and as these are the only limitations, then claims 33 and 34 fail to further narrow the subject matter of claim 30, meriting this rejection.
Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Regarding claims 33 and 34, examiner notes that amending the claims to address the contingent limitations, as suggested in the claim interpretation section above, would sufficiently address the rejection under 35 U.S.C. 112(d) as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21-27 and 29-37 are rejected under 35 U.S.C. 103 as being unpatentable over Tripathi et al. (US 2014/0071140) in view of Biswas et al. (US 2020/0004444).
Regarding claim 21, Tripathi teaches an apparatus (Fig. 2, apparatus 200 100), comprising:
Circuitry (“During processing, control logic within the display controller may send multiple memory access requests to the memory controller,” [0011]) configured to:
forward a first received memory request on a path to a memory controller (“The multiple functional units on the chip are sources for memory access requests sent to the memory controller. Additionally, one or more functional units may include multiple sources for memory access requests to send to the memory controller,” [0005] and ”During processing, control logic within the display controller may send multiple memory access requests to the memory controller,” [0011] teaches that the logic forward requests sourced from the functional units to the memory controller),
if the first received memory request is not a last memory request of a plurality of received memory requests, continue sending individual ones of the plurality of received memory requests on the path to the memory controller until all of the plurality of received memory requests have been forwarded on the path to the memory controller (in the context of Fig. 6, Tripathi provides a process for processing memory requests; in steps 612 and 614, Tripathi explicitly determines if a request is a last memory request to send, and if not, it circles back to step 602 to send memory access requests for processing, reading on this limitation; examiner further notes that even in a requestor burst mode, a determination is made if the received memory request is the last of a limit number of queued access requests, i.e. the last of a limit number, which also reads upon the limitation of the claim).
Tripathi fails to teach where the first received memory request targeting a portion of a given memory fetch granule identifying a sequentially addressable portion of memory having a size corresponding to an access granularity as well as where the plurality of received memory requests correspond to the memory fetch granule and where the sending provides a sequential access pattern.
Biswas’ disclosure relates to a multi-agent system sending a stream of commands to memory and as such comprises analogous art in the same field of endeavor.
As part of this disclosure, in the context of Fig. 1, Biswas provides that a series of memory transactions can be provided in data stream 110 containing data blocks 130 that are to be sent to the memory circuit, see [0026]. Biswas provides that “To send a particular data block to a given memory circuit, Memory Controller 120 may generate one or more memory commands, each command sending a part of the particular data block. For example, to send Data Block 130b to Memory Circuit 155b, Memory Controller 120 generates four memory commands for sending four parts of Data Block 130b (parts labeled “e,” “f,” “g,” and “h”). Each part of Data Block 130b may correspond to an amount of data to be sent to a particular memory bank in Memory Circuit 155b, such as, for example, an amount of data to fill a page of a memory bank. An amount of data in a given data block may correspond to a memory fetch granule. As used and described herein a memory fetch granule (or “MFG”) refers to an amount of data that can be accessed via a single memory channel across multiple banks included in a given memory circuit as part of a single memory access transaction. In various embodiments, the amount data included in an MFG may be a function of an architecture of a memory circuit. For example, an MFG may include a number of data bits corresponding to a respective page from each bank included in a memory circuit,” [0030], see also [0061] where data blocks and MFG is used interchangeably, where a page is the amount of data accessible in a single command, see [0031], and Fig. 2 shows that the data blocks can be stored sequentially in a memory circuit (see data blocks 210a-210d storing in sequential addresses from 0x0100 to 0x0280). Biswas also provides that when sending commands, the commands storing portions of a same data block may be sent in parallel, [0046], where parallel means at least overlapping in time, see [0047].
An obvious modification can be identified: incorporating Biswas’ disclosure of MFG’s for the destination locations of a data transaction, with MFG’s containing multiple commands, and where MFG’s are stored in sequentially addressable sections of memory circuits. Such a modification reads upon where the received memory request targets a portion of a given memory fetch granule identifying a sequentially addressable portion of memory having a size corresponding to an access granularity (see Fig. 1, with memory block 130a being split into portions a, b, c, d, see also [0046]), as well as where the plurality of memory requests correspond to the memory fetch granule, and where the sending of memory requests provides a sequential access pattern, as Biswas [0046,0047] teaches sending memory requests directed to the same MFG together as well as where Fig. 2 shows that the data blocks contain sequential regions, reading on the sequential access pattern.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Biswas’ MFG disclosures into Tripathi’s memory system, as the MFG and ability to break up data blocks into different memory commands/circuits, as the ability to break up a data stream into MFG’s allows for distribution of data blocks across memory circuits based on a utilization of the communication channel, see [0027].
Regarding claim 22, the combination of Tripathi and Biswas teaches the apparatus as recited in claim 21, wherein the given memory fetch granule comprises a programmable amount of data that corresponds to a plurality of memory requests (as seen in the claim 21 rationale, Biswas provides for breaking up data block 130a into components a, b, c, d, see also “Memory Controller 120 generates four memory commands for sending four parts of Data Block 130b (parts labeled “e,” “f,” “g,” and “h”). Each part of Data Block 130b may correspond to an amount of data to be sent to a particular memory bank in Memory Circuit 155b, such as, for example, an amount of data to fill a page of a memory bank,” [0030]).
Regarding claim 23, the combination of Tripathi and Biswas teaches the apparatus as recited in claim 22, wherein the circuitry is configured to delay forwarding of memory requests corresponding to the given memory fetch granule until all memory requests corresponding to the given memory fetch granule have been received (“The aggregate logic 422 may monitor the number of stored requests and compare the number to the stored threshold. Alternatively, the aggregate logic 422 may monitor an amount of freed storage space, convert the amount of storage to a number of memory read requests, and compare the number to the stored threshold. In response to determining the number of memory read requests reaches the threshold and an aggregate condition is satisfied, such as a system idle state, then the aggregate logic 422 may submit to an arbiter the respective pipeline as a candidate for submitting requests. Alternatively, the aggregate logic 422 may allow the fetch unit 412 to present memory read requests to the interface 450, which causes the pipeline 410a to become a candidate for arbitration. Until a given threshold is reached, the respective pixel-processing pipeline may not send any requests to the memory controller or an indication as a candidate for arbitration to the arbitration logic,” [0066]; “ One or more requestors in the system may have a programmable aggregate threshold of the number of stored memory read requests to send to the memory controller. The threshold may be a relatively large number, thereby delaying when memory requests may be sent to the memory controller. In one example, during the system idle state, the large aggregate threshold delays when a display controller sends memory read requests to the memory controller. This appreciable delay allows the memory subsystem to spend a longer duration in a low-power mode,” [0075]).
Regarding claim 24, the combination of Tripathi and Biswas teaches the apparatus as recited in claim 21, and Tripathi further teaches wherein the circuitry is configured to forward all memory requests corresponding to the memory fetch granule on the path to the memory controller responsive to the first received memory request winning arbitration amongst a plurality of pending memory requests (“A source among the sources 140a-140b and the source 170 may send queued memory read requests uninterrupted to the shared resource 110 through the controller 120, in response to: the source is in an aggregate mode, the selected source reaches the given threshold of a number of queued requests, and the source is selected by arbitration logic. In various embodiments, no arbitration may occur while the selected source sends its queued requests. In some embodiments, the selected source may send a request that is generated after winning arbitration and before sending a last request stored in the request queue,” [0030]; in combination with the Fig. 6 discussion in the claim 21 rationale, once a source is selected, it will send until the last memory access request to send is reached).
Regarding claim 25, the combination of Tripathi and Biswas teaches the apparatus as recited in claim 24, and Tripathi further teaches wherein responsive to the first received memory request winning arbitration, memory requests other than memory requests corresponding to the memory fetch granule are not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been forwarded (“A source among the sources 140a-140b and the source 170 may send queued memory read requests uninterrupted to the shared resource 110 through the controller 120, in response to: the source is in an aggregate mode, the selected source reaches the given threshold of a number of queued requests, and the source is selected by arbitration logic. In various embodiments, no arbitration may occur while the selected source sends its queued requests. In some embodiments, the selected source may send a request that is generated after winning arbitration and before sending a last request stored in the request queue,” [0030], where the uninterrupted sending reads upon where other memory request are not eligible to win arbitration).
Regarding claim 26, the combination of Tripathi and Biswas teaches the apparatus as recited in claim 24, and Tripathi teaches wherein the first received memory request is not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been received (“The aggregate logic 422 may monitor the number of stored requests and compare the number to the stored threshold. Alternatively, the aggregate logic 422 may monitor an amount of freed storage space, convert the amount of storage to a number of memory read requests, and compare the number to the stored threshold. In response to determining the number of memory read requests reaches the threshold and an aggregate condition is satisfied, such as a system idle state, then the aggregate logic 422 may submit to an arbiter the respective pipeline as a candidate for submitting requests. Alternatively, the aggregate logic 422 may allow the fetch unit 412 to present memory read requests to the interface 450, which causes the pipeline 410a to become a candidate for arbitration. Until a given threshold is reached, the respective pixel-processing pipeline may not send any requests to the memory controller or an indication as a candidate for arbitration to the arbitration logic,” [0066]).
Regarding claim 27, the combination of Tripathi and Biswas teaches the apparatus as recited in claim 21, and Tripathi further teaches wherein the circuitry is configured to accumulate memory requests targeting a memory until a sum of sizes of data referenced by the accumulated memory requests satisfy a threshold corresponding to the memory fetch granule (“The display controller 262 may include an arbiter for selecting a given request to send to the memory interface 210 through the fabric 230. The selected request may be from multiple requests generated by the display pipelines within the display controller 262. Alternatively, each display pipeline may include an arbiter for selecting a given request from multiple requests generated by multiple internal pixel-processing pipelines. Memory access requests may be stored in a request queue. The display controller 262 may include request aggregate logic. Alternatively, one or more of the display pipelines within the display controller 262 may include request aggregate logic. The aggregate logic may prevent a given one of the display pipelines or a given one of the internal pixel-processing pipelines from being a candidate for arbitration. In some embodiments, a display pipeline or an internal pixel-processing pipeline may not be a candidate for arbitration until the number of stored requests reaches a given threshold. In other embodiments, the display pipeline or the internal pixel-processing pipeline may not be a candidate for arbitration until the amount of storage space for subsequent response data reaches a given threshold. The threshold may be measured as a corresponding number of memory read requests. The given threshold may be a programmable number stored in a configuration register. Until the given threshold is reached, a corresponding arbiter may not use the associated pipeline source as a candidate for selecting requests to send to the fabric 230. In some embodiments, the aggregate logic is not used until an aggregate condition is satisfied. For example, the idle pause in user activity may be one condition,” [0048]).
Claim 29 is noted to be rejected under 35 U.S.C. 112(d) as failing to further limit claim 21 from which it depends, and as such can be rejected according to the same rationale of claim 21.
Claim 30 recites a method identical to the functional limitations of the circuitry of claim 21 and can therefore be rejected according to the same rationale of claim 21. Examiner notes for clarity of record that the rationale of claim 21 addresses all limitations, including the contingent limitation of claim 30. However, as one of the limitations is identified as contingent, examiner notes that any argument addressing the contingent limitation in claim 21 will not necessarily apply to claim 30, as the contingent limitation is not required within the broadest reasonable interpretation of the claim.
Claims 31-36 are rejected according to the same rationale of claims 22-27.
Claims 33 and 34 are noted to be rejected under 35 U.S.C. 112(d), so they can also be rejected according to the same rationale of claim 30.
Regarding claim 37, Tripathi teaches a system (Fig. 2, apparatus 200) comprising:
a first memory controller comprising circuitry configured to access a memory device (Fig. 2, memory controllers 212a and 212b, where “Each of the memory channels 220a-220d may be a separate interface to a memory, such as SDRAM. The memory controllers 212a-212b may include request queues for queuing memory requests. The memory controllers 212a-212b may also include logic for supporting a given protocol used to interface to the memory channels 220-220d,” [0042]); and
a communication fabric comprising a plurality of agents (Fig. 2, fabric 230 and display controller 262, with the fabric providing an interconnect for requestors, see [0035] and aggregating traffic for the system, see [0036], with the requestors being one of the multiple IC designs on the apparatus, including the processors, see [0035,0036], the requestors being an agent), wherein one or more agents of the plurality of agents comprise circuitry identical to the circuitry of claim 21 (control logic in display controller, see [0011]) and rejected according to the same rationale.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Tripathi in view of Biswas and further in view of Kazakov (US 2018/0018097).
The combination of Tripathi and Biswas teaches the apparatus as recited in claim 21, and the combination further teaches wherein the circuitry is configured to identify a memory request as the last memory request corresponding to the memory fetch granule (Tripathi Fig. 6 shows a number of ways through which the arbitration process can determine that a memory request is the last one to be accessed; Biswas’ disclosure breaks up the data blocks into component memory requests, and as they are sequentially addressed, can identify the last one based on the address).
The combination fails to teach where the identification of the last memory request is based on a tag associated with the last memory request.
Kazakov’s disclosure relates to processing a batch of memory requests, and as such comprises analogous art in the area of command processing.
As part of this disclosure, Kazakov provides for a batch identifier that can also serve as a delimiter, inserted before a first memory request of a batch and after the last memory request of each batch, see [0029,0065].
An obvious modification can be identified: incorporating Kazakov’s batch identifier tokens to serve to determine the start of a new batch/end of a previous batch of previous memory requests. Such a modification reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Kazakov’s batch token into Tripathi’s arbitration system, as this can help increase performance boosts, see [0021] and providing a single token to identify a batch of commands may reduce the bandwidth consumption, see [0029].
Claims 38 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Tripathi in view of Biswas and further in view of Lee et al. (US 5,799,203).
Regarding claim 38, the combination of Tripathi and Biswas teaches the system as recited in claim 37, but fails to teach wherein the one or more agents are configured to store an indication of a size of the memory fetch granule.
Lee’s disclosure relates to a computing system featuring processors/memories processing requests, and as such comprises analogous art in the same field of endeavor of memory command processing.
As part of this disclosure, Lee provides for memory controllers providing information about the underlying memory, including capacity, speed, width, burst length, which can go to a support logic, and then to a CPU, see Col. 4, Lines 6-33.
An obvious modification can be identified: incorporating Lee’s disclosure of having memory controllers provide memory sizes, including cache line size, to a requesting CPU into Tripathi’s system as modified by Biswas. Such a modification reads upon the limitation of the claim, as the processors store the memory information, where this information is utilized in Biswas to identify memory fetch granule sizes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Lee’s ability for a memory controller to provide memory information to a system and processors, as this helps optimize system performance, see Col. 1, Lines 49-58.
Regarding claim 39, the combination of Tripathi, Biswas, and Lee teaches the system as recited in claim 38, wherein the first memory controller is configured to convey the indication of the size to the agent (as discussed in the claim 38 rationale, Lee provides for the underlying memory controllers to provide the CPU with the memory configuration information, reading on this claim, see Lee Col. 4, Lines 6-33).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21, 23-25, 27-30, and 32-34 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 16, and 17 of U.S. Patent No. US 11,467,988
Claims 22, 26, 31, and 35 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 11,467,988 in view of Tripathi and Biswas.
Claims 37-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16, 19, and 20 of U.S. Patent No. US 11,467,988 in view of Tripathi.
For the purpose of comparison, only the apparatus and system claim sets are compared, as the method claims are largely identical to the apparatus claims (see the prior art rejection), with the exception of different statutory categories, and the broader scope due to contingent limitations. As such, addressing the apparatus claims will necessarily satisfy the broader method claims.
For the purpose of clarity, the instant application claims are presented with limitations in order as recited, and patented limitations may be moved around as needed.
Claim 21, instant application
Claim 16, US 11,467,988
An apparatus, comprising:
circuitry configured to:
forward a received memory request on a path to a memory controller, the received memory request targeting a portion of a given memory fetch granule identifying a sequentially addressable portion of memory having a size corresponding to an access granularity;
if the received memory request is not a last memory request of a plurality of received memory requests corresponding to the given memory fetch granule, continue sending individual ones of the plurality of received memory requests to provide a sequential access pattern on the path to the memory controller until all of the plurality of received memory requests corresponding to the given memory fetch granule have been forwarded on the path to the memory controller.
A system comprising:
a first arbiter … wherein the first arbiter is configured to:
forward the given memory request of the given memory fetch granule to the first memory controller … (accumulate memory requests having a sequential access pattern which target the first memory… wherein the first memory fetch granule specifies an access granularity for the first memory…)
if the given memory request is not the last memory request of the given memory fetch granule, …continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
Claim 23, instant application
Claim 16, US 11,467,988
The apparatus as recited in claim 22, wherein the circuitry is configured to delay forwarding of memory requests corresponding to the given memory fetch granule until all memory requests corresponding to the given memory fetch granule have been received.
…wherein the first arbiter is configured to: accumulate real-time requests from the first agent targeting the first memory coupled to the first memory controller until a sum of sizes of data referenced by the memory requests satisfies the first memory fetch granule size threshold
Claim 24, instant application
Claim 16, US 11,467,988
The apparatus as recited in claim 21, wherein the circuitry is configured to forward all memory requests corresponding to the memory fetch granule on the path to the memory controller responsive to the received memory request winning arbitration amongst a plurality of pending memory requests.
…wherein the first arbiter is configured to:
determine if a given memory request, selected as a winner of arbitration, is a last memory request of a given memory fetch granule; and if the given memory request is not the last memory request of the given memory fetch granule, forward the given memory request of the given memory fetch granule to the first memory controller and continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
Claim 25, instant application
Claim 17, US 11,467,988
The apparatus as recited in claim 24, wherein responsive to the received memory request winning arbitration, memory requests other than memory requests corresponding to the memory fetch granule are not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been forwarded.
The system as recited in claim 16, wherein after forwarding the given memory request on the path to the first memory controller, the first arbiter is configured to prevent memory requests of other memory fetch granules from being eligible for arbitration until the entirety of the given memory fetch granule has been forwarded on the path to the first memory controller.
Claim 27, instant application
Claim 16, US 11,467,988
The apparatus as recited in claim 21, wherein the circuitry is configured to accumulate memory requests targeting a memory until a sum of sizes of data referenced by the memory requests satisfy a threshold corresponding to the memory fetch granule.
Wherein the first arbiter is configured to….
accumulate real-time requests from the first agent targeting the first memory coupled to the first memory controller until a sum of sizes of data referenced by the memory requests satisfies the first memory fetch granule size threshold
Claim 28, instant application
Claim 2, US 11,467,988
The apparatus as recited in claim 21, wherein the circuitry is configured to identify a memory request as the last memory request corresponding to the memory fetch granule based on a tag associated with the last memory request.
wherein the first agent is further configured to: tag, with an end of memory fetch granule flag, a last memory request in a group of memory requests based on the group of memory requests haaving a sequential access pattern and the sum of sizes of data referenced by the group satisfying the first memory fetch granule size threshold
Claim 29, instant application
Claim 16, US 11,467,988
The apparatus as recited in claim 21, wherein the memory requests corresponding to the given memory fetch granule identify sequential physical addresses.
accumulate memory requests having a sequential access pattern which target the first memory coupled to the first memory controller
Claim 37, instant application
Claim 16, US 11,467,988
A system comprising:
a first memory controller comprising circuitry configured to access a memory device; and
a communication fabric comprising a plurality of agents, wherein one or more agents of the plurality of agents comprise circuitry configured to:
forwarding a memory request for a portion of a given memory fetch granule on a path to the first memory controller, the received memory request targeting a portion of a given memory fetch granule identifying a sequentially addressable portion of memory having a size corresponding to the access granularity; and
if the memory request is not a last memory request of a plurality of received memory requests corresponding to the given memory fetch granule, continue sending, by circuitry of the one or more agents, individual ones of the plurality of received memory requests corresponding to the given memory fetch granule to provide a sequential access pattern on the path to the first memory controller until all memory requests corresponding to the given memory fetch granule have been forwarded.
A system comprising:
a first memory controller configured to:
define a first memory fetch granule for the one or more agents to use when forwarding real-time memory requests which target first memory coupled to the first memory controller, wherein the first memory fetch granule specifies an access granularity for the first memory;
one or more agents; a first arbiter… the first arbiter configured to:
forward the given memory request of the given memory fetch granule to the first memory controller … (accumulate memory requests having a sequential access pattern which target the first memory… wherein the first memory fetch granule specifies an access granularity for the first memory…)
if the given memory request is not the last memory request of the given memory fetch granule, …continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
Claim 38, instant application
Claim 19, US 11,467,988
The system as recited in claim 37, wherein the one or more agents is configured to store an indication of a size of the memory fetch granule.
The system as recited in claim 16, wherein the first agent is further configured to store the indication of the size of the first memory fetch granule in a memory fetch granule table.
Claim 39, instant application
Claim 16, US 11,467,988
The system as recited in claim 38, wherein the first memory controller is configured to convey the indication of the size to the agent.
The first memory controller configured to: convey an indication of a size of the first memory fetch granule to the one or more agents and the first arbiter;
Claim 40, instant application
Claim 20, US 11,467,988
The system as recited in claim 38, further comprising a second memory controller, wherein the one or more agents are configured to store a size of a memory fetch granule corresponding to the second memory controller that is different from that of the size of the memory fetch granule corresponding to the first memory controller.
The system as recited in claim 19, wherein the first agent is further configured to store, in the memory fetch granule table, a plurality of indications of sizes of a plurality of different memory fetch granules corresponding to different memory controllers.
Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reasons:
Claims 21-36 differ from patented claims 16-20 in a different statutory category. However, this is seen as an obvious variant, and claims 21-29 in particular recite an apparatus with broader circuitry than the circuitry of patented claims 16-20.
For claims 22, 26, 31, and 35, these features are taught by the combination of Tripathi and Biswas, as seen in the obviousness rationale above.
For claim 37, it is noted that the patented claims do not teach the communication fabric; however this is taught in Tripathi as discussed in the prior art rejection, and it would have been obvious to one of ordinary skill in the art to incorporate Tripathi’s communication fabric into the patented system, as the communication fabric allows for communication between elements of a computing system.
Prior Art Comments
Claim 40 does not feature prior art rejections.
Claims 40 recites the system of claim 38 further comprising a second memory controller, wherein the one or more agents are configured to store a size of a memory fetch granule corresponding to the second memory controller that is different from that of the size of the memory fetch granule corresponding to the first memory controller.
The claims are currently rejected primarily on a combination of Tripathi and Biswas. Of note is that Biswas discloses that the data blocks/MFG’s have a common size, see [0044,0051]. As such, while Tripathi does disclose providing multiple memory controllers, an obvious modification does not appear that would render the feature of claim 40 obvious where different size memory fetch granules are indicated.
Response to Arguments
Applicant's arguments filed February 34, 2026 have been fully considered and are moot in part and unpersuasive in part.
New rejections under 35 U.S.C. 112 are provided that were not previously provided. In addition, while Tripathi, Kazakov, and Lee have been previously relied upon, a new obviousness rationale incorporating Biswas is presented in this action, so the arguments are moot in part for lack of opportunity to address the new reference and rationale.
The arguments are unpersuasive in part for lack of failure to address the double patenting rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Blankenship (US 2003/0204679) discusses processing write requests directed to memory granules.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
