Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendment filed 03 July 2025 and the supplemental amendment filed 08 August 2025. The Examiner notes that Applicant has not address the objection to the abstract set forth in the Office Action mailed 03 April 2025.
The prior double patenting rejection has been updated to address the amended claim limitations.
The prior 112(b) rejection has been withdrawn based on the amendments to the claims 28 and 39. New rejections under 112(a) (written description) and 112(b) have been added based on the amended language in claims 21, 30, and 37.
The prior 102 rejection has been overcome by the amendment to claims 21, 30, and 37. New 102 and 103 rejections have been provided addressing the amended claims.
Drawings
The drawings are objected to because in figure 6, block 615, the “No” and “Yes” designations appear to be at the incorrect locations. At paragraph [0045], lines 2-7, the “no” leg of conditional block 615 is sent to block 620 and the “yes” leg goes to block 625. However in figure 6, the “no” leg goes to block 625 and the “yes” leg goes to block 620. The specification appears to be correct.
In a similar manner, in figure 6, block 630, the “No” and “Yes” designations appear to be at the incorrect locations. At paragraph [0045], lines 7-10, the “yes” leg of conditional block 630 is sent to block 620 and at paragraph [0046] the “no” leg is sent to block 635. However in figure 6, the “yes” leg goes to block 635 and “no” goes to block 620. The specification appears to be correct.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because the abstract exceeds 150 words in length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 37-40 are objected to because of the following informalities:
In claim 37, lines 7-8, “first” should be added before “memory controller”.
In claim 37, line 15, “the agent” should be “the one or more agents”.
In claim 38, line 1, “the agent” should be “the one or more agents”.
In claim 40, line 2, “the agent” should be “the one or more agents”.
All dependent claims are objected to as having the same deficiencies as the claims they depend from.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 24, 25, 27, 30, 33, 34, 36-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16, 17, 19, and 20 of U.S. Patent No. US 11,467,988 B1 in view of Jakowski et al. (US 2018/0089088).
Instant Application 17/932983
US Patent (US 11,467,988 B1)
(Claim 21) An apparatus comprising circuitry configured to: forward a received memory request on a path to a memory controller; and if the received memory request
(Claim 16) wherein the first arbiter is configured to: … and if the given memory request is not the last memory request of the given memory fetch granule, forward the given memory request of the given memory fetch granule to the first memory controller and continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
(Claim 24) wherein the circuitry is configured to forward all memory requests corresponding to the memory fetch granule on the path to the memory controller responsive to the received memory request winning arbitration amongst a plurality of pending memory requests.
(Claim 16) … determine if a given memory request, selected as a winner of arbitration, is a last memory request of a given memory fetch granule; and
if the given memory request is not the last memory request of the given memory fetch granule, forward the given memory request of the given memory fetch granule to the first memory controller and continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
(Claim 25) wherein responsive to the received memory request winning arbitration, memory requests other than memory requests corresponding to the memory fetch granule are not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been forwarded.
(Claim 17) wherein after forwarding the given memory request on the path to the first memory controller, the first arbiter is configured to prevent memory requests of other memory fetch granules from being eligible for arbitration until the entirety of the given memory fetch granule has been forwarded on the path to the first memory controller.
(Claim 27) wherein the circuitry is configured to accumulate memory requests targeting a memory until a sum of sizes of data referenced by the memory requests satisfy a threshold corresponding to the memory fetch granule.
(Claim 16) … accumulate memory requests having a sequential access pattern which target the first memory coupled to the first memory controller until a sum of sizes of data referenced by the memory requests satisfies a first memory fetch granule size threshold; …
(Claim 30) A method comprising: forwarding, by circuitry, a received memory request on a path to a memory controller; and if the received memory request is not a last memory request corresponding to a given memory fetch granule, continue sending, by the circuitry, memory requests corresponding to the given memory fetch granule on the path to the memory controller until all memory requests corresponding to the given memory fetch granule have been forwarded.
(Claim 16) wherein the first arbiter is configured to: … and if the given memory request is not the last memory request of the given memory fetch granule, forward the given memory request of the given memory fetch granule to the first memory controller and continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
(Claim 33) further comprising forwarding the received memory request on the path to the memory controller, responsive to the received memory request winning arbitration amongst a plurality of pending memory requests.
(Claim 16) … determine if a given memory request, selected as a winner of arbitration, is a last memory request of a given memory fetch granule; and
if the given memory request is not the last memory request of the given memory fetch granule, forward the given memory request of the given memory fetch granule to the first memory controller and continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
(Claim 34) wherein responsive to the received memory request winning arbitration, memory requests other than memory requests corresponding to the memory fetch granule are not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been forwarded on the path to the memory controller.
(Claim 17) wherein after forwarding the given memory request on the path to the first memory controller, the first arbiter is configured to prevent memory requests of other memory fetch granules from being eligible for arbitration until the entirety of the given memory fetch granule has been forwarded on the path to the first memory controller.
(Claim 36) further comprising accumulating memory requests targeting a memory until a sum of sizes of data referenced by the memory requests satisfy a threshold corresponding to the memory fetch granule.
(Claim 16) … accumulate memory requests having a sequential access pattern which target the first memory coupled to the first memory controller until a sum of sizes of data referenced by the memory requests satisfies a first memory fetch granule size threshold; …
(Claim 37) A system comprising:
a first memory controller comprising circuitry configured to access a memory device; and
a communication fabric comprising a plurality of agents, wherein one or more agents of the plurality of agents comprise circuitry configured to: forwarding a memory request on a path to the first memory controller; and
if the memory request is not a last memory request corresponding to a given memory fetch granule, continue sending, by circuitry of the agent,
memory requests corresponding to the given memory fetch granule on the path to the first memory controller until all memory requests corresponding to the given memory fetch granule have been forwarded.
(Claim 16) A system comprising:
one or more agents;
a first arbiter; and
a first memory controller configured to: define a first memory fetch granule for the one or more agents to use when forwarding real-time memory requests which target first memory coupled to the first memory controller, wherein the first memory fetch granule specifies an access granularity for the first memory; …
send the memory requests to the first memory controller based at least in part on the sum of the sizes of data referenced by the memory requests satisfying the first memory fetch granule size threshold; wherein the first arbiter is configured to: … if the given memory request is not the last memory request of the given memory fetch granule, forward the given memory request of the given memory fetch granule to the first memory controller and continue sending other memory requests of the given memory fetch granule as credits become available until an entirety of the given memory fetch granule has been forwarded on a path to the first memory controller.
(Claim 38) The system as recited in claim 37, wherein the agent is configured to store an indication of a size of the memory fetch granule.
(Claim 16) a first memory controller configured to: … convey an indication of a size of the first memory fetch granule to the one or more agents and the first arbiter; and wherein a first agent, of the one or more agents, is configured to: receive the indication of the size of the first memory fetch granule;
(Claim 19) wherein the first agent is further configured to store the indication of the size of the first memory fetch granule in a memory fetch granule table.
(Claim 39) wherein the first memory controller is configured to convey an indication of the size to the agent.
(Claim 16) a first memory controller configured to: … convey an indication of a size of the first memory fetch granule to the one or more agents and the first arbiter;
(Claim 40) further comprising a second memory controller, wherein the agent is configured to store a size of a memory fetch granule corresponding to the second memory controller that is different from that of the size of the memory fetch granule corresponding to the first memory controller.
(Claim 20) wherein the first agent is further configured to store, in the memory fetch granule table, a plurality of indications of sizes of a plurality of different memory fetch granules corresponding to different memory controllers.
With respect to the amended limitations, the ‘988 patent teaches a “sequential access pattern”, but does not specify an “access granularity greater than one cache line”. Jakowski et al. teaches that the “given memory fetch granule” is the total number of blocks and metadata created in the buffer and sent to the NVM cache (see paragraph [0045]), and that this combination of blocks and metadata is greater than one cache line (see paragraph [0045], lines 23-25, and paragraph [0068], lines 3-4; “access granularity greater than one cache line”). Jakowski et al. also teaches the sequential access pattern as outlined in the 102 rejection herein. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an access granule greater than one cache line and to access based on a sequential access pattern because this would provide an improved technique for managing data and metadata.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claims 21, 30, and 37, the claims have been amended to set forth “the memory controller is configured to provide bounded latency access to a memory according to a sequential access pattern and an access granularity greater than one cache line”. However, the limitation “to provide bounded latency access to a memory according to a sequential access pattern and an access granularity greater than one cache line” does not appear to be supported in the original specification.
In the remarks submitted on 08 August 2025, at page 6, Applicant indicates support for the amendments can be found in paragraphs [0003], [0004], and [0007]. Paragraphs [0003] and [0004] are directed to the related art (background of the invention) and describe “Quality of Service” (QoS) as “a set of mechanisms for guaranteeing fabric, memory controller, and memory bandwidth over a bounded and pre-defined period of time” (paragraph [0003]) and “Real-time (RT) traffic has a stringent requirement where [a] required amount of bandwidth should be guaranteed with bounded latency to prevent failures…” (paragraph [0004]). In addition to being a description of the “related art”, neither paragraph describes how a memory controller of the present invention “is configured to provide bounded latency access to a memory according to a sequential access pattern and an access granularity greater than one cache line” as set forth in the independent claims.
Paragraph [0007] of the original specification describes that “RT agents shall access data at a granularity larger than a cache line”, however the paragraph does not describe how “a memory controller is configured to provide bounded latency access to a memory according to a sequential access pattern and an access granularity greater than one cache line” (emphasis added).
It is not clear where the present specification provides support for “a memory controller is configured to provide bounded latency access to a memory according to a sequential access pattern and an access granularity greater than one cache line” (emphasis added).
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 21, 30, and 37, it is not clear whether the amended language “to provide bounded latency” is intended use or meant to specify a limitation that further limits the claim. If the language is setting forth an intended use of “configuring”, then a question of the limiting effect of the language is raised (see MPEP 2103(I)(C)). If the language is meant to further be further limiting, it is not clear how “[providing] bounded latency access” is achieved “according to a sequential access pattern and an access granularity greater than one cache line”.
For purposes of applying prior art the Office will assume that the language “to provided bounded latency” is intended use and is met when a memory controller provides access to a memory according to a sequential access pattern and an access granularity greater than one cache line”.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-23, 27, 30-32, and 36-37 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jakowski et al. (US 2018/0089088 A1).
As per claim 21, Jakowski et al. teaches a process performed by the cache manager 104 and cache driver 122 to cache dirty blocks of data for storage 116 in NVM cache 114 (“forward a received memory request…on a path to a memory controller [“NVM controller 130”]). See paragraph [0045]. A block of data (“portion of a given memory fetch granule”) is added to a buffer (figure 9, step 904) and metadata is added to the block to create a block of second size (figure 9, step 906).
If the received memory block is not a last memory request, then process 904-908 (figure 9) are repeated until all the dirty blocks are processed. See paragraph [0045] (“if the received memory request is not a last memory request corresponding to the given memory fetch granule, continue sending memory requests corresponding to the given memory fetch granule on the path to the memory controller until all memory requests corresponding to the given memory fetch granule has been forwarded on the path to the memory controller”).
It is noted that the “given memory fetch granule” is the total number of blocks and metadata created in the buffer and sent to the NVM cache (see paragraph [0045]), and that this combination of blocks and metadata is greater than one cache line (see paragraph [0045], lines 23-25, and paragraph [0068], lines 3-4; “access granularity greater than one cache line”). It is further noted that data written is a contiguous second size with a logical start address and a number of addresses to write (see paragraph [0045], lines 5-7, 10-11, and 26-28; “according to a sequential access pattern…granule is sequentially addressed portion of memory having a size corresponding to the access granularity”).
The added limitation of “configured to provide bounded latency” is being treated as intended use and is met when a memory controller provides access to a memory “according to a sequential access pattern and an access granularity greater than one cache line”, which Jakowski et al. does as outlined above.
Claim 30 is rejected for the same reasons as claim 21.
Claim 37 is rejected for the same reasons as claim 21, noting the “NVM controller 130” represents the claimed “first memory controller configured to access a memory device” (i.e. storage die 132 with cache 112). Interface 118 represents the claimed “communication fabric” with processor 102 and main memory 110 representing the claimed “one or more agents of the plurality of agents”. See figure 1 and paragraphs [0026]-[0031].
As per claims 22 and 31, Jakowski et al. teaches that a plurality of dirty blocks are operated on for the process set forth in figure 9 (paragraph [0045], “a plurality of memory requests”). At some point a developer inherently had to program the amount of data to be gathered in the buffer to create the “memory fetch granule”. It is noted that Applicant has not specified, in the claim, how the “granule” is “programmable” or when the memory requests were made, or their relationship to the “received memory request” in claims 22 or 31.
As per claims 23 and 32, in figure 9 of Jakowski et al. it is taught that system does not write the second sized blocks until all blocks are processed (“all memory requests…have been received”). See step 910 which loops back to step 902 until all blocks are processed.
As per claims 27 and 36, in figure 9 of Jakowski et al. it is taught that system does not write the second sized blocks until all blocks are processed (“all memory requests…have been received”). See step 910 which loops back to step 902 until all blocks are processed (“satisfy a threshold corresponding to the memory fetch granule”, where the threshold is number of dirty blocks to be processed).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24-26, and 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Jakowski in view of Tripathi (US 2014/0071140 A1).
As per claim 24, Jakowski et al. does not teach “wherein the circuitry is configured to forward all memory requests corresponding to the memory fetch granule on the path to the memory controller responsive to the received memory request winning arbitration amongst a plurality of pending memory requests.”. However, Tripathi teaches including multiple sources accessing a memory and arbitrating for access amongst plural requests (¶0030 A source among the sources 140a-140b and the source 170 may send queued memory read requests uninterrupted to the shared resource 110 through the controller 120, in response to: the source is in an aggregate mode, the selected source reaches the given threshold of a number of queued requests, and the source is selected by arbitration logic. ... In some embodiments, the selected source may send a request that is generated after winning arbitration and before sending a last request stored in the request queue.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Jakowski et al. to include multiple sources and to arbitrate for access amongst multiple memory requests, as suggested by Tripathi. The modification would be obvious because one of ordinary skill in the art would be motivated to provide an expanded capability of increased functionality by adding multiple sources of processing data and the system of Tripathi would provide an efficient method for scheduling memory access requests (see paragraph [0010] of Tripathi).
With regards to claim 25, Tripathi teaches “wherein responsive to the received memory request winning arbitration, memory requests other than memory requests corresponding to the memory fetch granule are not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been forwarded.” (¶0030 A source among the sources 140a-140b and the source 170 may send queued memory read requests uninterrupted to the shared resource 110 through the controller 120, in response to: the source is in an aggregate mode, the selected source reaches the given threshold of a number of queued requests, and the source is selected by arbitration logic. In various embodiments, no arbitration may occur while the selected source sends its queued requests. In some embodiments, the selected source may send a request that is generated after winning arbitration and before sending a last request stored in the request queue.)
With regards to claim 26, Tripathi teaches “wherein the received memory request is not eligible to win arbitration until all memory requests corresponding to the memory fetch granule have been received”. (¶0066 The aggregate logic 422 may monitor the number of stored requests and compare the number to the stored threshold. Alternatively, the aggregate logic 422 may monitor an amount of freed storage space, convert the amount of storage to a number of memory read requests, and compare the number to the stored threshold. … Until a given threshold is reached, the respective pixel-processing pipeline may not send any requests to the memory controller or an indication as a candidate for arbitration to the arbitration logic.; Fig. 6 shows that there would be a delay waiting for "the last memory access request to send" in element 612 if burst mode is off and aggregate mode is off. Until the "last memory access request to send" is received the system does not begin arbitration for requestors again.)
Claim 33 is essentially the same as claim 24 except that the claim is directed to a method instead of the apparatus in claim 21. Claim 33 is therefore rejected under the same rationale as applied to claim 24 above.
Claim 34 is essentially the same as claim 25 except that the claim is directed to a method instead of the apparatus in claim 21. Claim 34 is therefore rejected under the same rationale as applied to claim 25 above.
Claim 35 is essentially the same as claim 26 except that the claim is directed to a method instead of the apparatus in claim 21. Claim 35 is therefore rejected under the same rationale as applied to claim 26 above.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Jakowski et al. in view of Kazakov (US 2018/0018097).
With regards to claim 28, Jakowski et al. teaches wherein the circuitry is configured to identify a memory request as a last memory request corresponding to the memory fetch granule …
Jakowski does not teach:
… based on a tag associated with the last memory request.
However, Kazakov does teach:
… based on a tag associated with the last memory request. (¶0065 FIG. 6 illustrates an ... The batch start identifier may be tagged to the last memory request of the batch such that the batch start identifier is positioned after the last memory request when stored in the conflict arbitration queue and serve as a batch delimiter.; ¶0083 In some examples, ... For example, processing unit 1 may be configured to sequentially release memory requests on a per-batch basis by checking for batch delimiters in the conflict arbitration queue. In such an example, processing unit 1 may be configured to sequentially release memory requests of a batch from the conflict arbitration queue until the submit pointer reaches a batch delimiter (e.g., a batch start identifier).)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus disclosed by Jakowski et al. to have a tag associated with the last memory request using the teaching of Kazakov. The modification would be obvious because one of ordinary skill in the art would be motivated to provide a performance boost, enable more memory requests to be queued, and increase the bandwidth. (¶0021 In general, this … One or more techniques described herein may increase memory request execution parallelism and memory latency hiding, thereby providing a performance boost. For example, one or more techniques described herein enable more memory requests to be in flight to a memory or a memory controller by exploiting the absence of inter-group (e.g., inter-wave) and inter-thread dependencies according to APIs (e.g., GPU APIs). ¶0029 Processing unit 1 may … By tagging the batch of memory requests or only the first memory request in the batch of memory requests, processing unit 1 may be configured to reduce the consumption of bandwidth by not tagging each memory request in a batch of memory requests with the metadata.)
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Jakowski et al. in view of Wu (US 2006/0143426).
Jakowski teaches consecutive logical addresses as detailed above for claim 21. Jakowski doesn’t specifically teach that the consecutive logical addresses map to consecutive (“sequential”) physical addresses as set forth in claim 29. Wu teaches that consecutive virtual (“logical”) addresses are mapped to sequential physical addresses. See the abstract and paragraph [0036]. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus disclosed by Jakowski et al. to have consecutive logical addresses map to consecutive physical addresses, as taught by Wu, because Wu teaches at paragraph [0036] that this manner of filling blocks with data units results in less erasing of the block (thereby saving time and improving system efficiency).
Claims 38-39 are rejected under 35 U.S.C. 103 as being unpatentable over Jakowski et al. in view of Lee (US Patent 5799203).
With regards to claims 38-39, Jakowski et al. does not teach that the agent (processor or main memory) stores an indication of a size of the memory fetch granule and memory controller conveys the indication of the size to the agent.
However Lee teaches a cache controller providing information regarding memory capacity and memory width (“memory fetch granule” size) [claim 38] which can be provided to system support, then to a CPU [claim 39]. See column 4, lines 6-33.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Jakowski to have the NVM cache controller provide a size of the fetch granule to the process using the teaching of Lee. The modification would be obvious because one of ordinary skill in the art would be motivated to allow for optimizing of system performance by providing a processor with configuration information. See column 1, lines 49-58, of Lee.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of prior art rejection has been set forth addressing the amended claim language.
Prior Art Remarks
No prior art has been applied to claim 40, however the claim is rejected under 112(a), 112(b) and double patenting.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Reginald G. Bragdon whose telephone number is (571)272-4204. The examiner can normally be reached M-Th 6:30am-4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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