DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-20 are pending; claims 1, 8 and 15 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114 was filed in this application on 01/28/2026 after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action.
Response to Arguments
4. Applicant's arguments filed 01/28/2026 have been fully considered but they are not persuasive.
In response to applicant's arguments that “Park is absent any teaching or suggestion of supplying a variable ELVDD as a function of display brightness value (DBV) to maintain a constant ELVDD voltage over a range of digital dimming and calibrated brightness levels, as recited in amended claim 1” against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant's arguments that Zhang fails to cure the deficiencies of Park. While Examiner relies on Zhang to allegedly teach the features of using the interpolations between taps, Applicant respectfully submits Zhang is absent any teaching or suggestion of setting of taps adjacent to either side of a step discontinuity and generating interpolations, as well as the use of the interpolations to compensate for brightness or color temperature of the display panel to maintain a constant ELVDD voltage over a range of digital dimming and calibrated brightness levels as recited in amended claims 1, 8 and 15
However, the examiner respectfully disagrees, Park as a primary reference taught in figs 7-13 and Paras 0083-0087, wherein the method of correction for different positions like the first to third display areas 1, 2, and 3. The problem of luminance differences can be solved by correcting the bit value of a subframe for each position on the display panel 150 when supplying a high-potential voltage, varying between different levels during 1 frame, commonly to the display panel 150. In other words, luminance differences within the same subframe can be compensated for by varying the bit value of the subframe for each position on the display panel 150.
Zhang clearly taught in fig. 20 and Paras 0144-0149, wherein a current-voltage curve 270 interpolated from the set of current and voltage values (e.g., 272) with various brightness settings, according to an embodiment of the present disclosure. A first portion of the current-voltage curve 270, from V.sub.G1 274 to V.sub.DBV1 276 may correspond to a first brightness setting. V.sub.G1 274 may correspond to a voltage level that, when supplied to a pixel 65 at the first brightness setting, emits a gray level 1.In fig. 30 and Para 0172, the brightness setting 540 (e.g., display brightness value (DBV)) changes (e.g., from DBV1, to DBV2, to DBV3, to DBV4), the ELVSS voltage value 542 (e.g., ELVSS0) remains constant.
In response to applicant's arguments “Zhang is absent any teaching or suggestion of setting of taps adjacent to either side of a step discontinuity and generating interpolations” against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
For the reasons above rejection to claims 2-7, 9-14 and 16-20 still stands.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, recited “generate interpolations interpolate…”, line 17, should be change to “generate interpolations .
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2015/0187280), and further in view of Zhang (US 2019/0088205).
Regarding claims 1 and 8, Park teaches an electronic apparatus (fig. 7, an organic electroluminescence display), a method of operating an electronic apparatus (Paras 0003 and 0011) comprising:
a display panel (fig. 7 and the display panel 150);
a power management subsystem (fig. 7 and the power supply 160) configured to supply a variable electroluminescence voltage (ELVDD) to the display panel, the power management subsystem configured to supply a first ELVDD step voltage at a lower and a second ELVDD step voltage at a higher, wherein a first ELVDD step voltage discontinuity exists between the first ELVDD step voltage and the second ELVDD step voltage (fig. 10 and Paras 0077-0082, wherein a high-potential voltage, varying between different levels during 1 frame, was supplied to the display panel 150 through the first power line ELVDD);
a display driver integrated circuit configured to place at least two taps at each brightness level, the placing including: adding a first tap adjacent to the first ELVDD step discontinuity on the first ELVDD step, adding a second tap adjacent to the first ELVDD step discontinuity on the second ELVDD step voltage (fig. 13 and Paras 0083-0087, wherein the method of correction for different positions like the first to third display areas 1, 2, and 3. The problem of luminance differences can be solved by correcting the bit value of a subframe for each position on the display panel 150 when supplying a high-potential voltage, varying between different levels during 1 frame, commonly to the display panel 150);
Park does not expressly disclose a variable electroluminescence voltage (ELVDD) as a function of display brightness value (DBV) and the display driver circuit is further configured to: interpolate generate interpolations between taps on the at least two taps at each brightness level, and use the interpolations to compensate for brightness or color temperature of the display panel to maintain a constant ELVDD voltage over a range of digital dimming and calibrated brightness levels.
However, Zhang discloses “interpolate generate interpolations between taps on the at least two taps at each brightness level, and use the interpolations to compensate for brightness or color temperature of the display panel to maintain a constant ELVDD voltage over a range of digital dimming and calibrated brightness levels”, see fig. 20, Paras 0144-0149, fig. 30 and Para 0172.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified an electronic apparatus and a method of Park with incorporated the teaching of Zhang to include an interpolation technique from a current-voltage curve interpolated from the set of current and voltage values with various brightness settings in order to get a predictable result.
Regarding claims 2 and 9, Park in view of Zhang teaches the electronic apparatus of claim 1 and the electronic method of claim 8, wherein the power management system is further configured to supply a third ELVDD step voltage at a third brightness level of the display panel, wherein a second ELVDD step voltage discontinuity exists between the second ELVDD step voltage and the third ELVDD step voltage (fig. 10 and Paras 0077-0082, Park ).
Regarding claims 3 and 10, Park in view of Zhang teaches the electronic apparatus of claim 2 and the electronic method of claim 9, wherein the placing further includes: adding a third tap adjacent to the second ELVDD step discontinuity on the second ELVDD step voltage; adding a fourth tap adjacent to the second ELVDD step continuity on the third ELVDD step voltage (fig. 13 and Paras 0083-0087, Park).
Regarding claims 4 and 11, Park in view of Zhang teaches the electronic apparatus of claim 1 and the electronic method of claim 8, wherein the display driver integrated circuit further comprises a look-up-table to interpolate between the taps on the same ELVDD step (figs 31-33, LUT 582 and Paras 0177-0181, Zhang).
Regarding claims 5 and 12, Park in view of Zhang teaches the electronic apparatus of claim 3 and the electronic method of claim 10, wherein the display driver integrated circuit further comprises a look-up-table to interpolate between the taps on the same ELVDD step (figs 31-33, LUT 582 and Paras 0177-0181, Zhang).
Regarding claims 6 and 13, Park in view of Zhang teaches the electronic apparatus of claim 4 and the electronic method of claim 11, wherein the display panel is a light- emitting diode (LED) or liquid crystal display (LCD) display (Para 0087, LED display, Zhang).
Regarding claims 7 and 14, Park in view of Zhang teaches the electronic apparatus of claim 4 and the electronic method of claim 11, wherein the display panel is an organic light-emitting diode (OLED) display (figs 1, 2, an organic light emitting diode OLED and Para 0042, Park).
Regarding claims 15, Park teaches an instructions causing the electronic apparatus to: supplying a variable electroluminescence voltage (ELVDD) to the display panel, the power management subsystem configured to supply a first ELVDD step voltage at a lower and a second ELVDD step voltage at a higher, wherein a first ELVDD step voltage discontinuity exists between the first ELVDD step voltage and the second ELVDD step voltage (fig. 10 and Paras 0077-0082, wherein a high-potential voltage, varying between different levels during 1 frame, was supplied to the display panel 150 through the first power line ELVDD);
place at least two taps at each ELVDD step with a display driver integrated circuit, the placing including: adding a first tap adjacent to the first ELVDD step discontinuity on the first ELVDD step, adding a second tap adjacent to the first ELVDD step continuity on the second ELVDD step voltage (fig. 13 and Paras 0083-0087, wherein the method of correction for different positions like the first to third display areas 1, 2, and 3. The problem of luminance differences can be solved by correcting the bit value of a subframe for each position on the display panel 150 when supplying a high-potential voltage, varying between different levels during 1 frame, commonly to the display panel 150);
Park does not expressly disclose a variable electroluminescence voltage (ELVDD) as a function of display brightness value (DBV) and a non-transitory computer readable medium encoded with data and instructions and the display driver integrated circuit is further configured to: generate interpolations between taps on the at least two taps at each brightness level, and use the interpolations to compensate for brightness or color temperature of the display panel over a range of digital dimming and calibrated brightness levels.
However, Zhang discloses “a non-transitory computer readable medium encoded with data and instructions and the display driver integrated circuit is further configured to: generate interpolations between taps on the at least two taps at each brightness level, and use the interpolations to compensate for brightness or color temperature of the display panel over a range of digital dimming and calibrated brightness levels”, see fig. 20, Paras 0085, 0144-0149, fig. 30 and Para 0172.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified an electronic apparatus of Park with incorporated the teaching of Zhang to include an interpolation technique from a current-voltage curve interpolated from the set of current and voltage values with various brightness settings in order to get a predictable result.
Regarding claims 16, Park in view of Zhang teaches the non-transitory computer readable medium of claim 15, wherein the data instructions further cause the electronic apparatus to: supplying a third ELVDD step voltage at a third brightness level of the display panel with the power management system, wherein a second ELVDD step voltage discontinuity exists between the second ELVDD step voltage and the third ELVDD step voltage (fig. 10 and Paras 0077-0082, Park).
Regarding claims 17, Park in view of Zhang teaches the non-transitory computer readable medium of claim 16, wherein the data instructions further cause the electronic apparatus to: add a third tap adjacent to the second ELVDD step discontinuity on the second ELVDD step voltage; add a fourth tap adjacent to the second ELVDD step continuity on the third ELVDD step voltage (fig. 13 and Paras 0083-0087, Park).
Regarding claims 18, Park in view of Zhang teaches the non-transitory computer readable medium of claim 15, the display driver integrated circuit further comprises a look-up-table to interpolate between the taps on the same ELVDD step (figs 31-33, LUT 582 and Paras 0177-0181, Zhang).
Regarding claims 19, Park in view of Zhang teaches the non-transitory computer readable medium of claim 17, the display driver integrated circuit further comprises a look-up-table to interpolate between the taps on the same ELVDD step (figs 31-33, LUT 582 and Paras 0177-0181, Zhang).
Regarding claims 20, Park in view of Zhang in view of Zhang teaches the non-transitory computer readable medium of claim 18, wherein the display panel is an organic light-emitting diode (OLED) display (figs 1, 2, an organic light emitting diode OLED and Para 0042, Park).
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A. Shikata (US 11,151,941), relates to a device and method for controlling a display panel. A display driver includes signal supply circuitry and a power source controller. The signal supply circuitry is configured to update a display panel during a refresh period and not update the display panel during a non-refresh period that follows the refresh period.
B. Kornienko (US 11,094,038), relates generally to image processing and, more particularly, to the scaling image data used to display images on an electronic display at multiple different scaling ratios.
C. Aflattooni (US 2016/0284275), relates generally to electronic displays and, more particularly, to compensating for voltage degradation in an electronic display with voltage-driven pixels and/or current-driven.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.E/Examiner, Art Unit 2625 3/4/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625