DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/20/2022 and 08/26/2025 was filed after the mailing date of the non-final action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ihara (US 2015/0243694 A1) in view of Togashi (US 20160204156 A1).
Re claim 1: Ihara teaches (fig.15) An image sensor, comprising: a substrate (3) that includes a trench (52) that defines a plurality of pixel regions (UP);
and a deep isolation pattern (11a) provided between the pixel regions (UP) and in the trench (52),
wherein the deep isolation pattern (11a) comprises:
a first insulating liner pattern (left half of 23, hereinafter 23L) disposed on a first inner side surface (left side of 52 hereinafter SSL) of the trench (52);
a second insulating liner pattern (right half of 23, hereinafter 23R) disposed on a second inner side surface (right side of 52, hereinafter SSR) of the trench (52);
a first lower insulating pattern (7a on left side of 52 hereinafter 7aL) disposed on a lower inner side surface (left surface under 23L hereinafter LSS) of the first insulating liner pattern (23L);
a second lower insulating pattern (7a on right side of 52 hereinafter 7aR) disposed on a lower inner side surface of the second insulating liner pattern (right side under 23R, hereinafter RSS);
an isolation pattern (25 and middle portion of 23 on surface 52x, hereinafter IP) provided between the first (7aL) and second (7aR) lower insulating patterns and that extends through the substrate (backside of 3, par.53);
Ihara is silent to teach a first air gap region that is a space enclosed by the first insulating liner pattern, the first lower insulating pattern, and the isolation pattern; and a second air gap region that is a space enclosed by the second insulating liner pattern, the second lower insulating pattern, and the isolation pattern.
Togashi teaches (fig.1) a first air gap region (70 on left side, hereinafter 70L) that is a space enclosed by the first insulating liner pattern (25A/B on left side hereinafter 25L), the first lower insulating pattern (lower portion of film 24 on left side hereinafter 24L), and the isolation pattern (25);
and a second air gap region (70 on right side, hereinafter 70R) that is a space enclosed by the second insulating liner pattern (25A/B on right side hereinafter 25R), the second lower insulating pattern (lower portion of film 24 on right side hereinafter 24R), and the isolation pattern (25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first and second air gap regions of Togashi in the device of Ihara in order to have the predictable result of reducing capacitance generated between an electrode and the semiconductor substrate thereby enhancing conversion efficiency as well as suppressing lag (persistence). (par.69 of Togashi)
Re claim 2: Ihara in view of Togashi teaches the image sensor of claim 1, wherein the first lower insulating pattern (7aL of Ihara) exposes an upper inner side surface of the first insulating liner pattern (23L of Ihara), and the second lower insulating pattern (7aR) exposes an upper inner side surface of the second insulating liner pattern (23R).
Re claim 6. Ihara in view of Togashi teaches the image sensor of claim 1,
Ihara in view of Togashi is silent to explicitly teach wherein a height of the first lower insulating pattern is between 5% and 20% of a height of the deep isolation pattern, and a height of the second lower insulating pattern is between 5% and 20% of a height of the deep isolation pattern.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the height of the first and second lower insulating patterns between 5% and 20% of a height of the deep isolation pattern depending on the spec requirements for the device for isolation requirements during manufacturing.
Re claim 10: Ihara in view of Togashi teaches the image sensor of claim 1, wherein the first (23L of Ihara) and second (23R of Ihara) insulating liner patterns comprise a same material (metal oxides, par. 51 of Ihara), the first (7aL of Ihara) and second (7aR of Ihara) lower insulating patterns comprise a same material (same throughout as shown in fig.15 of Ihara) and the material of the first (23L of Ihara) and second (23R of Ihara) insulating liner patterns differs (23L/R are metal oxides while 7aL/R of Ihara are not) from the material of the first (7aL of Ihara)and second (7aR of Ihara) lower insulating patterns.
Claims 3-5,7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ihara (US 2015/0243694 A1) in view of Togashi (US 20160204156 A1) and Adkisson (US 2007/0187734 A1) as applied to claim 1.
Re claim 3: Ihara in view of Togashi teaches the image sensor of claim 1, wherein the isolation pattern (IP of Ihara) comprises:
and a capping insulating pattern (25 of Ihara) disposed on the semiconductor gap-fill pattern (9a of Ihara) and that fills a remaining portion of the trench (52 of Ihara);
Ihara in view of Togashi is silent to teach a semiconductor liner pattern that conformally covers a bottom surface of the trench (52 of Ihara), an inner side surface of the first lower insulating pattern (7aL of Ihara), and an inner side surface of the second lower insulating pattern (7aR of Ihara);
a semiconductor gap-fill pattern (9a of Ihara) that covers inner side surfaces of the semiconductor liner pattern;
Adkisson teaches (fig.2) a semiconductor liner pattern (118) surrounding a p-type polysilicon filled layer (121)
Ihara in view of Togashi and Adkisson teaches a semiconductor liner pattern (118 of Adkisson would be around 9a of Ihara) that conformally covers a bottom surface of the trench (52 of Ihara), an inner side surface of the first lower insulating pattern (7aL of Ihara), and an inner side surface of the second lower insulating pattern (7aR of Ihara);
a semiconductor gap-fill pattern (9a of Ihara) that covers inner side surfaces of the semiconductor liner pattern (118 of Adkisson);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the semiconductor liner pattern 118 of Adkisson around the polysilicon pattern 9a of Ihara in order to have the predictable result of further isolating the n-type regions of the photodiode from the trench walls and substrate surface and ultimately improve current performance of the device. (par.48 of Adkisson)
Re claim 4: Ihara in view of Togashi and Adkisson teaches the image sensor of claim 3, wherein the semiconductor gap-fill pattern (9a of Ihara) comprises poly silicon (par.70 of Ihara), and the semiconductor liner pattern (118 of Adkisson) comprises poly silicon doped par. 30 of Adkisson) with p-type impurities.
Re claim 5: Ihara in view of Togashi and Adkisson teaches the image sensor of claim 3, wherein the capping insulating pattern (25 of Ihara is silicon oxide par.53) comprises a material that differs from that of the semiconductor liner pattern (118 of Adkisson is p-doped polysilicon par.30) and the semiconductor gap-fill pattern (9a of Ihara).
Re claim 7: Ihara in view of Togashi teaches the image sensor of claim 1, wherein the isolation pattern (IP of Ihara) comprises:
and a capping insulating pattern (25 of Ihara) disposed on the semiconductor gap-fill pattern (9a of Ihara) and that fills a remaining portion of the trench (52 of Ihara);
Ihara in view of Togashi is silent to teach a semiconductor liner pattern that conformally covers a bottom surface of the trench (52 of Ihara), an inner side surface of the first lower insulating pattern (7aL of Ihara), and an inner side surface of the second lower insulating pattern (7aR of Ihara);
a semiconductor gap-fill pattern (9a of Ihara) that covers inner side surfaces of the semiconductor liner pattern;
Adkisson teaches (fig.2) a semiconductor liner pattern (118) surrounding a p-type polysilicon filled layer (121)
Ihara in view of Togashi and Adkisson teaches a semiconductor liner pattern (118 of Adkisson would be around 9a of Ihara) that conformally covers a bottom surface of the trench (52 of Ihara), an inner side surface of the first lower insulating pattern (7aL of Ihara), and an inner side surface of the second lower insulating pattern (7aR of Ihara);
a semiconductor gap-fill pattern (9a of Ihara) that covers inner side surfaces of the semiconductor liner pattern (118 of Adkisson);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the semiconductor liner pattern 118 of Adkisson around the polysilicon pattern 9a of Ihara in order to have the predictable result of further isolating the n-type regions of the photodiode from the trench walls and substrate surface and ultimately improve current performance of the device. (par.48 of Adkisson)
Re claim 8: Ihara in view of Togashi and Adkisson teaches the image sensor of claim 7, wherein an upper width (as shown in fig. 15 of Ihara) of the capping insulating pattern (25) is greater than a lower width of the capping insulating pattern (25).
Re claim 9: Ihara in view of Togashi and Adkisson teaches the image sensor of claim 7, wherein the semiconductor liner pattern (118 of Adkisson) is spaced apart (118 of Adkisson would be directly on 9a of Ihara) from the first insulating liner pattern (23L of Ihara) by the first lower insulating pattern (7aL of Ihara) and the first air gap region (70L of Togashi), and the semiconductor liner pattern (118 of Adkisson) is spaced apart from the second insulating liner pattern (23R of Ihara) by the second lower insulating pattern (7aR of Ihara) and the second air gap region (70R of Togashi).
Claims 11-14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ihara (US 2015/0243694 A1) in view of Togashi (US 20160204156 A1) and Adkisson (US 2007/0187734 A1).
Re claim 11: Ihara teaches (fig.15) An image sensor, comprising:
a substrate (3) that includes a plurality of pixel regions (UP), wherein the substrate (3) includes a trench (52) that defines the pixel regions (UP);
and a deep isolation pattern (11a) provided between the pixel regions (UP) and in the trench (52), wherein the deep isolation pattern (11a) comprises:
a first insulating liner pattern (left half of 23, hereinafter 23L) disposed on a first inner side surface (left side of 52 hereinafter SSL) of the trench (52);
a second insulating liner pattern (right half of 23, hereinafter 23R) disposed on a second inner side surface (right side of 52, hereinafter SSR) of the trench (52);
a first lower insulating pattern (7a on left side of 52 hereinafter 7aL) disposed on a lower inner side surface (left surface under 23L hereinafter LSS) of the first insulating liner pattern (23L);
a second lower insulating pattern (7a on right side of 52 hereinafter 7aR) disposed on a lower inner side surface of the second insulating liner pattern (right side under 23R, hereinafter RSS);
Ihara is silent to teach a semiconductor liner pattern provided between the first (7aL) and second (7aR) lower insulating patterns and spaced apart from the first (23L) and second (23R) insulating liner patterns;
Adkisson teaches (fig.2) a semiconductor liner pattern (118) surrounding a p-type polysilicon filled layer (121)
Ihara in view of Adkisson teaches a semiconductor liner pattern (118 of Adkisson would be around 9a of Ihara) provided between the first (7aL of Ihara) and second (7aR of Ihara) lower insulating patterns and spaced apart from the first (23L of Ihara) and second (23R of Ihara) insulating liner patterns;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the semiconductor liner pattern 118 of Adkisson around the polysilicon pattern 9a of Ihara in order to have the predictable result of further isolating the n-type regions of the photodiode from the trench walls and substrate surface and ultimately improve current performance of the device. (par.48 of Adkisson)
Ihara in view of Adkisson is silent to teach a first air gap region that is a space enclosed by the first insulating liner pattern, the first lower insulating pattern, and the isolation pattern; and a second air gap region that is a space enclosed by the second insulating liner pattern, the second lower insulating pattern, and the isolation pattern.
Togashi teaches (fig.1) a first air gap region (70 on left side, hereinafter 70L) that is a space enclosed by the first insulating liner pattern (25A/B on left side hereinafter 25L), the first lower insulating pattern (lower portion of film 24 on left side hereinafter 24L), and the isolation pattern (25);
and a second air gap region (70 on right side, hereinafter 70R) that is a space enclosed by the second insulating liner pattern (25A/B on right side hereinafter 25R), the second lower insulating pattern (lower portion of film 24 on right side hereinafter 24R), and the isolation pattern (25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first and second air gap regions of Togashi in the device of Ihara in view of Adkisson in order to have the predictable result of reducing capacitance generated between an electrode and the semiconductor substrate thereby enhancing conversion efficiency as well as suppressing lag (persistence). (par.69 of Togashi)
Re claim 12: Ihara in view of Togashi and Adkisson teaches the image sensor of claim 11, wherein a top surface of the first lower insulating pattern (7aL of Ihara) is located (as shown in fig.15) at a lower level than a top surface of the first insulating liner pattern (23L of Ihara) and an uppermost surface of the semiconductor liner pattern (118 of Adkisson), and a top surface of the second lower insulating pattern (7aR of Ihara) is located at a lower level than a top surface of the second insulating liner pattern (23R of Ihara) and the uppermost surface of the semiconductor liner pattern (118 of Adkisson).
Re claim 13: Ihara in view of Togashi and Adkisson teaches the image sensor of claim 11, further comprising: a semiconductor gap-fill pattern (9a of Ihara) that covers inner side surfaces of the semiconductor liner pattern (118 of Adkisson); and a capping insulating pattern (13 of Ihara) disposed on the semiconductor gap-fill pattern (9a of Ihara) and that fills a remaining portion of the trench (52 of Ihara).
Re claim 14: : Ihara in view of Togashi and Adkisson teaches the image sensor of claim 13, wherein a top surface of the semiconductor gap-fill pattern (9a of Ihara) is coplanar (as shown in fig.2 of Adkisson) with an uppermost surface of the semiconductor liner pattern (118 of Adkisson).
Re claim 16. Ihara in view of Togashi and Adkisson teaches the image sensor of claim 11, further comprising a capping insulating pattern (25 of Ihara) disposed on the semiconductor liner pattern (118 of Adkisson) and that fills a remaining portion of the trench (52 of Ihara).
Re claim 17. Ihara in view of Togashi and Adkisson teaches the image sensor of claim 16, wherein the capping insulating pattern (25 of Ihara) comprises an oxide (13 can be same material as 7 which can be an oxide par. 59 of Ihara).
Re claim 18. Ihara teaches an image sensor, comprising:
a substrate (3), wherein the substrate (3) includes a first surface (Bottom surface) and a second surface (Top surface) that are opposite to each other, a plurality of pixel regions (UP), a first trench (51) that is recessed from the first surface (bottom surface) of the substrate (3), and a second trench (52) that defines the plurality of pixel regions (UP);
a shallow isolation pattern (FD and 13) disposed in the first trench (51);
a deep isolation pattern (11a) provided between the pixel regions (UP) and in the second trench (52);
a transistor (15) disposed on the first surface (bottom surface) of the substrate (3);
a micro lens (31) disposed on the second surface (top surface) of the substrate (3);
and color filters (29) interposed between the substrate (3) and the micro lens (31) and disposed on the pixel regions (UP), respectively, wherein the deep isolation pattern (11a) comprises:
a first insulating liner pattern (left half of 23, hereinafter 23L) disposed on a first inner side surface (left side of 52 hereinafter SSL) of the trench (52);
a second insulating liner pattern (right half of 23, hereinafter 23R) disposed on a second inner side surface (right side of 52, hereinafter SSR) of the trench (52);
a first lower insulating pattern (7a on left side of 52 hereinafter 7aL) disposed on a lower inner side surface (left surface under 23L hereinafter LSS) of the first insulating liner pattern (23L);
a second lower insulating pattern (7a on right side of 52 hereinafter 7aR) disposed on a lower inner side surface of the second insulating liner pattern (right side under 23R, hereinafter RSS);
Ihara is silent to teach a semiconductor liner pattern provided between the first (7aL) and second (7aR) lower insulating patterns and spaced apart from the first (23L) and second (23R) insulating liner patterns;
Adkisson teaches (fig.2) a semiconductor liner pattern (118) surrounding a p-type polysilicon filled layer (121)
Ihara in view of Adkisson teaches a semiconductor liner pattern (118 of Adkisson would be around 9a of Ihara) provided between the first (7aL of Ihara) and second (7aR of Ihara) lower insulating patterns and spaced apart from the first (23L of Ihara) and second (23R of Ihara) insulating liner patterns;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the semiconductor liner pattern 118 of Adkisson around the polysilicon pattern 9a of Ihara in order to have the predictable result of further isolating the n-type regions of the photodiode from the trench walls and substrate surface and ultimately improve current performance of the device. (par.48 of Adkisson)
Ihara in view of Adkisson is silent to teach a first air gap region that is a space enclosed by the first insulating liner pattern, the first lower insulating pattern, and the isolation pattern; and a second air gap region that is a space enclosed by the second insulating liner pattern, the second lower insulating pattern, and the isolation pattern.
Togashi teaches (fig.1) a first air gap region (70 on left side, hereinafter 70L) that is a space enclosed by the first insulating liner pattern (25A/B on left side hereinafter 25L), the first lower insulating pattern (lower portion of film 24 on left side hereinafter 24L), and the isolation pattern (25);
and a second air gap region (70 on right side, hereinafter 70R) that is a space enclosed by the second insulating liner pattern (25A/B on right side hereinafter 25R), the second lower insulating pattern (lower portion of film 24 on right side hereinafter 24R), and the isolation pattern (25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first and second air gap regions of Togashi in the device of Ihara in view of Adkisson in order to have the predictable result of reducing capacitance generated between an electrode and the semiconductor substrate thereby enhancing conversion efficiency as well as suppressing lag (persistence). (par.69 of Togashi)
Allowable Subject Matter
Claim 15 and 19-20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Ihara, Togashi, and Adkisson fail to teach the limitation of claim 15 “wherein the capping insulating pattern (13 of Ihara) is in contact with the semiconductor liner pattern (118 of Adkisson) and the gap-fill pattern (9a of Ihara)”
Ihara, Togashi, and Adkisson fail to teach the limitation of claim 19, “wherein a bottom surface of the deep isolation pattern (11a of Ihara) is coplanar with the second surface (top surface of 3 of Ihara) of the substrate (3 of Ihara).”
Ihara, Togashi, and Adkisson fail to teach the limitation of claim 20, “wherein an upper portion of the semiconductor liner pattern (118 of Adkisson) has a width that decreases in a direction toward the first surface of the substrate”
Conclusion
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/RICKY VERDES/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898