DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings The drawings are objected to for lacking suitable descriptive legends in letters, English alphabet . See 37 CFR 1.84 (o). Descriptive legends are being required by Examiner for figure 2, reference designators 110, 205, 210, 215, 225, 110, 230, 245, 250, 270, 275, 280. Suitable Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Claim 20 limitation means for processing, and the means for processing and executing instructions is being interpreted under 35 USC 112f. In review of the specification the structure for the means for processing and executing instructions is being interpreted as a processing circuit , combination of hardware, firmware, and software, employed to process data or digital signals, ASIC, general purpose or special purpose CPU, DSP, GPU, programmable logic device such as FPGA including input and output connections and equivalent. See [0046], fig 1 105. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1- 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Regarding claim 1 , under the Alice framework Step 1, the claim falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process , machine , manufacture or a composition of matter. Under the Alice framework Step 2A prong 1, the claim recites mathematical concepts of mathematical relationships and mental steps with respect to vectors . Specifically, claim 1 recites the following mathematical relationships and mental steps : forming a culled index vector comprising a first index, the first index being a first element of a first index vector, the first index being culled within the culled index vector; and requesting a weight vector corresponding to the first index. Forming the culled vector comprises a mathematical relationship of removing redundant elements in the index vector, which comprises the mathematical relationship of comparing values. Requesting a weight vector, without the limitation being required to be performed in a computer includes a request one might make to another person verbally or using pen and paper. For these reasons, claim 1 recites mathematical concepts and mental steps . Under the Alice framework Step 2A prong 2 analysis, and Step 2B analysis, the claim recites no additional elements that would require further analysis. For these reasons claim 1 is not integrated into a practical application, and does not amount to significantly more than the abstract idea. Claims 2-1 4 are rejected for at least the reasons set forth with respect to claim 1. Claims 2- 7 merely further mathematically limit the mathematical concepts , or further limit mental steps of claim 1. Claims 2- 7 contain no further additional elements beyond those recited in claim 1 that would require further analysis under step 2A prong 2 and step 2B. With respect to the claim 4 saving the first index and first hashed value in the hashed value table, this is a step that may be performed as a mental step using pen and paper. Regarding claim 8 , in addition to the mathematical concepts and mental steps recited in claim 1, claim 8 recites the following additional elements: wherein the requesting of the weight vector comprises performing a check, in cache, for the first index. Under the step 2A prong 2 analysis, this limitation comprises an insignificant extra solution activity. For these reasons, claim 8 is not integrated into a practical application. Under the step 2B analysis, the requesting the weight vector comprising performing a check in cache for the first index comprises well understood, routine and conventional activity. See e.g., D.A. Patterson et al., Computer Organization and Design: The Hardware/Software Interface , Elsevier Science & Technology, 2007 (hereinafter “Patterson”), which discloses that caches are typically used to access a memory hierarchy (p. 35, section 1.6 concluding remarks last sentence, see also p. 20 last paragraph). For these reasons, claim 8 does not amount to significantly more than the abstract idea. Regarding claim 9 , in addition to the mathematical concepts and mental steps recited in claim 8 , claim 9 recites the following additional elements: wherein the requesting of the weight vector further comprises, in response to a result of the check, reading, from the cache, a weight vector corresponding to the first index. Under the step 2A prong 2 analysis, th ese limitation s comprises an insignificant extra solution activity. For these reasons, claim 9 is not integrated into a practical application. Under the step 2B analysis, the reading from the cache comprises well understood, routine and conventional activity. See e.g., Patterson, which discloses that caches are typically used to access a memory hierarchy (p. 35, section 1.6 concluding remarks last sentence, see also p. 20 last paragraph). See also MPEP 2106.05(d).II.i. retrieving information is well understood, routine, and conventional activity . For these reasons, claim 9 does not amount to significantly more than the abstract idea. Regarding claim 10 , in addition to the mathematical concepts and mental steps recited in claim 9 , claim 10 recites the following additional elements: wherein: the performing of the check comprises performing the check by a first input-output thread and the reading from the cache comprises reading from the cache by the first input- output thread. Under the step 2A prong 2 analysis, these limitations comprises an insignificant extra solution activity. For these reasons, claim 10 is not integrated into a practical application. Under the step 2B analysis, the reading from the cache comprises well understood, routine and conventional activity. See e.g., Patterson, which discloses that caches are typically used to access a memory hierarchy (p. 35, section 1.6 concluding remarks last sentence, see also p. 20 last paragraph). See also MPEP 2106.05(d).II.i. retrieving information is well understood, routine, and conventional. Furthermore the performing the check and reading being by a first input-output thread comprises well understood, routine, and conventional activity. See e.g., J.L Hennessy et al., Computer Architecture: A quantitative approach , Elsevier Science & Technology, 2014 (hereinafter “Hennessy”), describing use of threads as one common approach in parallel processing (Section 6.1, p. 529-530). For these reasons, claim 10 does not amount to significantly more than the abstract idea. Regarding claim 11, in addition to mathematical concepts and mental steps recited in claim 8, claim 11 recites the following additional elements: wherein the requesting of the weight vector further comprises, in response to a result of the check, reading, from persistent storage, a weight vector corresponding to the first index. Under the step 2A prong 2 analysis, these limitations comprises an insignificant extra solution activity. For these reasons, claim 11 is not integrated into a practical application. Under the step 2B analysis, the reading from persistent storage comprises well understood, routine and conventional activity. See also MPEP 2106.05(d).II.i. retrieving information from memory is well understood, routine, and conventional activity . For these reasons, claim 11 does not amount to significantly more than the abstract idea. Regarding claim 1 2 , and claim 13 in addition to mathematical concepts and mental steps recited in claim 1 , claim 12 and claim 13 recite the following additional elements: wherein the forming of the culled index vector comprises forming the culled index vector by a persistent storage driver (claim 12); wherein the requesting of the weight vector comprises requesting the weight vector by the persistent storage driver (claim 13). Under the step 2A prong 2 analysis, these limitations comprises an insignificant extra solution activity. For these reasons, claim 12, and claim 13 are not integrated into a practical application. Under the step 2B analysis, the forming the culled index vector and the requesting the weight vector by the persistent storage driver comprises well understood, routine and conventional activity. See also MPEP 2106.05(d).II.i. retrieving information from memory is well understood, routine, and conventional. For these reasons, claim 1 2 and claim 13 do not amount to significantly more than the abstract idea. Regarding claim 1 4 in addition to mathematical concepts and mental steps recited in claim 1 2 , claim 1 4 recite s the following additional elements: wherein the persistent storage driver comprises a Nonvolatile Memory Express (NVME) driver . Under the step 2A prong 2 analysis, these limitations merely generally link to a particular technological environment . For these reasons, claim 1 4 is not integrated into a practical application. Under the step 2B analysis, the persistent storage driver comprises a Nonvolatile Memory Express (NVME) driver merely generally links the abstract idea to a particular technological environment. For these reasons, claim 14 do es not amount to significantly more than the abstract idea. Regarding claim 1 5 , under the Alice framework Step 1, the claim falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process , machine , manufacture or a composition of matter. Under the Alice framework Step 2A prong 1, the claim recites mathematical concepts of mathematical relationships and mental steps with respect to vectors. Specifically, claim 1 5 recites the following mathematical relationships and mental steps: forming a culled index vector comprising a first index, the first index being a first element of a first index vector, the first index being culled within the culled index vector; and requesting a weight vector corresponding to the first index. Under the step 2A prong 2 analysis, claim 1 5 recites the following additional elements: a system comprising a processing circuit; and memory, operatively connected to the processing circuit and storing instructions that, when executed by the processing circuit, cause the system to perform a method. Under the step 2A prong 2 analysis, merely recite the words “apply it” in a computer and merely include instructions to apply the abstract idea on a computer. For these reasons, claim 15 is not integrated into a practical application. Forming the culled vector comprises a mathematical relationship of removing redundant elements in the index vector, which comprises the mathematical relationship of comparing values. Requesting a weight vector, without the limitation being required to be performed in a computer includes a request one might make to another person verbally or using pen and paper. For these reasons, claim 1 recites mathematical concepts and mental steps. Under the Alice framework Step 2A prong 2 analysis, and Step 2B analysis, the claim recites no additional elements that would require further analysis. For these reasons claim 1 is not integrated into a practical application, and does not amount to significantly more than the abstract idea. Under the step 2B analysis, the analysis under step 2A prong 2 applies equally to step 2B. For these reasons, claim 1 5 does not amount to significantly more than the abstract idea. Claims 16-19 are rejected for at least the reasons set forth with respect to claim 1 5 . Claims 16-19 merely further mathematically limit the mathematical concepts, or further limit mental steps of claim 1 5 . Claims 16-19 contain no further additional elements beyond those recited in claim 1 5 that would require further analysis under step 2A prong 2 and step 2B. With respect to the claim 18 saving the first index and first hashed value in the hashed value table, this is a step that may be performed as a mental step using pen and paper. Regarding claim 20 , under the Alice framework Step 1, the claim falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process , machine , manufacture or a composition of matter. Under the Alice framework Step 2A prong 1, the claim recites mathematical concepts of mathematical relationships and mental steps with respect to vectors. Specifically, claim 20 recites the following mathematical relationships and mental steps: forming a culled index vector comprising a first index, the first index being a first element of a first index vector, the first index being culled within the culled index vector; and requesting a weight vector corresponding to the first index. Under the step 2A prong 2 analysis, claim 20 recites the following additional elements: a system comprising a means for processing; and memory, operatively connected to the means for processing and storing instructions that, when executed by the means for processing, cause the system to perform a method . Under the step 2A prong 2 analysis, merely recite the words “apply it” in a computer and merely include instructions to apply the abstract idea on a computer. For these reasons, claim 15 is not integrated into a practical application. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1-13 and 15- 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by M. Xie et al., Fleche: An Efficient GPU Embedding Cache for Personalized Recommendations , EuroSys ’22, ACM, 5-8 April 2022 , (hereinafter “ Xie ”) . Regarding claim 1, Xie teaches the following: forming a culled index vector comprising a first index, the first index being a first element of a first index vector, the first index being culled within the culled index vector (section 2.1, p. 404 left column, line 4-9, embedding vector (embedding for short) for index vector, section 4, 39-46, deduplicating for culled , ID for first index, ID deduplicated, fig 5 ) ; and r equesting a weight vector corresponding to the first index (section 2.1, p. 404 left column line 11-13 embedding lookup process for requesting a weight vector associated with the ID , fig 5a lookup process via query ) . Regarding claim 2 , in addition to the teachings addressed in the claim 1 analysis, Xie teaches the following: wherein the forming of the culled index vector comprises calculating a first hashed value, the calculating of the first hashed value comprising hashing the first element of the first index vector (section 3.1, p. 406 left column line 16 – right column 16, feature ID (hashed) bits ). Regarding claim 3 , in addition to the teachings addressed in the claim 2 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises performing a check for the first hashed value in a hashed values table (fig 5a section 3.3 p. 408 left column line 13-15, section 3.1, p. 405 right column) . Regarding claim 4 , in addition to the teachings addressed in the claim 3 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises, in response to a result of the check, saving the first index and the first hashed value in the hashed values table (secti o n 3.1 p. 406 right column, cache replacement & eviction section, query policy wherein embedding gets swapped into cache with a certain probability p, the check being the probability of the embedding cache hit, and being swapped in for saving the first index and the first hashed value in the hashed values table as in the previous claim mappings , done for embeddings missing from the table ) . Regarding claim 5, in addition to the teachings addressed in the claim 2 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises: performing a check for the first hashed value in a hashed values table (fig 5a section 3.3 p. 408 left column line 13-15, section 3.1, p. 405 right column) ; determining that the first hashed value is present in the hashed values table (section 3.3 p. 408 left column line 13-15 hit) ; calculating a second hashed value, the calculating of the second hashed value comprising hashing the first index (another thread, fig 5, fig 6, same search hash steps as with first hash) ; performing a check for the second hashed value in the hashed values table (another thread, fig 5, fig 6, same search hash steps as with first hash) ; and saving the first index and the second hashed value in the hashed values table (section 3.1 p. 406 left column lines 11-28, same ID one table) . Regarding claim 6 , in addition to the teachings addressed in the claim 2 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises calculating a second hashed value, the calculating of the second hashed value comprising hashing a second element of the first index vector ( another thread, fig 5, fig 6, same search hash steps as with first hash , section 3.1 p. 406 left column line 11 – right column line 11, reencode all features IDs to identify different embedding tables, features share the same table ID ) . Regarding claim 7 , in addition to the teachings addressed in the claim 6 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises performing a check for the second hashed value in the hashed values table (another thread, fig 5, fig 6, same search hash steps as with first hash) . Regarding claim 8 , in addition to the teachings addressed in the claim 1 analysis, Xie teaches the following: wherein the requesting of the weight vector comprises performing a check, in a cache, for the first index ( fig 5a section 3.3 p. 408 left column line 13-15, section 3.1, p. 405 right column ) . Regarding claim 9 , in addition to the teachings addressed in the claim 8 analysis, Xie teaches the following: wherein the requesting of the weight vector further comprises, in response to a result of the check, reading, from the cache, a weight vector corresponding to the first index ( fig 5a, section 2.1, p. 404 left column line 11-13 embedding lookup process for requesting a weight vector associated with the ID, fig 5a lookup process via query) . Regarding claim 10 , in addition to the teachings addressed in the claim 9 analysis, Xie teaches the following: the performing of the check comprises performing the check by a first input-output thread and the reading from the cache comprises reading from the cache by the first input-output thread (fig 5a section 3.3 p. 408 left column line 13-15, section 3.1, p. 405 right column , section checks and reading from cache by thread) . Regarding claim 1 1 , in addition to the teachings addressed in the claim 8 analysis, Xie teaches the following: wherein the requesting of the weight vector further comprises, in response to a result of the check, reading, from persistent storage, a weight vector corresponding to the first index ( fig 5c, memory pool, section 3.1 p. 406 right column line 17-20, missing embeddings swapped in from DRAM, section 1, p. 403 left column line 16-21 CPU-DRAM layer storing all embeddings) . Regarding claim 1 2 , in addition to the teachings addressed in the claim 1 analysis, Xie teaches the following: wherein the forming of the culled index vector comprises forming the culled index vector by a persistent storage driver (fig 5c, memory pool, section 3.1 p. 406 right column line 17-20, missing embeddings swapped in from DRAM , section 3.1, p. 405 right column line 37, slab memory allocator for persistent storage driver) . Regarding claim 1 3 , in addition to the teachings addressed in the claim 1 2 analysis, Xie teaches the following: wherein the requesting of the weight vector comprises requesting the weight vector by the persistent storage driver ( section 2.1, p. 404 left column line 11-13 embedding lookup process for requesting a weight vector associated with the ID, fig 5a lookup process via query , fig 5c, memory pool, section 3.1 p. 406 right column line 17-20, missing embeddings swapped in from DRAM, section 3.1, p. 405 right column line 37, slab memory allocator for persistent storage driver ) . Regarding claim 1 5 , Xie teaches the following: a system comprising: a processing circuit (Introduction, GPU , section 6.1 NVIDIA T4 GPU ) ; and memory, operatively connected to the processing circuit and storing instructions that, when executed by the processing circuit, cause the system to perform a method (section 6.1 NVIDIA T4 GPU, with 15 GB HBM), the method comprising: forming a culled index vector comprising a first index, the first index being a first element of a first index vector, the first index being culled within the culled index vector (section 2.1, p. 404 left column, line 4-9, embedding vector (embedding for short) for index vector, section 4, 39-46, deduplicating for culled, ID for first index, ID deduplicated, fig 5) ; and r equesting a weight vector corresponding to the first index (section 2.1, p. 404 left column line 11-13 embedding lookup process for requesting a weight vector associated with the ID, fig 5a lookup process via query) . Regarding claim 16 , in addition to the teachings addressed in the claim 1 5 analysis, Xie teaches the following: wherein the forming of the culled index vector comprises calculating a first hashed value, the calculating of the first hashed value comprising hashing the first element of the first index vector (section 3.1, p. 406 left column line 16 – right column 16, feature ID (hashed) bits). Regarding claim 17 , in addition to the teachings addressed in the claim 16 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises performing a check for the first hashed value in a hashed values table (fig 5a section 3.3 p. 408 left column line 13-15, section 3.1, p. 405 right column) . Regarding claim 18 , in addition to the teachings addressed in the claim 17 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises, in response to a result of the check, saving the first index and the first hashed value in the hashed values table (section 3.1 p. 406 right column, cache replacement & eviction section, query policy wherein embedding gets swapped into cache with a certain probability p, the check being the probability of the embedding cache hit, and being swapped in for saving the first index and the first hashed value in the hashed values table as in the previous claim mappings, done for embeddings missing from the table) . Regarding claim 19 , in addition to the teachings addressed in the claim 16 analysis, Xie teaches the following: wherein the forming of the culled index vector further comprises: performing a check for the first hashed value in a hashed values table (fig 5a section 3.3 p. 408 left column line 13-15, section 3.1, p. 405 right column) ; determining that the first hashed value is present in the hashed values table (section 3.3 p. 408 left column line 13-15 hit) ; calculating a second hashed value, the calculating of the second hashed value comprising hashing the first index (another thread, fig 5, fig 6, same search hash steps as with first hash) ; performing a check for the second hashed value in the hashed values table (another thread, fig 5, fig 6, same search hash steps as with first hash) ; and saving the first index and the second hashed value in the hashed values table (section 3.1 p. 406 left column lines 11-28, same ID one table) . Regarding claim 20 , Xie teaches the following: a system comprising: a means for processing (Introduction, GPU, section 6.1 NVIDIA T4 GPU ); and memory, operatively connected to the means for processing and storing instructions that, when executed by the means for processing , cause the system to perform a method (section 6.1 NVIDIA T4 GPU, with 15 GB HBM), the method comprising: forming a culled index vector comprising a first index, the first index being a first element of a first index vector, the first index being culled within the culled index vector (section 2.1, p. 404 left column, line 4-9, embedding vector (embedding for short) for index vector, section 4, 39-46, deduplicating for culled, ID for first index, ID deduplicated, fig 5) ; and r equesting a weight vector corresponding to the first index (section 2.1, p. 404 left column line 11-13 embedding lookup process for requesting a weight vector associated with the ID, fig 5a lookup process via query) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Cla im 14 is rejected unde r 35 U.S.C. 103 as being unpatentable over Xie in view o f NVMe Driver , documentation found at https://spdk.io/doc/nvme.html , 201 8 (hereinafter “ spdk ”) . Regarding claim 1 4 , Xie teaches the claim 13 limitations. Xie discloses a persistent storage driver, but does not explicitly disclose wherein the persistent storage driver comprises a Nonvolatile Memory Express (NVME) driver. However, in the same field of endeavor of storage systems, spdk discloses an NVMe driver for accessing memory (Introduction). It would have been obvious to one of ordinary skill in the art before the effective filing date for Xie to use the NVME driver disclosed by spdk as the persistent storage driver. It would have been obvious to achieve the benefit provided by the NVME driver of direct, zero-copy data transform (introduction). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. H.B McMahan et al., Ad click prediction: a view from the trenches , KDD ’13 Proceedings of the 19 th ACM SIGKDD international conference on Knowledge discovery and data mining, ACM 2014, discloses probabilistic feature inclusion in which new features are included in the model probabilistically as they first occur (section 4.1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT EMILY E LAROCQUE who se telephone number is FILLIN "Phone number" \* MERGEFORMAT (469)295-9289 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT 10:00am - 1200pm, 2:00pm - 8pm ET M-F . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Andrew Caldwell can be reached on 571-272- 3701 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILY E LAROCQUE/ Examiner, Art Unit 2182