DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
[0016], line 9: The phrase “also provide” is grammatically incorrect. Examiner recommends to change the phrase to “also provides”.
[0061], line 4: Remove the redundant phrase “a multimedia processing unit 410”.
Appropriate correction is required.
Claim Objections
Claims 1, 7, 17, 29, and 30 are objected to because of the following informalities:
Claim 1: The phrases “the selected at least the portion of the weight data” and “the selected at least the portion of the input data” is not concise and does not flow well. Examiner recommends that Applicant changes the “at least the portion” segment in each of the phrases.
Claims 17, 29, and 30 are objected for the same reasons as claim 1.
Claim 7 is objected to for inheriting the objection of claim 1.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 29 recites the following limitations:
“means for initializing at least a portion of weight data for a machine learning model in a nonvolatile random access memory (NVRAM) associated with a processor”. Examiner identifies the “means” of the limitation as a “weight data initializing component”, which is identified to provide the recited function as seen in paragraph [0043, 0074]. A “component” may be a processor (see [0103]). Since the limitation “initializing at least a portion of weight data” is read as storing data, where storing data is a coextensive function of a processor, special programming is not required (see MPEP 2181(II)(B)).
“means for storing input data in a dynamic random access memory (DRAM) coupled with the processor”. Examiner identifies the “means” of the limitation as an “input data storing component”, which is identified to provide the recited function as seen in paragraph [0044-0045, 0074]. A “component” may be a processor (see [0103]). Since storing data is a coextensive function of a processor, special programming is not required (see MPEP 2181(II)(B)).
“means for selecting, based on an asymmetry in access latency between the NVRAM and the DRAM, at least the portion of the weight data from the NVRAM and at least a portion of the input data from the DRAM to load into memory registers of the processor”. Examiner could not identify the “means” of the limitation within the specification or drawings. Therefore, Examiner will give the limitation the broadest reasonable interpretation.
“means for loading the selected at least the portion of the weight data from the NVRAM and the selected at least the portion of the input data from the DRAM into the memory registers of the processor”. Examiner could not identify the “means” of the limitation within the specification or drawings. Therefore, Examiner will give the limitation the broadest reasonable interpretation.
“means for writing a result of the operations in the DRAM”. Examiner identifies the “means” of the limitation as an “result storing component”, which is identified to provide the recited function as seen in paragraph [0052, 0074]. A “component” may be a processor (see [0103]). Since storing data is a coextensive function of a processor, special programming is not required (see MPEP 2181(II)(B)).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 29 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 29, as described below in the 112(b) rejection, the disclosure does not provide adequate structure to perform the claimed functions of “selecting, based on an asymmetry in access latency between the NVRAM and the DRAM, at least the portion of the weight data from the NVRAM and at least a portion of the input data from the DRAM to load into memory registers of the processor” and “loading the selected at least the portion of the weight data from the NVRAM and the selected at least the portion of the input data from the DRAM into the memory registers of the processor”. The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 29 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 29, the means-plus-function limitations of “means for selecting…” and “means for loading…” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed functions and does not provide sufficient details such that one of ordinary skill in the art would understand which structure(s) would perform the claimed functions. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Mathuriya et al (US 11836102 B1) in view of Jiang (US 20200134433 A1) and Maiyuran et al. (US 20030229762 A1).
Ali “Artificial Neural Network (ANN) with Practical Implementation” (See Non-Final Office Action mailed February 6, 2026) is cited as extrinsic evidence to indicate that the AI training performed in Mathuriya is for an ANN model.
Wikipedia “Application-specific integrated circuit” (See Non-Final Office Action mailed February 6, 2026) is cited as extrinsic evidence to indicate that ASICs are processors for specific applications.
Hasan et al. "Bridging the Latency Gap between NVM and DRAM for Latency- bound Operations" (See Non-Final Office Action mailed February 6, 2026) is cited as extrinsic evidence to indicated a latency difference between non-volatile memory and dynamic RAM.
Regarding claim 1, Mathuriya teaches a computer-implemented method, the method comprising:
initializing at least a portion of weight data for a machine learning model in a non-volatile random access memory (NVRAM) associated with a processor (Figs. 1, 4, and 5, Col 19, line 60 to Col. 20, line 14: Weight buffer 501a can be implemented as FE-RAM, which is a type of nonvolatile random access memory. Weight buffer stores weight data, which is used to train an ANN model (see Fig. 4, 403), which is a machine learning model. Weight buffer is part of memory die 501, where memory die refers to memory 102 in Fig. 1, which is part of an AI ASIC 101, which is a processor. Therefore, weight buffer is associated with a processor; See “Artificial Neural Network (ANN) with Practical Implementation” by Ali and “Application-specific integrated circuit” by Wikipedia);
storing input data in a dynamic random access memory (DRAM) coupled with the processor (Figs. 1 and 5, Col. 19, line 60 to Col. 20, line 14 : Input/output buffer 501b stores input/output data and may be implemented as DRAM. The buffer is part of memory die 501, where memory die refers to memory 102, which is part of an AI ASIC 101, which is a processor. Therefore, input/output buffer is coupled with the processor);
executing, via a functional unit associated with the processor, operations using the machine learning model based on the at least the portion of the weight data and the at least the portion of the input data ; and
writing a result of the operations to the DRAM (Figs. 2A, and 5, Col. 4, lines 30-35, Col. 11, line 61 to Col. 12, line 21, Col. 19, lines 63-65, Col. 20, lines 27-31: Once the multiplication operations have been performed, the results are stored in the temp buffer 502e. The results are then sent to the bottom die to store the data in I/O buffer 501b through I/Os 503b’/503b (Similar to what occurs in Fig. 2A where the results stored in the buffer in die 2 sends data back to be stored/written into die 1)).
Mathuriya does not teach to load at least the portion of the weight data from the NVRAM and the at least the portion of the input data from the DRAM into the memory registers of the processor.
Jiang teaches to load at least the portion of the weight data from the weight memory into memory registers and at least a portion of data from data memory into memory registers (Fig. 2 and 3, [0071-0073]: Portions of weight data from weight memory 20 is loaded into weight registers, which connects to an operation unit 30. Portions of grey-scale value data from data memory 10 is loaded into data registers, which also connects to the operation unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Mathuriya with the teachings of Jiang to have loaded the weight data from the NVRAM into memory registers and loaded the input data from DRAM into memory registers. One of ordinary skill would recognize that by loading the data into registers from NVRAM or DRAM rather than loading them into arithmetic units directly reduces the critical path delay, allowing higher clock speeds, which allows data to be processed faster.
Mathuriya, in view of Jiang, still does not teach to select, based on an asymmetry in access latency between the NVRAM and the DRAM, the portion of the weight data from the NVRAM and at least a portion of the input data from the DRAM to load into memory registers of the processor.
Note that NVRAM has a longer access latency than DRAM (See “Bridging the Latency Gap between NVRAM and DRAM for Latency-bound Operations”, Abstract).
Maiyuran teaches to prefetch data from memory devices with a long latency (Fig. 3 and [0018]: Data from memory devices with a long latency may be prefetched to devices with a short latency closer to an execution unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Mathuriya, in view of Jiang, with the teachings of Maiyuran to have prefetched the data from the NVRAM and storing the data into the memory registers, resulting in the selection of data based on an asymmetry in access latency between the NVRAM and DRAM. One of ordinary skill would recognize that by reducing the access latency of the NVRAM, data becomes available quicker, which results in data getting processed earlier.
Mathuriya, in view of Jiang and Maiyuran, still does not teach that the memory registers include a smaller amount of space for the at least the portion of the weight data from the NVRAM than an amount of space reserved for the at least the portion of the input data from the DRAM.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of Mathuriya, in view of Jiang and Maiyuran, to have made the memory registers of the weight data be smaller in space compared to the memory registers of the input data, or alternatively, made the memory registers of the input data be bigger in space compared to the memory registers of the weight data. One of ordinary skill may recognize that by decreasing the size of the registers, less power is required to hold the data in the registers and results in faster access latency. Regarding weight data, one of ordinary skill may not use much weight data compared to input data for AI models (such as CNNs) since weight data is generally reused (see Mathuriya, Col. 22, lines 17-23). Therefore, smaller register storage for weight data may be considered. One of ordinary skill may recognize that by increasing the size of the registers, more data can be processed and/or larger data ranges can be represented. Additionally, a change in size/proportion, i.e., changing the size of the memory registers, is considered a routine expedient, not a patentable distinction (MPEP 2144.04(IV)(A)).
Regarding claim 7, Mathuriya, as modified and in view of Jiang and Maiyuran, teaches the method of Claim 1, wherein the input data comprises data received from a streaming data source (Mathuriya, Figs. 2A, and 5, Col. 4, lines 30-35, Col. 11, line 61 to Col. 12, line 21, Col. 19, lines 63-65, Col. 20, lines 27-31: Buffer 502e would transmit (stream) data into the I/O buffer 501b (similar to what’s seen in Fig. 2A). Therefore, buffer 502e is a streaming data source).
Regarding claim 29, Mathuriya teaches an apparatus (Fig. 1, Col. 7, lines 60-67: System 100 as the apparatus), comprising:
means for initializing at least a portion of weight data for a machine learning model in a non-volatile random access memory (NVRAM) associated with a processor (Figs. 1, 4, and 5, Col 19, line 60 to Col. 20, line 14: Weight buffer 501a can be implemented as FE-RAM, which is a type of nonvolatile random access memory. Weight buffer stores weight data, which is used to train an ANN model (see Fig. 4, 403), which is a machine learning model. Weight buffer is part of memory die 501, where memory die refers to memory 102 in Fig. 1, which is part of an AI ASIC 101, which is a processor. Therefore, weight buffer is associated with a processor. ASIC 101 as the means for initializing; See “Artificial Neural Network (ANN) with Practical Implementation” by Ali and “Application-specific integrated circuit” by Wikipedia);
means for storing input data in a dynamic random access memory (DRAM) coupled with the processor (Figs. 1 and 5, Col. 19, line 60 to Col. 20, line 14 : Input/output buffer 501b stores input/output data and may be implemented as DRAM. The buffer is part of memory die 501, where memory die refers to memory 102, which is part of an AI ASIC 101, which is a processor. Therefore, input/output buffer is coupled with the processor. ASIC 101 as the means for storing);
means for executing, via a functional unit associated with the processor, operations using the machine learning model based on the at least the portion of the weight data and the at least the portion of the input data ; and
means for writing a result of the operations to the DRAM (Figs. 2A, and 5, Col. 4, lines 30-35, Col. 11, line 61 to Col. 12, line 21, Col. 19, lines 63-65, Col. 20, lines 27-31: Once the multiplication operations have been performed, the results are stored in the temp buffer 502e. The results are then sent to the bottom die to store the data in I/O buffer 501b through I/Os 503b’/503b (Similar to what occurs in Fig. 2A where the results stored in the buffer in die 2 sends data back to be stored/written into die 1). ASIC 101 as the means for storing).
Mathuriya does not teach a means to load at least the portion of the weight data from the NVRAM and the at least the portion of the input data from the DRAM into the memory registers of the processor.
Jiang teaches a means to load at least the portion of the weight data from the weight memory into memory registers and at least a portion of data from data memory into memory registers (Figs 1-3, [0071-0073]: Portions of weight data from weight memory 20 is loaded into weight registers, which connects to an operation unit 30. Portions of grey-scale value data from data memory 10 is loaded into data registers, which also connects to the operation unit. The data storage circuit 1 and weight storage circuit 2 as the means for loading).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Mathuriya with the teachings of Jiang to have loaded the weight data from the NVRAM into memory registers and loaded the input data from DRAM into memory registers. One of ordinary skill would recognize that by loading the data into registers from NVRAM or DRAM rather than loading them into arithmetic units directly reduces the critical path delay, allowing higher clock speeds, which allows data to be processed faster.
Mathuriya, in view of Jiang, still does not teach a means to select, based on an asymmetry in access latency between the NVRAM and the DRAM, the portion of the weight data from the NVRAM and at least a portion of the input data from the DRAM to load into memory registers of the processor.
Note that NVRAM has a longer access latency than DRAM (See “Bridging the Latency Gap between NVRAM and DRAM for Latency-bound Operations”, Abstract).
Maiyuran teaches to prefetch data from memory devices with a long latency (Fig. 3 and [0018]: Data from memory devices with a long latency may be prefetched to devices with a short latency closer to an execution unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Mathuriya, in view of Jiang, with the teachings of Maiyuran to have prefetched the data from the NVRAM and storing the data into the memory registers, resulting in the selection of data based on an asymmetry in access latency between the NVRAM and DRAM. One of ordinary skill would recognize that by reducing the access latency of the NVRAM, data becomes available quicker, which results in data getting processed earlier.
Mathuriya, in view of Jiang and Maiyuran, still does not teach that the memory registers include a smaller amount of space for the at least the portion of the weight data from the NVRAM than an amount of space reserved for the at least the portion of the input data from the DRAM.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of Mathuriya, in view of Jiang and Maiyuran, to have made the memory registers of the weight data be smaller in space compared to the memory registers of the input data, or alternatively, made the memory registers of the input data be bigger in space compared to the memory registers of the weight data. One of ordinary skill may recognize that by decreasing the size of the registers, less power is required to hold the data in the registers and results in faster access latency. Regarding weight data, one of ordinary skill may not use much weight data compared to input data for AI models (such as CNNs) since weight data is generally reused (see Mathuriya, Col. 22, lines 17-23). Therefore, smaller register storage for weight data may be considered. One of ordinary skill may recognize that by increasing the size of the registers, more data can be processed and/or larger data ranges can be represented. Additionally, a change in size/proportion, i.e., changing the size of the memory registers, is considered a routine expedient, not a patentable distinction (MPEP 2144.04(IV)(A)).
Claims 17 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Mathuriya et al (US 11836102 B1) in view of Yu (US 9998334 B1).
Regarding claim 17, the claim is mostly rejected for the same reasons as claim 1. Mathuriya, as modified and in view of Jiang and Maiyuran, also teaches a memory
Mathuriya, as modified and in view of Jiang and Maiyuran, does not teach that the memory has executable instructions stored.
Yu teaches a memory having executable instructions stored thereon (Fig. 5 and Col. 11, lines 47-60: Memory 532 may store instructions that are executable by a processor (e.g., processor 510)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Mathuriya, as modified and in view of Jiang and Maiyuran, with the teachings of Yu to have the memory contain executable instructions. One of ordinary skill would recognize that by having executable instructions stored in memory, a processor can retrieve and perform those instructions, which would allow data to be processed.
Regarding claim 30, the claim is mostly rejected for the same reasons as claim 1. Mathuriya, as modified and in view of Jiang and Maiyuran, also teaches one or more processors of a processing system (Mathuriya, Fig. 1, Col. 7, lines 60-67: System 100 comprising ASIC 101. ASIC 101 as the processor of the system).
Mathuriya, as modified and in view of Jiang and Maiyuran, does not teach a non-transitory computer-readable medium comprising computer-executable instructions.
Yu teaches a non-transitory computer-readable medium comprising computer-executable instructions (Fig. 5 and Col. 11, lines 33-60: Memory 532 (a non-transitory computer-readable medium) may store instructions that are executable by a processor (e.g., processor 510)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Mathuriya, as modified and in view of Jiang and Maiyuran, with the teachings of Yu to have the memory contain executable instructions. One of ordinary skill would recognize that by having executable instructions stored in memory, a processor can retrieve and perform those instructions, which would allow data to be processed.
Response to Arguments/Amendments
Applicant’s amendments, filed April 28, 2026, addresses the specification objections. The objections of the specification have been withdrawn.
Applicant’s amendments, filed April 28, 2026, addresses the claim objections. The objections of the claims has been withdrawn. However, new claim objections have been raised. See “Claim Objections” above.
Applicant’s amendments, filed April 28, 2026, addresses the 112(b) rejection. The 112(b) rejection of claim 17 have been withdrawn.
Applicant’s arguments, see page 12, paragraph 4 to page 17, paragraph 2, filed April 28, 2026, with respect to claims 1-4, 7, 17-20, 29, and 30 rejected under 35 U.S.C. 101 have been fully considered and are mostly persuasive.
Regarding arguments on page 12, paragraph 4 to page 13, paragraph 2, Applicant argues that the claims do not recite a mathematical concept.
Examiner respectfully disagrees with this argument. See MPEP 2106.04 regarding whether a claim is directed to a judicial exception. The claim indeed recites a judicial exception from the limitation “executing… operations using the machine learning model based on the at least the portion of the weight data and input data”, which recites a mathematical concept of performing operations using a machine learning model. The limitation itself does not have to recite a mathematical formula or equation (MPEP 2106.04(a)(2), paragraph 4). Furthermore, Applicant does not specify how the limitation is “merely based on or involves math”. Therefore, Applicant’s arguments, with respect to the claims not reciting a mathematical concept, is considered not persuasive.
Despite Applicant providing unpersuasive arguments, the rejection of the claims 1-4, 7, 17-20, 29, and 30 under 101 have been withdrawn due to providing persuasive arguments on pages 13, paragraph 4 to page 17, paragraph 2 and amendments made to the independent claims.
Applicant’s arguments, see page 12, paragraph 4 to page 17, paragraph 2, filed April 28, 2026, with respect to claims 1-4, 7, 17-20, 29, and 30 under 35 U.S.C. 102/103 have been fully considered and are mostly persuasive.
Regarding arguments on page 19, paragraph 3, Applicant argues that “if Maiyuran describes moving information from longer latency memory to shorter latency memory, and if NVRAM has long access latency than DRAM, this would suggest moving information from the [NV]RAM to the DRAM”.
Applicant does not provide details of how they came to the conclusion of moving information from the NVRAM to the DRAM. Therefore, Examiner cannot conclude that Applicant provided a persuasive argument. The purpose of Maiyuran is to give the general teachings of prefetching data from NVRAM to registers, which would, at least, suggest moving data from NVRAM (a longer latency memory) to registers (a shorter latency memory), such that it could teach a selection of data, based on an asymmetry in access latency. Therefore, Applicants arguments, with respect to the teachings of Maiyuran, is considered not persuasive.
Despite Applicant providing unpersuasive arguments, the rejection of the claims under 102/103 have been withdrawn due to amendments. However, upon further consideration, the claims are rejected under 35 U.S.C. 103.
Applicant’s request for rejoinder of claims 8, 10-16, and 22-28, will be denied at this time due to the claims being dependent on an independent claim rejected under prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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