DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status
Claims 1-18 are pending.
Claims 5, 11, and 17 are rejected under 35 U.S.C. 112(b). Claims 1-2, 6-8, 12-14, and 18 are rejected under 35 U.S.C. 103.
Claims 3-5, 9-11, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 5, 11, and 17 must also be amended to overcome rejection under 35 USC 112(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 11, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitations “generating a netlist corresponding to the to-be-simulated circuit according to a design database of the to-be-simulated circuit; acquiring, from the netlist, the node identifier corresponding to each power supply node in the to-be-simulated circuit; and generating the first netlist according to the node identifier corresponding to each power supply node.”.
It is unclear which netlist each recitation refers to.
First, it is unclear if “generating a netlist” is referencing a second netlist separate from “a first netlist” in claim 1. It could not be referencing “a first netlist” in claim 1 because the first netlist must have already been generated in claim 1 to be present for searching.
Second, it is unclear if “acquiring, from the netlist” is referencing “a first netlist” in claim 1 or a second netlist separate from “a first netlist” in claim 1.
Also, the “a first netlist corresponding to the to-be-simulated circuit” in claim 1 is the initial recitation, but claim 5 includes “generating the first netlist” as if it were not already present in claim 1. The first netlist must have already been generated in claim 1 to be present for searching.
Claims 11 and 17 are rejected in the same way as claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over “SPICE ‘Quick’ Reference Sheet”, Stanford EE133-Winter 2001, retrieved from https://web.stanford.edu/class/ee133/handouts/general/spice_ref.pdf, hereafter referred to as SPICE, in view of “Find and Replace Text”, Altium CircuitStudio Technical Documentation updated August 16, 2018, retrieved from https://www.altium.com/documentation/cstu/find-and-replace-text, hereafter referred to as Altium.
Regarding claim 1, SPICE discloses a circuit simulation method, applied to a to-be-simulated circuit comprising multiple power supply nodes, the method comprising: (pg. 2 ¶ 1 “First, Data Statements describe the components and the interconnections. Then, Control Statements tell SPICE what type of analysis to perform on the circuit.” Pg. 5 “Dependent Sources” “Voltage controlled voltage source” A voltage controlled voltage source indicates at least 2 voltage sources.)
generating a power supply voltage file (pg. 2 ¶ 1 “SPICE input file, called source file, consists of three parts. First, Data Statements describe the components and the interconnections.” Pg. 3 “Voltage and Current Sources” ) and simulating the to-be-simulated circuit according to the power supply voltage file (pg. 2 ¶ 1 “Then, Control Statements tell SPICE what type of analysis to perform on the circuit. Finally, Output Statements specify what outputs are to be printed or plotted.”).
SPICE does not explicitly disclose determining a key character string corresponding to at least one target power supply node;
searching out a node identifier corresponding to the at least one target power supply node from a first netlist corresponding to the to-be-simulated circuit according to the key character string, the node identifier consisting of the key character string and at least one other character; and
generating a power supply voltage file corresponding to the at least one target power supply node according to the searched-out node identifier.
Altium teaches determining a key character string corresponding to at least one target power supply node (The figure shows a “Text to find:” box for a user to enter a string. In the Scope section under Identifiers, “Net Identifiers Only” includes “power ports”.);
searching out a node identifier corresponding to the at least one target power supply node from a first netlist corresponding to the to-be-simulated circuit according to the key character string, the node identifier consisting of the key character string and at least one other character (In the Text section, “For example, if you enter the string VCC into the Text to Find field and enter the string {CC=DD} into the Replace With field, all instances of the string VCC will be changed to VDD .” Within the circuit description, the voltage VCC is replaced with VDD.); and
generating a power supply voltage file corresponding to the at least one target power supply node according to the searched-out node identifier (In the Text section, “For example, if you enter the string VCC into the Text to Find field and enter the string {CC=DD} into the Replace With field, all instances of the string VCC will be changed to VDD .” By replacing the CC with DD, the program updates the text file corresponding to voltage VCC.).
SPICE and Altium are analogous because they are from the “same field of endeavor” circuit modelling.
Before the effective filing date of the claimed invention, it would have been obvious to one of the ordinary skill in the art, having the teachings of Spice and Altium before him or her, to modify SPICE to include find and replace for voltage sources as taught by Altium.
The suggestion/motivation for doing so would have been Altium Summary “This dialog provides controls to quickly find specific or partial text in accordance with defined search options, then replace that text with specified new text.”
Regarding claim 2, SPICE in view of Altium teach the method of claim 1, and SPICE discloses wherein different power supply nodes in the first netlist correspond to different node identifiers (pg. 3 “Voltage and Current Sources” “Vname” Each voltage source has an identifier.);
SPICE does not disclose wherein searching out the node identifier corresponding to the at least one target power supply node from the first netlist corresponding to the to-be-simulated circuit according to the key character string comprises:
searching out a node identifier comprising the key character string from the first netlist corresponding to the to-be-simulated circuit and
using a searched-out node identifier comprising the key character string as the node identifier corresponding to the at least one target power supply node.
Altium teaches wherein searching … comprises: searching out a node identifier comprising the key character string from the first netlist corresponding to the to-be-simulated circuit (In the Text section, “For example, if you enter the string VCC into the Text to Find field and enter the string {CC=DD} into the Replace With field, all instances of the string VCC will be changed to VDD .” VCC is a node identifier character string.); and
using a searched-out node identifier comprising the key character string as the node identifier corresponding to the at least one target power supply node (In the Text section, “For example, if you enter the string VCC into the Text to Find field and enter the string {CC=DD} into the Replace With field, all instances of the string VCC will be changed to VDD .” The instances of VCC are the target nodes.).
Regarding claim 6, SPICE in view of Altium teach the method of claim 1, and SPICE discloses wherein the target power supply node is a power supply node, which is connected with an external power supply through a power switch, in the to-be- simulated circuit (pg. 5 “Dependent Sources” “Value is a multiplier value. In math terms: Value*(NC1-NC2)=(N+ – N–)” The dependent source is switched; if the controlling source supplies no voltage, i.e. NV1-NC2=0, then the dependent source supplies no voltage.).
Claims 7-8, 12-14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over “SPICE ‘Quick’ Reference Sheet”, Stanford EE133-Winter 2001, retrieved from https://web.stanford.edu/class/ee133/handouts/general/spice_ref.pdf, hereafter referred to as SPICE, in view of “Find and Replace Text”, Altium CircuitStudio Technical Documentation updated August 16, 2018, retrieved from https://www.altium.com/documentation/cstu/find-and-replace-text, hereafter referred to as Altium, in view of Chen et al. (US 2022/0245316 A1).
Regarding claim 7, SPICE in view of Altium teach the body of the claim in the same way as claim 1, and SPCIE discloses a to-be-simulated circuit comprising multiple power supply nodes (pg. 2 ¶ 1 “First, Data Statements describe the components and the interconnections. Then, Control Statements tell SPICE what type of analysis to perform on the circuit.” Pg. 5 “Dependent Sources” “Voltage controlled voltage source” A voltage controlled voltage source indicates at least 2 voltage sources.)
SPICE and Altium do not explicitly disclose a circuit simulation apparatus, the apparatus comprising: a memory storing processor-executable instructions; and a processor configured to execute the stored processor-executable instructions to perform operations.
Chen teaches a circuit simulation apparatus ([0028] “In actual simulation, the created schematic are transformed into a file referred a "netlist" by the EDA platform, wherein information like interconnections between different devices, nodes or block and the condition settings to be simulated or checked are described in text or numeric format in the netlist for the circuit simulator to perform the actions like reading, calculating and processing.”), the apparatus comprising: a memory storing processor-executable instructions; and a processor configured to execute the stored processor-executable instructions to perform operations ([0026] “A processor 101 reads, compute and process the computer readable code and data from random access memory DRA 102. A high capacity secondary storage device, such as disk drive 103, provides program code and data which can be loaded into the DRAM 102.”).
SPICE, Altium, and Chen are analogous because they are from the “same field of endeavor” circuit modelling.
Before the effective filing date of the claimed invention, it would have been obvious to one of the ordinary skill in the art, having the teachings of SPICE, Altium, and Chen before him or her, to modify SPICE and Altium to include an apparatus as taught by Chen.
The suggestion/motivation for doing so would have been Chen Abstract “A computer-implemented method of performing voltage rule check in an electronic design automation (EDA)…”. The computer apparatus is used for implementing the simulation method.
Regarding claim 8, SPICE in view of Altium and Chen teach the apparatus of claim 7, and the remainder of claim 8 is rejected in the same way as claim 2.
Regarding claim 12, SPICE in view of Altium and Chen teach the apparatus of claim 7, and the remainder of claim 12 is rejected in the same way as claim 6.
Regarding claim 13, SPICE in view of Altium teach the body of the claim in the same way as claim 1.
SPICE and Altium do not explicitly disclose a non-transitory computer-readable storage medium having stored thereon computer- executable instructions that, when executed by a processor, cause the processor to implement operations.
Chen teaches a non-transitory computer-readable storage medium having stored thereon computer- executable instructions that, when executed by a processor, cause the processor to implement operations ([0026] “A processor 101 reads, compute and process the computer readable code and data from random access memory DRA 102. A high capacity secondary storage device, such as disk drive 103, provides program code and data which can be loaded into the DRAM 102.”)..
SPICE, Altium, and Chen are analogous because they are from the “same field of endeavor” circuit modelling.
Before the effective filing date of the claimed invention, it would have been obvious to one of the ordinary skill in the art, having the teachings of SPICE, Altium, and Chen before him or her, to modify SPICE and Altium to include an apparatus as taught by Chen.
The suggestion/motivation for doing so would have been Chen Abstract “A computer-implemented method of performing voltage rule check in an electronic design automation (EDA)…”. The computer apparatus is used for implementing the simulation method.
Regarding claim 14, SPICE in view of Altium and Chen teach the medium of claim 13, and the remainder of claim 14 is rejected in the same way as claim 2.
Regarding claim 18, SPICE in view of Altium and Chen teach the medium of claim 13, and the remainder of claim 18 is rejected in the same way as claim 6.
Allowable Subject Matter
Claims 3-5, 9-11, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 5, 11, and 17 must also be amended to overcome rejection under 35 USC 112(b).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art as exemplified by SPICE, Altium, and Chen teaches the method of claim 1, however, the prior art of record fails to teach, alone or in obvious combination, “querying a power supply voltage of the target power supply node corresponding to each node identifier according to the searched-out node identifier; and
generating the power supply voltage file according to the power supply voltage of the target power supply node corresponding to each node identifier.”, in combination with the other limitations of the claims.
Claim 4 inherits the subject matter of claim 3.
Regarding claim 5, the prior art as exemplified by SPICE, Altium, and Chen teaches the method of claim 1, however, the prior art of record fails to teach, alone or in obvious combination, “generating a netlist corresponding to the to-be-simulated circuit according to a design database of the to-be-simulated circuit; acquiring, from the netlist, the node identifier corresponding to each power supply node in the to-be-simulated circuit; and generating the first netlist according to the node identifier corresponding to each power supply node..”, in combination with the other limitations of the claims.
Claims 9-11 and 15-17 are objected to in the same way as claims 3-5 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (US 2021/0182467 A1) discloses assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net.
Naveen et al. "N2S: An Automatic Netlist to Schematic generator" 1991 IEEE discloses generating a schematic based on a netlist.
“Find-Replace Text”, NEXUS Client 5, 4, 3.2, 3.1, 3.0, 2.1, 2.0, 1.1 and 1.0 Technical Documentation, updated July 16, 2018, retrieved on 1/17/2026 from https://www.altium.com/documentation/altium-nexus/textedit-dlg-findrepldlgformfind-replace-text-ad discloses finding and replacing text in the NEXUS client application.
The examiner respectfully requests, in response to this Office action, support is shown for language added to any original claims on amendment and any new claims. Indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s).
When responding to this Office Action, the applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TROY A MAUST whose telephone number is (571)272-1931. The examiner can normally be reached on Monday-Friday from 8AM to 4PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen, can be reached at telephone number (571) 272-3676. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.A.M./Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189