Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
All claims have a priority date of 09/23/2022 as filed.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/24/2025 has been entered.
Claims 1, 3, 5, 9-14, 16, and 21-23 are amended and claim 4 previously canceled. Claims 1-3, and 5-26 remain pending, while 25-26 are withdrawn.
Response to Arguments
Applicant’s arguments filed 10/24/2025 with respect to the 35 USC 103 rejection of claims 1-3, 5-24 have been considered but are moot because the arguments do not apply to the specific grounds of rejection based on the references being used in the current rejection.
Although the rejection is based on an existing reference Khlat, the mapping and elements of Khlat have been changed to reflect the features incorporated or modified by claim amendments from previous claim 9 that included the feedback circuitry. New teachings of Khlat include:
a second amplifier a control input (Fig. 2C Control Signal 926 into control input 930A of LDO 930)
sensing and conditioning circuitry output (Fig. 2C, V_offset 42 AND/OR 874F) and one or more inputs (V_para_amp, 876 VCC, Fig’s 2C, 8B and 8D) coupled to the output (928C) of the first amplifier (928) and the output (LDO1 Output) of the second amplifier (930; 950);
feedback circuitry (Fig. 2A-C: feedback selection switch 940, connections 940A, 940B, 940C to LDO output, LDO feedback) coupled between the sensing and conditioning circuitry (Fig. 2A-C: 41) and the control input of the second amplifier (Fig. 2C, , 930B [control] inverting input to amplifier 930), wherein the feedback circuitry provides a feedback signal from the sensing and conditioning circuitry to the control input (Fig. 2C and accompanying text “The feedback selection switch 940 includes an output terminal 940A in communication with an inverting input 930B of the linear regulator 930, LDO”) to adjust a match between a power demand of a power amplifier (Fig. 2A RF Amplifier 869) coupled to the output power port (Fig. 2A P_OUT) and a voltage provided by the switcher circuitry (Fig. 2C V_SW and SW_OUT coupled to 869A input RF Amplifier via 876/VCC wherein “a collector voltage supply input 869A configured to receive the modulated power supply voltage, V.sub.CC, from the modulated power supply output 876"), the first amplifier (928C output coupled to RF amplifier input 869A via VCC 876, Fig. 2C and 8B), and the second amplifier at the output power port (“the second linear regulator output 874D, LDO.sub.2 OUTPUT, to provide a second linear regulator output voltage, V.sub.LDO2, to the CMOS logic supply input 869C”).
Thus claims 1-3, 6-8, 10-13, 15, and 17-24 are rejected under USC 102 by Khlat.
Applicant’s arguments filed 10/24/2025 with respect to the obviousness type double patenting rejection of claims 1-3, 5-26 have been considered but are conclusory and not persuasive.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8, 10-13, 15, and 17-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KHLAT NADIM et al. EP 2705604 B2.
Consider Claim 1
KHLAT teaches An envelope tracking power supply (Fig. 1, Fig. 2A, [0001], [0007], [0013] power management system), the envelope tracking power supply comprising:
an envelope signal input port (Figs. 1, 2A-2C, 8B; See VRAMP+, VRAMP-; [0009]-[0010]“the.. power amplifier supply voltage, V cc, may be modulated to substantially follow..modulated radio frequency input signal..”);
an output power port (Fig. 1, 2A-2C and 8B, [0008] “..a power amplifier supply voltage, Vcc,..”);
a first amplifier (''parallel amplifier 928" [0050] and Fig. 2C and BB) having an input (928A, Fig. 2C and 8B) and an output (928C, Fig. 2C and 8B);
a second amplifier ("linear regulator 930, LDO, [0109] and Fig. 2C; 950, Fig. 8B) having an input (930A, 930B, Fig. 2C; 950A, Fig. 8B), an output (LDO_1 OUTPUT, Fig.'s 2C and BB), and a control input (Fig. 2C Control Signal 926 into control input 930A of LDO 930; SEE ALSO: 44 Figs. 1 and 2C and BB; [0121]" the controller 50 may configure the differential filter 924 to provide maximum peaking of the differential V RAMP signal ...", and Fig. 5A),
wherein the control input of the second amplifier is configured to set a power state for the second amplifier ([0119] and Fig. 4 "high power modulation mode", "medium power modulation mode", "low power modulation mode");
an input interface circuit (Fig. 's 2C and 8B) having an input coupled to the envelope signal input port (V_ramp+, V_ramp-), a first output coupled to the input (928A) of the first amplifier (928), and a second output coupled to the input (930A; 950A) of the second amplifier ( [0176] first linear regulator 950, LDO1);
sensing and conditioning circuitry (Fig 2C, 8D, [0089] “..the VoFFSET loop circuit 41 may be configured to provide a threshold offset current 42, ITHRESHow_oFFSET, to the switcher control circuit 880..” having an output (Fig. 2C, V_offset 42 AND/OR 874F) and one or more inputs (V_para_amp, 876 VCC, Fig’s 2C, 8B and 8D) coupled to the output (928C) of the first amplifier (928) and the output (LDO1 Output) of the second amplifier (930; 950);
switcher circuitry (Fig. 1: 12, Fig 8A 872, Fig. 2B: 872) having an input (Fig. 1 42, Fig. 2A-C and 8B) and an output Fig. 1, 2A-2C and 8B, 26), wherein the input (42) is coupled to the output (V_Offset) of the sensing and conditioning circuitry (41), and wherein the output (26) is coupled to the output power port (V_CC; Fig. 2C and 8B: NB via filter 16, 18A, 19);
output filter circuitry (Fig. 2C and 8B: 16, 18A, 19), wherein the output of the first amplifier (928) is coupled to the output power port (Vcc) via the output filter circuitry (Fig. 2C and 8B 16, 18A, 19), and
wherein the output (LDO1_OUTPUT) of the second amplifier (930;950) is coupled to the output power port via the output filter circuitry (Fig. 2C and 8B 16, 18A, 19 and V_CC); and
feedback circuitry (Fig. 2A-C: feedback selection switch 940, connections 940A, 940B, 940C to LDO output, LDO feedback) coupled between the sensing and conditioning circuitry (Fig. 2A-C: 41) and the control input of the second amplifier (Fig. 2C, , 930B [control] inverting input to amplifier 930), wherein the feedback circuitry provides a feedback signal from the sensing and conditioning circuitry to the control input (Fig. 2C and accompanying text “The feedback selection switch 940 includes an output terminal 940A in communication with an inverting input 930B of the linear regulator 930, LDO”) to adjust a match between a power demand of a power amplifier (Fig. 2A RF Amplifier 869) coupled to the output power port (Fig. 2A P_OUT) and a voltage provided by the switcher circuitry (Fig. 2C V_SW and SW_OUT coupled to 869A input RF Amplifier via 876/VCC wherein “a collector voltage supply input 869A configured to receive the modulated power supply voltage, V.sub.CC, from the modulated power supply output 876"), the first amplifier (928C output coupled to RF amplifier input 869A via VCC 876, Fig. 2C and 8B), and the second amplifier at the output power port (“the second linear regulator output 874D, LDO.sub.2 OUTPUT, to provide a second linear regulator output voltage, V.sub.LDO2, to the CMOS logic supply input 869C”).
Consider Claim 2.
The combination teaches The envelope tracking power supply of claim 1,
wherein the first amplifier (928) is a main amplifier configured to provide linear amplification (''parallel amplifier 928" [0050] and Fig. 2C and 8B 928 is main linear amplifier).
Consider Claim 3.
The combination The envelope tracking power supply of claim 1,
wherein the control input is configured to set the power state for the second amplifier by switching the second amplifier between the on state and the off state based on at least one of a voltage level or frequency envelope changes indicated by the sensing and conditioning circuitry (Fig. 3, [0053] “..the peaking amplifier is turned On/Off automatically considering a power level of an input signal of the Doherty power amplifier 330. In an example, the peaking amplifier is inactivated together with the envelope tracking power amplifier 340. After that, at a time when the carrier amplifier is saturated, the peaking amplifier is activated to amplify a sign…”).
Consider Claim 6.
The combination teaches The envelope tracking power supply of claim 1,
wherein the control input is configured to set the power state based on a current operating mode selected from a plurality of operating modes ([0119] and Fig. 4 "high power modulation mode", "medium power modulation mode", "low power modulation mode");.
Consider Claim 7.
The combination teaches The envelope tracking power supply of claim 6,
wherein the plurality of operating modes includes a high power mode and a low power mode ([0119] and Fig. 4 "high power modulation mode", "medium power modulation mode", "low power modulation mode").
Consider Claim 8.
The combination teaches The envelope tracking power supply of claim 6,
wherein the control input is further based on one or more of a radio access technology (RAT) configuration, a peak-to-average power ratio value of a radio frequency (RF) signal, or a bandwidth of the RF signal ([0185] “..the power management system 870A may disable all active noise reduction circuits as a function of the expected output power to be generated by the radio frequency power amplifier 869' during a data transmission, a band of operation in which the data transmission will take place, a bandwidth of the band of operation in which the data transmission will take place, the of modulation used in the data transmission, the peakto-average ratio characteristic of the waveform to be generated…”).
Consider Claim 10.
The combination teaches The envelope tracking power supply of claim 1, further comprising: a first sense element coupled between the output of the first amplifier and the input of the sensing and conditioning circuitry; and a second sense element coupled between the output of the second amplifier and a second input of the sensing and conditioning circuitry (the sensing and conditioning circuitry senses both outputs of first and second amplifiers separately (VPARA AMP, Fig. 2C and 8D; LDO1_OUTPUT / Vcc, cf. D1: Fig. 's 2C and 8D; Both are sensed voltages are coupled by a sense element 18A, cf. D1: Fig. 2C).
Consider Claim 11.
The combination teaches The envelope tracking power supply of claim 1, further comprising: a first sense element coupled between the output of the first amplifier and the input of the sensing and conditioning circuitry; and a second sense element coupled between the output of the second amplifier and a second input of the sensing and conditioning circuitry (the sensing and conditioning circuitry senses both outputs of first and second amplifiers separately (VPARA AMP, Fig. 2C and 8D; LDO1_OUTPUT / Vcc, cf. D1: Fig. 's 2C and 8D; Both are sensed voltages are coupled by a sense element 18A, cf. D1: Fig. 2C).
Consider Claim 12.
The combination teaches The envelope tracking power supply of claim 1, further comprising:
a sense element having an input and an output, wherein the input is coupled to the output of the first amplifier and the output of the second amplifier, and wherein the output is coupled to the input of the sensing and conditioning circuitry (the sensing and conditioning circuitry senses both outputs of first and second amplifiers separately (VPARA AMP, Fig. 2C and 8D; LDO1_OUTPUT / Vcc, cf. D1: Fig. 's 2C and 8D; Both are sensed voltages are coupled by a sense element 18A, cf. D1: Fig. 2C).
Consider Claim 13.
The combination teaches The envelope tracking power supply of claim 1,
wherein the output filter circuitry comprises first filter circuitry coupled between the output of the first amplifier and the output power port; wherein the output filter circuitry further comprises second filter circuitry different from the first filter circuitry, wherein the second filter circuitry is coupled between the output of the second amplifier and the output power port (LDO1_OUTPUT is directly coupled to capacitor 19 and thus low-pass filtered at very high frequencies, whilst VPARA_AMP is attenuated by capacitive divider 18A, 19).
Consider Claim 15.
The combination teaches The envelope tracking power supply of claim 1,
wherein the first amplifier is a linear amplifier (''parallel amplifier 928" [0050] and Fig. 2C and 8B 928 is main linear amplifier)..
Consider Claim 17.
The combination teaches The envelope tracking power supply of claim 1,
wherein the input interface circuit is configured to receive a digital envelope signal at the envelope signal input port (Fig. 1, [0010]: “..the VRAMP signal may represent either an analog or digital signal..”) ;
wherein the input interface circuit is configured to output a first tracking signal at the first output ([0010] “..the parallel amplifier circuit 14 may generate the parallel amplifier output voltage, V PARA_AMP, based on the difference between the..”) based on a set of least significant bits of the digital envelope signal (Figs. 5-7 a normal tracking mode);
and wherein the input interface circuit is configured to output a second tracking signal based on one or more most significant bits of the digital envelope signal (Figs. 5-7, 1618 in Fig. 7, where a slow tracking mode the envelope tracking power supply would effectively only be taking the most significant bits in consideration).
Consider Claim 18.
KHLAT teaches The envelope tracking power supply of claim 1, further comprising a common stage element coupled to the input interface circuit, wherein the first output of the input interface circuit is a first output of the common stage element, and wherein the second output of the input interface circuit is a second output of the common stage element (the common stage can be seen e.g. as the combined circuit 924/942 (cf. D1: Fig. BB) providing individual outputs to the amplifiers.).
Consider Claim 19.
KHLAT teaches The envelope tracking power supply of claim 1,
wherein the envelope tracking power supply is coupled to a radio frequency (RF) front end (RFFE) transmit power amplifier,
wherein the RFFE transmit power amplifier comprises a voltage supply input coupled to the output power port (Figs. 2A-2C RF Amplifier 869 cooupled to VCC)
Consider Claim 20.
KHLAT teaches The envelope tracking power supply of claim 19,
wherein an output of the RFFE transmit power amplifier is coupled to an antenna (Figs. 2A-2C Antenna coupled to RF Amplifier 869).
Consider Claim 21.
KHLAT teaches The envelope tracking power supply of claim 19,
wherein an output of the RFFE transmit power amplifier is coupled to an input of a power tracking coupler;
wherein an output of the power tracking coupler is coupled to feedback circuitry configured to provide current supply feedback to the switcher circuitry (feedback of current supply information (IPAWA_ouT, ITHRESHoo_oFFSET, cf. D1: Fig. 's 1 and 2B-C) to the switcher circuitry).
Consider Claim 22.
The combination teaches The envelope tracking power supply of claim 21,
wherein the feedback circuitry is part of a transceiver, and wherein the transceiver further comprises a digital to analog circuit having an output coupled to the envelope signal input port ([0176]: “..the parallel amplifier circuit 87 4' may further include a (DAC) programmable digital to analog converter..”): .
Consider Claim 23.
The combination teaches The envelope tracking power supply of claim 21,
wherein the control input of the second amplifier is coupled to modem circuitry configured to provide envelope tracking control data to the second amplifier ([0241]: “..the digital baseband processing portion of the transceiver or modem that provides the differential VRAMP signal to the parallel amplifier circuit 874' may determine the expected output power to be generated by the radio frequency power amplifier 869'”).
Consider Claim 24.
The combination teaches The envelope tracking power supply of claim 23,
wherein the first amplifier further comprises a control input, and wherein the modem circuitry is coupled to the control input of the first amplifier ([0241]: “..the digital baseband processing portion of the transceiver or modem that provides the differential VRAMP signal to the parallel amplifier circuit 874' may determine the expected output power to be generated by the radio frequency power amplifier 869'”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over KHLAT NADIM et al. EP 2705604 B2 in view of CN 113054934 A ZHANG, XIANG-HUI et al.
Consider Claim 5.
The combination teaches The envelope tracking power supply of claim 4,
KHLAT does not explicitly disclose wherein the second amplifier is configured to operate in a saturation mode during the on state (See ZHANG Pg. 7 Paragraph 8 “..The envelope tracking modulator ETM21 can dynamically adjust the power supply voltage Vpa21 of the power amplifier circuit PA21 according to the envelope variation so that the power amplifier circuit PA21 can work in the saturation high efficiency region..”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art, to modify the invention of KHLAT to include the noted teachings of BBB in order to effectively improve the transmission efficiency, so as to improve the whole efficiency of the wireless communication system. (See ZHANG Pg. 7 Paragraph 8).
Claims 9, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over KHLAT NADIM et al. EP 2705604 B2 in view of US 20130093511 A1 BAEK; Sang-Hyun et al
Consider Claim 9.
The combination teaches The envelope tracking power supply of claim 1 (see claim 1).
KHLAT further teaches the second amplifier provides a maximum peaking (930 and 924 together [0091]: “..the controller 50 may configure the differential filter 924 to provide maximum peaking of the differential VRAMP signal..”), but does not teach the second amplifier is a peaking amplifier, and wherein the control input of the second amplifier is configured to set a power state for the second peaking amplifier by switching the peaking amplifier between an on state and an off state.
Baek teaches the second amplifier is a peaking amplifier (Baek Fig. 3, [0053] “..the Doherty power amplifier 330 includes a class-AB carrier amplifier and a class-C peaking amplifier …”) and configured to set a power state for the second peaking amplifier by switching the peaking amplifier between an on state and an off state (Baek Fig. 3, [0053] “..the peaking amplifier is turned On/Off automatically considering a power level of an input signal of the Doherty power amplifier 330. In an example, the peaking amplifier is inactivated together with the envelope tracking power amplifier 340. After that, at a time when the carrier amplifier is saturated, the peaking amplifier is activated to amplify a sign..”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art, to modify the invention of KHLAT to include the noted teachings of Baek in order to m employs a scheme of amplifying an input signal using a supply voltage (Baek [006])
Consider Claim 14.
The combination teaches wherein the first amplifier is a class-AB amplifier, and wherein the second amplifier is a class-C amplifier (Baek [0053] “..the Doherty power amplifier 330 includes a class-AB carrier amplifier and a class-C peaking amplifier …”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art, to modify the combination to include the noted teachings of Baek in order to m employs a scheme of amplifying an input signal using a supply voltage (Baek [006])
Consider Claim 16.
The combination teaches the second amplifier is a switching amplifier (Baek [0055] “..he supply modulator 342 includes a linear amplifier and a switching amplifier…”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art, to modify the combination to include the noted teachings of Baek in order to m employs a scheme of amplifying an input signal using a supply voltage (Baek [006])
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of Co-pending Application No. 17935074 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because as shown in the table below claim 1 and 10 sufficiently cover the subject matter of instant claim 1 including the first and second amplifier which are covered in claim 10. The remaining dependent claims 2-24 are also rejected as covered by the subject matter of 17935074 claims 1-20.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant application 17935071
Pending application 17935074
1. An envelope tracking power supply, the envelope tracking power supply comprising: an envelope signal input port; an output power port; a first amplifier having an input and an output; a second amplifier having an input, an output, and a control input, wherein the control input of the second amplifier is configured to set a power state for the second amplifier configured to set a power state for the second amplifier by switching the second amplifier between an on state and an off state; an input interface circuit having an input coupled to the envelope signal input port, a first output coupled to the input of the first amplifier, and a second output coupled to the input of the second amplifier; sensing and conditioning circuitry having an output and one or more inputs coupled to the output of the first amplifier and the output of the second amplifier; switcher circuitry having an input and an output, wherein the input is coupled to the output of the sensing and conditioning circuitry, and wherein the output is coupled to the output power port; and output filter circuitry, wherein the output of the first amplifier is coupled to the output power port via the output filter circuitry, and wherein the output of the second amplifier is coupled to the output power port via the output filter circuitry.
1. An envelope tracking power supply, the envelope tracking power supply comprising: an envelope signal input port; an output power port; an input interface circuit having an output and an input coupled to the envelope signal input port; sensing and conditioning circuitry having an output and an input; amplifier circuitry coupled between the output of the input interface circuit and the input of the sensing and conditioning circuitry, the amplifier circuitry having one or more control inputs; switcher circuitry having an input and an output, wherein the input is coupled to the output of the sensing and conditioning circuitry, and wherein the output is coupled to the output power port; output filter circuitry, wherein the output filter circuitry is coupled to the output power port via the output filter circuitry; and machine learning circuitry having an output coupled to the one or more control inputs, and one or more inputs configured to receive state tracking data for performance of transmit power amplifier (PA) that receives power via the output power port.
10. The envelope tracking power supply of claim 1, wherein the amplifier circuitry comprises a linear amplifier configured to provide a first portion of a high frequency component of a tracking voltage; and wherein the amplifier circuitry further comprises a switching amplifier configured to operate in a saturation mode and provide a second portion of the high frequency component of the tracking voltage when the tracking voltage is above a threshold value.
12. The envelope tracking power supply of claim 10, wherein the one or more control inputs comprise a control input to select between an on state and an off state for the switching amplifier.
Conclusion
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/UMAIR AHSAN/Primary Examiner, Art Unit 2647