Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-13, and 15-17 are rejected under 35 U.S.C. 102 as anticipated by Go et al. (CN 114446991 A).
Regarding Claim 9, Go et al. discloses a semiconductor structure comprising:
A substrate (21, Fig. 1);
A plurality of gate structures (stack structure 68, gate electrode GE), located on the substrate and arranged at intervals along a first direction;
A plurality of supporters (support piece 49, dummy columns 81, insulating layer 48 used to provide structural support) penetrating a top of each of the plurality of gate structures and extending along the first direction, wherein, wherein the plurality of supporters are arranged along a second direction and shaped as crossbars parallel to each other at a same horizontal level, the first direction and the second direction are both parallel to the substrate (Fig. 12).
“A plurality of dummy columns 81 may be used to provide structural support for a plurality of horizontal conductive layers 61, 62N-2, 62N-1, 62N + 1, and 62 that are alternately stacked on the substrate 21. For example, virtual column 81 can prevent a plurality of horizontal conductive layer 61, 62N-2 62N-1, 62N, 62N + 1 and 62 when processing the semiconductor device collapse, and a plurality of horizontal conductive layer connection area EXT 61, 62N-2, 62N 62N-1 62N + 1 and 62 can be more firmly in place.”
PNG
media_image1.png
354
597
media_image1.png
Greyscale
PNG
media_image2.png
170
310
media_image2.png
Greyscale
Regarding Claim 10, Go et al. discloses a gate structure comprising:
A gate dielectric layer (element isolation layer 23) located on the substrate (FIG. 16);
A gate conductive layer (conductive layers 61) located on the gate dielectric layer;
An insulation cap layer (35) located on the gate conductive layer.
“It will be understood that when the element is referred to as "connected" or "bonded" to another element or "on" another element ", the element can be directly connected or directly bonded to the other element or directly on the other element, or may be present in the intermediate element. In contrast, when the element is referred to as "directly connected" or "directly combined" to another element, or is referred to as "contact" another element or with another element "contact", there is no intervening element at the contact.”
PNG
media_image3.png
404
602
media_image3.png
Greyscale
Regarding Claim 11, Go et al. discloses a gate conductive layer comprising:
A first conductive layer located on the gate dielectric layer (62);
A barrier layer located on the first conductive layer (moulding layers 51, 52);
And a second conductive layer located on the barrier layer (62).
PNG
media_image4.png
339
568
media_image4.png
Greyscale
Regarding Claim 12, Go et al. discloses a plurality of supporters (dummy posts 81) which penetrate a top of the insulation cap layer (FIG. 15).
PNG
media_image5.png
375
593
media_image5.png
Greyscale
Regarding Claim 13, Go et al. discloses a gate structure further comprising:
A supplementary layer located on the insulation cap layer (connection moulding layer 45M);
A supporter (support piece 49) which penetrates the supplementary layer;
And a top surface of the supplementary layer is flush with a top surface of the plurality of supporters.
Regarding Claim 15, Go et al. discloses a material of the plurality of supporters comprises silicon carbon nitride:
“a plurality of dummy columns 81 and a plurality of word line isolation pattern 82 in each may include silicon oxide, silicon nitride, silicon oxynitride, boron silicon nitride (SiBN), silicon carbon nitride (SiCN), low-k dielectric or high-k dielectric (e.g., metal oxide such as HfO or Al2O3; such as metal silicate of HfSiO and so on).
Regarding Claim 16, Go et al. discloses a plurality of gate structures (68) constitute one gate group (GE), with each gate group comprising two gate structures that form an annular structure.
Regarding Claim 17, Go et al. discloses a plurality of supporters (81) which penetrates a top of each of 2 to 6 gate groups (FIG. 15).
PNG
media_image6.png
182
235
media_image6.png
Greyscale
FIG. 15
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as obvious over Go et al. (CN 114446991 A).
Regarding Claim 14, Go et al. discloses a second direction as being perpendicular to the first (81 being perpendicular to 47/48) but does not disclose the width dimension of the supporter as 2 nm to 10 nm in a second direction, however, it would be obvious to one ordinarily skilled in the art before the effective filing date of the application to size the supporter based on the available mechanical space available to provide appropriate compressive/tensile stress allowances and prevent device collapse.
Response to Arguments
Applicants’ amendment with respect to claim 9 “plurality of supporters, penetrating a top of each of the plurality of gate structures and extending along the first direction, wherein the plurality of supporters are arranged along a second direction and shaped as crossbars parallel to each other at a same horizontal level, the first direction and the second direction are both parallel to the substrate." has been acknowledged.
With respect to the “plurality of supporters”, Applicants argue that “Further according to Fig. 9, it clearly shows that, the plurality of supporters 3 are shaped as crossbars parallel to each other at a same horizontal level, and the first direction (direction X) and the second direction (direction Y) are both parallel to the substrate 1. With respect of Go, the semiconductor device includes the support piece 49 and dummy columns 81, which are regarded as the supporters. However, the support piece 49 and dummy columns 81 are different members, the dummy columns 81 are shaped as pillars extending along a direction perpendicular to the substrate 21, while the support piece 49 is a film layer with multiple holes formed by the dummy columns 81 (the dummy columns 81 penetrating the support piece 49). Hence, the support piece 49 and dummy columns 81 are obviously different from the plurality of supporters of the amended claim 9. The independent claim 9 and dependent claims 10-13 and 15-17 with their dependencies from claim 1 are therefore believed to be novel over Go.”
However, Go et al. (CN 114446991 A) teaches a plurality of supporters (support piece 49, dummy columns 81, insulating layer 48 used to provide structural support) penetrating a top of each of the plurality of gate structures and extending along the first direction (“The upper surface and the sixth insulating layer 48 of the support piece 49 can be substantially coplanar with each other.”), wherein the plurality of supporters are arranged along a second direction and shaped as crossbars parallel to each other at a same horizontal level, the first direction and the second direction are both parallel to the substrate (Fig. 12).
“A plurality of dummy columns 81 may be used to provide structural support for a plurality of horizontal conductive layers 61, 62N-2, 62N-1, 62N + 1, and 62 that are alternately stacked on the substrate 21. For example, virtual column 81 can prevent a plurality of horizontal conductive layer 61, 62N-2 62N-1, 62N, 62N + 1 and 62 when processing the semiconductor device collapse, and a plurality of horizontal conductive layer connection area EXT 61, 62N-2, 62N 62N-1 62N + 1 and 62 can be more firmly in place.” Thus, while dummy columns 81P and support piece 49 are perpendicular to each other, dummy column 81S, insulating layer 48 as well as stacked structure 68 including a plurality of moulded layers 51 and 52 are parallel (Fig. 18).
PNG
media_image7.png
307
540
media_image7.png
Greyscale
Conclusion
Applicants' amendment did not necessitate a new grounds of rejection in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua S Wyatt whose telephone number is (703) 756-1937. The examiner can normally be reached 7:00 AM - 5:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSHUA SCOTT WYATT/Examiner, Art Unit 2815
/JAY C KIM/Primary Examiner, Art Unit 2815