DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The replacement drawings were received on 06/05/2025. These drawings are acceptable to overcome the drawing objections made in the Non-Final Office Action mailed on 03/12/2025. However, additional drawing objections are noted below.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Since claim 1 is a method claim, the drawings associated with the method must show every step and feature of the method in the proper sequence so the method claim logically and consistently maps to the drawings associated with he method. For claim 1, the Examiner cannot map all of the method limitations to the submitted drawings in a sequential manner which conveys a clear set of steps to manufacture a semiconductor structure. The sequence jumps to several drawings out of sequence. For example, the limitations in lines 7-14 including “forming a sacrificial layer…forming a plurality of first conductive segments disposed at intervals in the sacrificial layer…” implies the sequence as illustrated in FIGS. 9-11. But then lines 17-18 recite the limitation “removing all sacrificial layers in the plurality of first structures in a single processing step”, which is only shown in FIG. 6. The drawings therefore do not show the claimed method steps in the order in which they occur. The clear and consistent sequence of steps recited in the method must be explicitly shown in the drawings or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Page 10, line 14 appears to have a typographical error: “…formed a plurality of times are connected as a whore…”. Appropriate correction is required.
Additionally, the specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 3-4 and 6-11 are objected to because of the following informalities:
Claim 1, lines 26-28 and 39-41 recite multiple instances of the phrase “capacitor holes”. It is recommended to change this language to for example a term which is more widely used in the art such as, only for example, “openings for a capacitor”.
Claims 3-4 and 6-11 are objected to based on their dependence on claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4 and 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, when read it its entirety, is unclear and indefinite because it does not recite a method in an ordered, clear and cohesive sequence of steps so as to enable one of ordinary skill in the art to understand the invention or practice the method. Several examples of the indefiniteness of claim 1 are given below.
Claim 1, lines 4-6 recite “sequentially forming a plurality of first structures …wherein a method for forming the plurality of first structures comprises: …”, then line 22 recites “wherein the sequentially forming a plurality of first structures comprises: …”. It is unclear how these two limitations of the claim relate to each other, and which happens first in the method. The Examiner does not understand how there are separate method steps for “sequentially forming a plurality of first structures” and “forming the plurality of first structures” as claimed. Does “wherein a method for forming the plurality of first structures comprises: …” refer to a method to form an individual first structure of the plurality of first structures? As best understood, this is the case based on lines 7-14 appearing to map to FIGS. 9-13.
Claim 1, lines 15-16 recite “sacrificial layers in adjacent two of the first structures…”, although the method in the preceding lines of the claim has not yet provided a clear sequence of steps to form multiple “sacrificial layers” or “adjacent two” first structures. Line 7 recites “forming a sacrificial layer”, but does not explain how the sacrificial layer becomes “sacrificial layers”. Therefore, the limitation “sacrificial layers” lacks antecedent basis in the claim.
Claim 1, line 17 recites “removing all sacrificial layers in the plurality of first structures in a single step”. This limitation is unclear since the claim has not provided steps to form “sacrificial layers”.
Claim 1, line 24 recites “and the first sacrificial layer is a same layer as the sacrificial layer”. This limitation is unclear. For purposes of examination, as best understood, the first sacrificial layer in the first first structure of the plurality of first structures is interpreted as becoming part of a continuous sacrificial layer connecting several first structures, as shown, e.g. in FIG. 5. Lines 28-29 recite a similar limitation regarding “the second sacrificial layer”, which is also unclear.
Claim 1, lines 24-25 recites “the first support layer is a same layer as the support layer”. This limitation is unclear. For purposes of examination, as best understood, the first support layer in the first first structure of the plurality of first structures is interpreted as becoming part of the support layer. Lines 40-41 recite a similar limitation regarding “the second support layer”, which is also unclear.
Claim 1, lines 15 and 19 recite “the first structures”. There is insufficient antecedent basis for this limitation in the claim. Additionally, it is unclear how “the first structures” relate to “the plurality of first structures” as recited in line 4 and repeatedly used throughout claim 1. For purposes of examination, as best understood, “the first structures” has been interpreted as “the plurality of first structures”. It is recommended to change instances of “the first structures” to “the plurality of first structures” where appropriate. Appropriate correction is required.
Claim 8, line 2 recites the limitation "the substrate". There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, as best understood, “the substrate” has been interpreted as the substrate of the base as recited in claim 4. Appropriate correction is required.
Claim 9, line 2 recites the limitation "the substrate". There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, as best understood, “the substrate” has been interpreted as the substrate of the base as recited in claim 4. Appropriate correction is required.
Claims 3-4 and 6-7 and 10-11 are rejected at least based on their dependence on claim 1.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-4 and 8-11, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. in US 2012/0193761 A1 (hereinafter Park).
Regarding claim 1, Park teaches in FIGS. 5A-5H, 6, 10A-10G and related text, A method of manufacturing a semiconductor structure, comprising:
providing a base (see annotated FIG. 10E below); and
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Annotated FIG. 10E (Park)
sequentially forming a plurality of first structures (annotated FIG. 10E; 132/123/125a in lower first structure, [0021]/[0040]; 222/211/213a in upper first structure, [0067]/[0081]/[0070]) stacked in a direction perpendicular to the base (vertical), wherein a method for forming the plurality of first structures comprises (inasmuch as Applicant’s disclosure shows):
forming a sacrificial layer (123/211, FIG. 10E, [0040]/[0081])
forming a plurality of first conductive segments (132/222, FIG. 10E, [0021]/[0067]) disposed at intervals in the sacrificial layer (123/211), wherein tops of the first conductive segments (132/222) are exposed outside the sacrificial layer (123/211); and
forming a support layer (125a/213a, FIG. 10E, [0021]/[0070]) on a top surface of the sacrificial layer (123/211, respectively, FIG. 10E), wherein the support layer (125a/213a) is at least partially formed on surfaces of some of the first conductive segments (132/222) exposed outside the sacrificial layer (123/211), the support layer (125a/213a) is provided with openings (see annotated FIG. 10E. [0052]), and the openings expose parts of the sacrificial layer (123/211; [0052]);
sacrificial layers (123/127) in adjacent two of the first structures are connected by using the openings (sacrificial layer 211 of the upper first structure is connected to sacrificial layer 123 of the lower first structure using the lower opening shown in annotated FIG. 10E); and
removing all sacrificial layers (123 and 211) in the plurality of first structures (FIG. 10G, [0092]), wherein in the direction perpendicular to the base (vertical), the first conductive segments (132/222) in the first structures form a first conductive structure (132 and 222 combine to form part of lower electrode 250, FIG. 6, [0066]), support layers (125a/213a) in the first structures form a support segment, and the support segment and the first conductive structure form an intermediate structure (structure of FIG. 10G is an intermediate structure that is formed into a capacitor such as those shown in FIGS. 6-9, [0093]);
wherein the sequentially forming a plurality of first structures comprises (inasmuch as Applicant’s disclosure shows):
forming a first sacrificial layer (123, FIG. 5B) on the base (annotated FIG. 10E) and a first initial support layer (125, FIG. 5B, [0041]) on the first sacrificial layer (123), and the first sacrificial layer (123) is a same layer as the sacrificial layer (123 in lower plurality of first structures, annotated FIG 10E);
providing a first mask pattern (hard mask pattern, [0043]), and based on the first mask pattern, forming first capacitor holes (129, FIG. 5C, [0043]) penetrating the first initial support layer (125) and the first sacrificial layer (123);
depositing a conductive material (130, FIG. 5D, [0044]) in the first capacitor holes (129), and forming the first conductive segments (132, FIG. 5E, [0051]);
providing a second mask pattern (mask pattern, [0052]), and based on the second mask pattern, removing parts of the first initial support layer (125, FIG. 5E, [0052]), and forming a plurality of first openings (refer to annotated FIG. 10E, [0052]), wherein remaining parts of the first initial support layer (125) form a first support layer (125a, FIG. 5E, [0052]), and the first support layer (125a) is a same layer as the support layer (125a of lower first structure, annotated FIG. 10E);
depositing a second sacrificial layer (211, FIG. 10A, [0081]) on the first support layer (123) and the first conductive segments (132), wherein the second sacrificial layer (211) and the first sacrificial layer (123) are connected by using the first openings (lower openings shown in annotated FIG. 10A), and the second sacrificial layer (211) is a same layer as the sacrificial layer (211 in upper first structure of annotated FIG. 10E);
depositing a second initial support layer (213, FIG. 10A, [0081]) on the second sacrificial layer (211);
providing a third mask pattern (hard mask pattern, [0082]), and based on the third mask pattern, forming second capacitor holes (217, FIG. 10B, [0082]) penetrating through the second sacrificial layer (211) and the second initial support layer (213), wherein the second capacitor holes (217) at least partially expose the first conductive segments (132, FIG. 10B);
depositing a conductive material (220, FIG. 10D, [0085]) in the second capacitor holes (217), and forming second conductive segments (222, FIG. 10E, [0085]), wherein the second conductive segments (222) are connected to the first conductive segments (132, FIG. 10E, [0085]); and
providing a fourth mask pattern ([0090], FIG. 10E described with respect to FIG. 5E which uses a mask pattern, [0052]), and based on the fourth mask pattern, removing parts of the second initial support layer (213), and forming a plurality of second openings (openings formed in upper first structure similar to those formed in lower first structure shown in annotated FIG. 10E), wherein remaining parts of the second initial support layer (213) form a second support layer (213a), and the second support layer (213a) is a same layer as the support layer (support layer 213a in upper first structure of annotated FIG. 10E); and
the first support layer (125a) and the second support layer (213a) form a support segment, and the first conductive segments (132) and the second conductive segments (222) form a first conductive structure.
Park does not explicitly teach removing all sacrificial layers (123 and 211) in the plurality of first structures (FIG. 10G, [0092]) in a single processing step.
However, Park appears to teach in FIG. 10G all sacrificial layers (123 and 211) are removed in a single processing step. Park additionally teaches layers 123 and 211 are formed from the same materials ([0041]/[0081]) having different etch selectivity relative to layers 125a and 213a ([0092]), which would allow them to be etched without in a single step without substantially etching 125a and 213a.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have removed all sacrificial layers in the plurality of first structures in a single processing step, as suggested by Park in FIG. 10G and [0092], in order to reduce the number of chemical etching steps in the manufacturing process.
Regarding claim 3, Park teaches the method of manufacturing a semiconductor structure according to claim 1. Park teaches further comprising:
forming a dielectric layer (260, FIG. 6, [0093]) covering the intermediate structure (structure of FIG. 10G); and
forming a second conductive structure (270, FIG. 6, [0092]) covering the dielectric layer (260), wherein the intermediate structure (structure of FIG. 10G), the dielectric layer (260), and the second conductive structure (270) form a capacitor structure ([0066]).
Regarding claim 4, Park teaches the method of manufacturing a semiconductor structure according to claim 1. Park further teaches wherein the providing a base (see annotated FIG. 10E in the rejection of claim 1) comprises:
providing a substrate (100, [0019]); and
forming a plurality of contact structures (113, [0067]) disposed at intervals in the substrate (100), wherein the plurality of first structures (see annotated FIG. 10E) are connected with the substrate (100), the first conductive segments (132/222, FIG. 10E) in the plurality of first structures in connection with the substrate (100) are respectively connected to the contact structures (113) in one-to-one correspondence (lower electrode 250 of capacitor in FIG. 6 is formed on each contact structure 113, [0067]).
Regarding claim 8, Park teaches the method of manufacturing a semiconductor structure according to claim 1. Park further teaches wherein in a direction perpendicular to the substrate (100; vertical direction), the first sacrificial layer (123) and the second sacrificial layer (211) have a same thickness or not (mold layer 120 has a thickness of 5000-15,000 Å, [0039], most of which is from first sacrificial layer 123; mold layer 210 has a thickness of about 5000 – 21,000 Å, [0081], most of which is from second sacrificial layer 211; also see FIG. 10E).
Regarding claim 9, Park teaches the method of manufacturing a semiconductor structure according to claim 1. Park further teaches wherein in a direction perpendicular to the substrate (100; vertical direction), the first initial support layer (125) and the second initial support layer (213) have a same thickness or not (125 has a thickness of about 100 – 1000 Å, [0041]; Park is silent regarding the specific thickness of 213 but states the second mold layer 210, which comprises layer 213, is similar to first mold layer 120a, which comprises layer 125).
Regarding claim 10, Park teaches the method of manufacturing a semiconductor structure according to claim 1. Park further teaches wherein the first mask pattern (mask pattern used to create capacitor holes 129 in FIG. 5C, [0043]) and the third mask pattern (mask pattern used to create capacitor holes 217 in FIG. 10B, [0082]) are the same or different (same mask pattern, [0082]).
Regarding claim 11, Park teaches the method of manufacturing a semiconductor structure according to claim 1. Park further teaches wherein the second mask pattern (mask pattern used to create openings shown in lower part of annotated FIG. 10E, [0052]) and the fourth mask pattern (mask pattern used to create openings shown in upper part of annotated FIG. 10E, [0090]) are the same or different (FIG. 10E is described in reference to FIG. 5E which creates the second mask pattern, [0052], so the second and fourth mask patterns are the same).
Claims 6 and 7, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. in US 2012/0193761 A1 (hereinafter Park) in view of Choi in US 2021/0296431 A1 (hereinafter Choi).
Regarding claim 6, Park teaches the method of manufacturing a semiconductor structure according to claim 1, wherein the providing a second mask pattern (mask pattern used to create openings shown in lower part of annotated FIG. 10E, [0052]), and based on the second mask pattern, removing parts of the first initial support layer (125), and forming a plurality of first openings (lower openings in annotated FIG. 10E) comprises:
forming the second mask pattern ([0052]), wherein a plurality of first pattern holes are provided in the second mask pattern ([0052]), and the first pattern holes each expose at least a part of the first initial support layer (125) between adjacent two of the first conductive segments (132, FIG. 5E; portions of 125 exposed by first pattern holes ([0052]);
etching the first initial support layer (125, FIG. 5E, [0052]) along the first pattern holes, and forming the first openings (lower openings shown in annotated FIG. 10E) exposing parts of the first sacrificial layer (123); and
removing the first mask layer (first mask layer does not exist in final structure and thus must be removed), wherein remaining parts of the first initial support layer (125a, FIG. 5E) each are formed between at least adjacent two of the first conductive segments (132, FIG. 5E).
Park does not explicitly teach forming a first mask layer on the first initial support layer; and patterning the first mask layer.
Choi teaches in FIGs.14A, 14B and related text, forming a first mask layer (continuous layer 224, FIG. 14A, [0096]) on a first initial support layer (152T, FIG. 14A, [0096]); and patterning the first mask layer (224 is patterned in FIG. 14B).
Park and Choi are analogous art to the claimed invention because they are directed to capacitor structures having high aspect ratio in the vertical dimension and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Choi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method as taught by Park to include forming a first mask layer on the first initial support layer; and patterning the first mask layer, as taught by Choi, with the purpose of creating the first pattern holes in the fewest number of processing steps, since other methods of forming the second mask pattern would involve greater complexity. Additionally, patterning of mask layers to form etch masks is a well-known technique well known widely used in the art.
Regarding claim 7, Park as modified by Choi teaches the method of manufacturing a semiconductor structure according to claim 6. Park further teaches wherein the providing a fourth mask pattern (mask pattern used to create openings shown in upper part of annotated FIG. 10E, [0090]), and based on the fourth mask pattern, removing parts of the second initial support layer (213), and forming a plurality of second openings (upper openings in annotated FIG. 10E) comprises:
forming the fourth mask pattern ([0052], noting the process in FIGS. 10D-10E are described with respect to FIG. 5E, [0090]), wherein a plurality of second pattern holes ([0052]) are provided in the fourth mask pattern, and the second pattern holes each expose a part of the second initial support layer (213) and a part of the second conductive segments (222, FIG. 10E);
etching the second initial support layer (213, see [0052]) along the second pattern holes, and forming the second openings (upper openings shown in annotated FIG. 10E) exposing parts of the second sacrificial layer (211) and parts of the second conductive segments (222); and
removing the second mask layer (second mask layer is not preset in the final structure and is thus removed), wherein remaining parts of the second initial support layer (213a, FIG. 10E) each are formed on a partial outer surface of at least one of the second conductive segments (221).
Park does not explicitly teach forming a second mask layer on the second initial support layer; and patterning the second mask layer.
Choi teaches in FIGS. 21A, 21B and related text, forming a second mask layer (continuous layer 254, FIG. 21A, [0113]) on a second initial support layer (154T, FIG. 14A, [0113]); and patterning the second mask layer (254 is patterned in FIG. 21B).
Park and Choi are analogous art to the claimed invention because they are directed to capacitor structures having high aspect ratio in the vertical dimension and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Choi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method as taught by Park to include forming a second mask layer on the second initial support layer; and patterning the second mask layer, as taught by Choi, with the purpose of creating the second pattern holes in the fewest number of processing steps, since other methods of forming the second mask pattern would involve greater complexity. Additionally, patterning of mask layers to form etch masks is a well-known technique well known widely used in the art.
Response to Arguments
Applicant’s remarks on page 8 regarding amendments to the drawings is acknowledged.
In response, the Examiner finds the replacement drawing sheets acceptable to remedy the drawing objections made in the Non-Final Office Action mailed on 03/12/2025. However, additional drawing objections are noted in the Instant Office Action as described on pages 2-3.
Applicant’s remarks on page 9 regarding the status of the claims in the Instant Application is acknowledged.
Applicant’s additional remarks on pages 9-10 regarding amendments to the drawings is acknowledged.
In response, the Examiner finds the replacement drawing sheets acceptable but notes additional drawing objections, as stated above.
Applicant’s remarks on page 10 regarding rejections made under 35 USC 112(b) in the Non-Final Office Action made on 03/12/2025 are acknowledged.
In response, the Examiner finds the amendments are not sufficient to overcome the 112(b) rejections made in the Non-Final Office Action made on 03/12/2025. In fact, the Examiner finds the amendments to claim 1 render the claim even further indefinite than the original claim, because when read it its entirety, claim 1 does not recite a method in an ordered sequence of steps so as to enable one of ordinary skill in the art to understand the invention or practice the method. Applicant is directed to pages 4-6 for an explanation of several problems with amended claim 1 which render it indefinite.
Applicant’s remarks on pages 10-11 regarding 102 rejections made in the Non-Final Office Action made on 03/12/2025 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Additionally, the Examiner finds the references applied in the new ground of rejection teach all the limitations of claims 1, 3-4 and 6-11 as best understood by the Examiner and inasmuch as the Applicant’s disclosure shows.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN LEE JOHNSON JR whose telephone number is (571)270-3217. The examiner can normally be reached Mon-Fri: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.L.J./Examiner, Art Unit 2811
/LYNNE A GURLEY/
Supervisory Patent Examiner, Art Unit 2811