DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Prior Art Rejections
Applicant’s arguments, filed6/3/2026, with respect to the rejections of claims 1-25 under 35 USC 103 have been fully considered and are persuasive. The prior art of record does not teach updating two destination-accumulator rows. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection is made in view of new prior art rejections necessitated by Applicant’s amendments.
Claim Interpretation
The Examiner interprets “destination-accumulator rows” to mean “accumulator vector registers” based on paragraphs [0373] and [0378] of Applicant’s specification describing rows as vectors and the FPU pipeline resolving two rows of results together.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation “destination-accumulator rows”. It is unclear whether the “destination-accumulator rows” are components within the system, processor, processing resources, or is external to the system. That is, it is not clear whether the “destination-accumulator rows” are inferentially citing a structural element of the claim, as the elements have not been positively recited within a claimed structure.
Claims 1, 10 are rejected for the same reasons as discussed above for claim 16.
Claims 2-9, 11-15, 17-25 are rejected for depending on claims 1, 10, and 16 respectively without correcting the deficiencies of the claims as discussed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-13, 16-19, 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al. (US 20210191724 A1, hereinafter “Pal”) in view of Cordrescu et al. (US 20160026607 A1, hereinafter “Cordrescu”).
As per claim 1, Pal teaches A processor comprising: processing resources comprising multiplier circuitry to: receive operands for a matrix multiplication operation, wherein the operands comprising two source matrices to be multiplied as part of the matrix multiplication operation (Pal: Fig. 20; [0235]);
and issue a multiply and add vector (MADV) instruction for the multiplication operation (Pal: Fig. 21A; [0242]),
wherein the MADV instruction to multiply two vectors of the two source matrices in a single floating point (FP) pipeline of the processor (Pal: [0248], [0253]).
However, while Pal discloses an execution pipeline for MADV instructions (Fig. 21C), Pal does not explicitly disclose detailed circuitry for performing the instruction. Thus, Pal does not teach utilizing a double accumulator access output; wherein the double accumulator access output comprises a double-wide output from a single FP pipeline to a destination accumulator to update, in a same cycle of the processor, two destination-accumulator rows for the MADV instruction.
Cordrescu teaches utilizing a double accumulator access output (Cordrescu: Fig. 1 elements 22; [0023]); wherein the double accumulator access output comprises a double-wide output from a single FP pipeline to a destination accumulator to update, in a same cycle of the processor, two destination-accumulator rows for the MADV instruction (Cordrescu: Fig. 2 elements 22; [0029], a vector register corresponding with a destination-accumulator row).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the execute stages of Pal (Fig. 21C elements 2132A with the vector processor of Cordrescu such that each execute stage of Pal corresponds to a write port of Cordrescu. One would have been motivated to combine these references because both references disclose performing vector multiply-add operations, and the data parallelization of Codrescue increases processing bandwidth and overall processing performance (Cordrescu: [0009]).
As per claim 2, Pal/Cordrescu further teaches The processor of claim 1, wherein the multiplier circuitry is further to: iterate through a loop of the MADV instruction to combine results of vector multiplications to generate a final result for the matrix multiplication operation (Pal: Fig. 22; [0251]);
and output the final result for the matrix multiplication operation (Pal: [0235]).
As per claim 3, Pal/Cordrescu further teaches The processor of claim 1, wherein the MADV instruction is to generate a matrix output (Pal: [0235]).
As per claim 4, Pal/Cordrescu further teaches The processor of claim 1, wherein the multiplier circuitry comprises one or more multiplier-accumulate (MAC) units to support double precision (DP) multiplication operations on at least two elements of a vector of one of the two source matrices in a same cycle (Pal: [0112], [0124]).
As per claim 5, Pal/Cordrescu further teaches The processor of claim 1, wherein the MADV instruction is issued to a single floating point unit (FPU) pipeline of the processor, the FPU pipeline configured to provide double wide source input for one of the two source matrices and configured to provide the double accumulator access output via the double-wide output for the destination accumulator (Cordrescu: Fig. 2 elements 22; [0029]).
As per claim 8, Pal/Cordrescu further teaches The processor of claim 1, wherein the processor comprises a graphics processing unit (GPU) (Pal: [0087]).
As per claim 9, Pal/Cordrescu further teaches The processor of claim 1, wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine (Pal: [0112]).
As per claim 10, the claim is directed to a method that implements the same or similar features as the processor of claim 1, and is therefore rejected for at least the same reasons therein.
As per claim 11, Pal/Cordrescu further teaches The method of claim 10, further comprising: iterating through a loop of the MADV instruction to combine results of vector multiplications to generate a final result for the matrix multiplication operation (Pal: Fig. 22; [0251]);
and outputting the final result for the matrix multiplication operation (Pal: [0235]); wherein the MADV instruction is to generate a matrix output (Pal: [0235]).
As per claims 12-13, the claims are directed to a method that implements the same or similar features as the processor of claims 4-5, respectively, and are therefore rejected for at least the same reasons therein.
As per claim 16, the claim is directed to a system that implements the same or similar features as the method of claim 10, and is therefore rejected for at least the same reasons therein. Furthermore, Pal/Cordrescu teaches a memory to store a block of data (Pal: [0231]).
As per claims 17-19, the claims are directed to a method that implements the same or similar features as the method of claims 11-13, respectively, and are therefore rejected for at least the same reasons therein.
As per claim 21, the claim is directed to a non-transitory computer-readable medium that implements the same or similar features as the processor of claim 2, and is therefore rejected for at least the same reasons therein.
As per claims 22-24, the claims are directed to a non-transitory computer-readable medium that implements the same or similar features as the processor of claims 3-5, respectively, and are therefore rejected for at least the same reasons therein.
Claims 6-7, 14-15, 20, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Pal/Cordrescu in further view of Heinecke et al. (US 20190227797 A1, hereinafter “Heinecke”).
As per claim 6, Pal/Cordrescu teaches The processor of claim 1,
However, while Pal discloses an execution pipeline for MADV instructions (Fig. 21C), Pal does not explicitly disclose detailed circuitry for performing the instruction. Thus, Pal does not teach wherein the multiplier circuitry is comprised in a single floating point unit (FPU) pipeline that comprises 16 channel double precision (DP) multiplier-accumulate (MAC) units, and wherein the 16 channel double precision MAC units can support a 16 channel single precision (SP) MAC to provide double speed for the MADV instruction with a SP data type.
Heinecke teaches wherein the multiplier circuitry is comprised in a single floating point unit (FPU) pipeline that comprises 16 channel double precision (DP) multiplier-accumulate (MAC) units, and wherein the 16 channel double precision MAC units can support a 16 channel single precision (SP) MAC to provide double speed for the MADV instruction with a SP data type (Heinecke: Fig. 5B element 528; [0093] showing the example MAC circuitry of Fig. 15 can expand to 16-wide).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the execute stages of Pal with the multiply-accumulate circuitry of Heinecke. While Pal discloses the instruction to be processed, Pal does not disclose the details of the underlying hardware that implements it. A person of ordinary skill of the art would look to Heinecke for suitable SIMD units for detailed, because both references are related to Intel processors. Thus, one would have been motivated to combine these references because both references disclose performing vector multiply-add operations on Intel processors, and combining prior art elements according to known methods to yield predictable results (circuitry for performing a vector multiply-add operation).
As per claim 7, Pal/Cordrescu teaches The processor of claim 1,
However, while Pal discloses an execution pipeline for MADV instructions (Fig. 21C), Pal does not explicitly disclose detailed circuitry for performing the instruction. Thus, Pal does not teach wherein the multiplier circuitry is part of an arithmetic logic unit (ALU) and comprises a plurality of adders and shifters.
Heinecke teaches wherein the multiplier circuitry is part of an arithmetic logic unit (ALU) and comprises a plurality of adders and shifters (Heinecke: Fig. 5B element 528; [0093]; [0125] last sentence; wherein the MAC circuitry of Fig. 15 is part of an ALU).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the execute stages of Pal with the multiply-accumulate circuitry of Heinecke for at least the same reasons as discussed for claim 6.
As per claims 14-15, the claims are directed to a method that implements the same or similar features as the processor of claims 6-7, respectively, and are therefore rejected for at least the same reasons therein.
As per claim 20, the claim is directed to a method that implements the same or similar features as the method of claim 14, and is therefore rejected for at least the same reasons therein.
As per claim 25, the claim is directed to a non-transitory computer-readable medium that implements the same or similar features as the processor of claim 6, and is therefore rejected for at least the same reasons therein.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Magklis et al. (US 20190377573 A1) discloses an element-by-vector circuit that is scalable for larger vectors (Fig. 12).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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