Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment to claims 1, 3, 5-6 and 14-16 submitted on January 15, 2026 are acknowledged and have since been entered. Cancellation of claim 4 and addition of claim 21 are further acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-17 and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu (US 20190157345 A1).
Regarding Claim 14, Zhu teaches a semiconductor structure (see Fig. 23c), comprising:
a substrate (1001);
a plurality of bit lines (1029), disposed on a surface of the substrate and arranged in parallel;
semiconductor pillars (1007, 1009 and 1011) formed by a silicon-based semiconductor layer (see [0046]), disposed on surfaces of the bit lines and arranged along a direction of the bit line, wherein the semiconductor pillar is electrically connected to the bit line (shown Fig. 23c);
wherein the semiconductor pillar comprises a first source-drain region (1007) at a bottom, a channel region (1009) in a middle, and a second source-drain region (1011) at a top;
a gate-all-around structure (1031, 1033, 1017, 1019, 1037 and 1039), wherein the gate-all-around structure comprises a first insulating layer (1017 and 1019), a gate structure layer (1033), and a second insulating layer (1037 and 1039) that are sequentially disposed on a side surface of the semiconductor pillar and the gate-all-around structure at least covers the channel region of the semiconductor pillar (shown Fig. 23c); and
a first wire (1047), a magnetic tunnel junction (1049, 1051 and 1053), and a second wire (1057) that are sequentially disposed above a surface of the gate-all-around structure, wherein the first wire is electrically connected to the semiconductor pillar (shown Fig. 23c).
Regarding Claim 15, Zhu teaches the semiconductor structure according to claim 14, wherein the first source-drain region and the second source-drain region are formed through doping with a first-type dopant, and the channel region is formed through doping with a second-type dopant (see [0047]); and
the first source-drain region is at least partially located below a lower surface of the gate structure layer (shown Fig. 23c), and when the first source-drain region is all located below the lower surface of the gate structure layer, an upper surface of the first source-drain region is flush with the lower surface of the gate structure layer (shown Fig. 23c, wherein a lower surface of 1031 is flush with an upper surface of 1007); and
the second source-drain region is at least partially located above an upper surface of the gate structure layer (shown Fig. 23c), and when the second source-drain region is all located above the upper surface of the gate structure layer, a lower surface of the second source-drain region is flush with the upper surface of the gate structure layer (shown Fig. 23c, wherein an upper surface of 1031 is flush with a lower surface of 1011).
Regarding Claim 16, Zhu teaches the semiconductor structure according to claim 14, wherein the gate structure layer comprises:
a gate dielectric layer (1031), disposed on a side surface of the semiconductor pillar (shown Fig. 23c); and
a gate conductive layer (1033), disposed between the first insulating layer (portions of 1017 and 1019) and the second insulating layer (1037 and 1039), covering a side surface of the gate dielectric layer (shown Fig. 23c), surrounding the side surface of the semiconductor pillar, and extending along a direction perpendicular to the bit line (shown Fig. 23c).
Regarding Claim 17, Zhu teaches the semiconductor structure according to claim 14, wherein the surface of the bit line comprises a first metal silicide layer (described in [0076] as being between the source 1007 and bit line 1029).
Regarding Claim 20, Zhu teaches the semiconductor structure according to claim 14, wherein the magnetic tunnel junction comprises a fixed layer (1049), a non-magnetic insulating layer (1051), and a non-fixed layer (1053) that are disposed sequentially, a direction of magnetic moment of the non-fixed layer is changeable (described as a magnetic free layer in [0091]), and a direction of magnetic moment of the fixed layer is fixed (described as a magnetic fixed layer in [0091]).
Regarding Claim 21, Zhu teaches a method of manufacturing a semiconductor structure, comprising:
providing a substrate (1001);
forming a base pattern on the substrate (see pattern in Fig. 14a), wherein the base pattern comprises a plurality of bit lines (1029) arranged in parallel, and an isolation structure (1023’) is disposed between adjacent two of the bit lines (shown Fig. 14a);
forming a plurality of semiconductor pillars (shown Fig. 23c of final structure) arranged in a direction of the bit line on a surface of each of the bit lines (shown Fig. 23c), wherein the bit line is electrically connected to the semiconductor pillar;
forming a gate-all-around structure (1031, 1033 and 1039, shown Fig. 23c) on a surface of the semiconductor pillar (shown Fig. 16a),
wherein the gate-all-around structure comprises a first insulating layer (1031), a gate structure layer (1033), and a second insulating layer (1039) that are sequentially disposed on a side surface of the semiconductor pillar (shown Fig. 23c); and
forming a first wire (1047), a magnetic tunnel junction (1049, 1051 and 1053), and a second wire (1057) that are stacked sequentially above a surface of the gate-all-around structure, wherein the first wire is electrically connected to the semiconductor pillar (shown Fig. 23c);
wherein the forming a plurality of semiconductor pillars arranged in a direction of the bit line on a surface of each of the bit lines comprises:
forming a silicon-based semiconductor layer (layers 1007, 1009 and 1011 shown Fig. 14a) on surfaces of the bit lines (shown Fig. 14a); and
patterning the silicon-based semiconductor layer (shown Fig. 15a), to form the plurality of semiconductor pillars in the direction of the bit line, wherein the semiconductor pillar comprises a first source-drain region (1007) at a bottom, a channel region (1009’) in a middle, and a second source-drain region (1011) at a top, and the gate-all-around structure at least covers the channel region of the semiconductor pillar (shown Fig. 23c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu (US 20190157345 A1) in further view of Oh (US 20150214314 A1).
Regarding Claim 18, Zhu teaches the semiconductor structure according to claim 14, but does not explicitly teach wherein air gaps are formed on sidewalls of the bit line.
Oh teaches a semiconductor structure wherein air gaps (318A, see Fig. 7B)) are formed on a sidewall of a bit line (316) as part of an isolation structure (318).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the isolation structure of Zhu to further comprise air gaps on a sidewall of the bit lines as this is known to reduce parasitic capacitance (see also [0078]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu (US 20190157345 A1) in further view of Lin (US 20230135098 A1) and Sanchez (Silicide Formation by High Does Transition Metal Implants Into Si, 2011).
Regarding Claim 19, Zhu teaches the semiconductor structure according to claim 14, but does not explicitly teach wherein a second metal silicide layer is disposed at a top of the semiconductor pillar. Lin teaches a semiconductor structure wherein a metal silicide (102a) is formed between a top doped region (112a) of a semiconductor pillar (100a) and a lower electrode (104a) of a memory structure (R, shown Fig. 1C). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a metal silicide layer connecting a semiconductor pillar to a first wire as silicide regions are known in the art to reduce contact resistance and power consumption (see also evidenced by P. 440 of Sanchez).
Allowable Subject Matter
Claims 1-3 and 5-13 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, Zhu (US 20190157345 A1) being the most relevant prior art of record teaches a method (shown Figs. 1-23) of manufacturing a semiconductor structure (shown Fig. 23a-c), comprising:
providing a substrate (1001);
forming a base pattern (1027 and 1029) on the substrate (shown Fig. 13a), wherein the base pattern comprises a plurality of bit lines (1029) arranged in parallel, and an isolation structure (1023’) is disposed between adjacent two of the bit lines (shown Fig. 13a, see also [0077]);
forming a plurality of semiconductor pillars (1007, 1009 and 1011, see also [0055]) arranged in a direction of the bit line on a surface of each of the bit lines (shown Fig. 13a), wherein the bit line is electrically connected to the semiconductor pillar (connected to source region 1007);
forming a gate-all-around structure (1031, 1033, 1017, 1019 1037 and 1039) on a surface of the semiconductor pillar, wherein the gate-all-around structure comprises a first insulating layer (1017 and 1019), a gate structure layer (1033), and a second insulating layer (1037 and 1039) that are sequentially disposed on a side surface of the semiconductor pillar (see Fig. 19a); and
forming a first wire (1047), a magnetic tunnel junction (1049, 1051 and 1053, see also [0091]), and a second wire (1057) that are stacked sequentially above a surface of the gate-all-around structure (shown Fig. 23c), wherein the first wire is electrically connected to the semiconductor pillar (shown Fig. 23c) wherein the forming a base pattern on the substrate comprises:
forming an isolation layer (1023) on a surface of the substrate;
patterning the isolation layer (to form 1023’), and forming an isolation structure (1023’); and
forming a first metal silicide layer on the surface of the bit line.
However, the prior art does not explicitly teach or suggest wherein the isolation structure comprises a plurality of bar grooves arranged in parallel and forming the bit line in each of the plurality of bar grooves. Rather, the prior art teaches a sacrificial layer 1005 being removed between adjacent isolation structures to accommodate deposition of the bit lines as shown in Figs. 10-12b. As such, claim 1 is allowed. Claims 2-3 and 5-13 are further allowed due to their dependence on claim 1.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Response to Arguments
Applicant's arguments filed January 15, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “a monolithic columnar structure” being a single silicon-based semiconductor layer implemented as the semiconductor pillar) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant further argues that the gate-all-around structure is not provided to cover at least the channel region of the semiconductor pillar. Examiner respectfully disagrees and notes that Fig. 23c of Zhu shows the gate structure covering a side surface of the entire channel portion. As such, claim 14 stands rejected under 35 U.S.C. 102(a)(1) as detailed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893