DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/17/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19, the limitation “the top contact connected to the second bottom source/drain region of the second plurality of VTFETs” appears to be conflicting with the limitation of claim 15, which claim 19 depends therefrom, reciting “the top contact connected to a top source/drain region of the second plurality of VTFETs”. For example, how a reference # “480B” considering as a top contact as shown in Fig. 4B in the instant application is connected to both the top source/drain region and the bottom source/drain region for the second plurality of VTFETs?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-11, 13-15, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0280474 A1; hereinafter “Wang”).
Regarding claim 6, Wang teaches a semiconductor device comprising:
a first plurality of vertical-transport field-effect transistors (VTFETs) (right-side vertical transport field effect transistors VTFETS as shown in an annotated Fig. 15 below) on a wafer (a substrate 202), each of the first plurality of VTFETs including a gate (a gate stack 212), wherein a distance between centers of the gates in adjacent VTFETs of the first plurality of VTFETs is a first distance that is a contact poly pitch (CPP) (a distance between 212 as a contact poly pitch (CPP) between 212 with 106 therebetween in a x-direction as shown in the annotated Fig. 15 below) (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34);
a second plurality of VTFETs (left-side VTFETs as shown in the annotated Fig. 15 below) adjacent to the first plurality of VTFETs on the wafer, wherein each of the second plurality of VTFETs includes one of the gates (212), wherein a distance between centers of the gates in adjacent VTFETs of the second plurality of VTFETs is the first distance (the CPP between 212 with 106 therebetween in the x-direction for the left-side VTFETs) (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34);
a shared top contact (a common top source/drain metal contact 108), wherein the shared top contact is connected to each top source/drain region (a top source/drain layer 216) of the first plurality of VTFETs and the second plurality of VTFETs (Fig. 15 and paragraphs 36 and 58);
a first bottom source/drain region of the first plurality of VTFETs (a bottom source/drain layer 206 for the right-side VTFETs) extending at least the first distance away from a center of the gate of a first one of the first plurality of VTFETs (a center of 112 for a first one of the right-side VTFETs adjacent to 110), wherein the bottom source/drain region of first plurality of VTFETs is connected to each VTFET of the first plurality of VTFETs (Figs. 1-2 and 15 and paragraph 31);
a second bottom source/drain region of the second plurality of VTFETs (a bottom source/drain layer 206 for the left-side VTFETs), wherein the second bottom source/drain region of second plurality of VTFETs extends across and is connected to each VTFET of the second plurality of VTFETs (Figs. 1-2 and 15 and paragraph 31); and
a contact (a bottom source/drain metal contact 110) connected to the first bottom source/drain region of the first plurality of VTFETs, a center of the contact being positioned at least the first distance away from the center of the gate of the first one of the first plurality of VTFETs that is adjacent to the contact (a center of 110 being positioned at least the first distance away from the center of 212 of the right-side VTFETs adjacent to 110 as shown in the annotated Fig. 15 below) (Figs. 1-2 and 15 and paragraphs 38-39).
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Regarding claim 7, Wang teaches wherein the contact is connected to the first bottom source/drain region of the first plurality of VTFETs on a frontside of the first bottom source/drain region (a frontside of 206) and extends toward a frontside of the VTFETs (a topside of the VTFETs in a z-direction) (Fig. 2).
Regarding claim 8, Wang teaches wherein the contact is connected to the first bottom source/drain region of the first plurality of VTFETs on a backside of the first bottom source/drain region (110 connected to 206 on a backside of 206) and extends toward a backside of the VTFETs (110 in combination with 250 partially extends toward backside of 100 in a z-direction) (Fig. 2).
Regarding claim 9, Wang teaches wherein the first plurality of VTFET are in parallel (the right-side VTFETs are in parallel) (Fig. 15).
Regarding claim 10, Wang teaches wherein the second plurality of VTFET are in parallel (the left-side VTFETs are in parallel) (Fig. 15).
Regarding claim 11, Wang teaches wherein the first plurality of VTFET and the second plurality of VTFET are connected in series (the right-side VTFETs and the left-side VTFETs are in series connection through 108) (Fig. 15).
Regarding claim 13, Wang teaches wherein a width of the contact is greater than the first distance (W2, which is equal to WC, is greater than the CPP of 212) (Fig. 2).
Regarding claim 14, Wang teaches wherein the contact is an output connection (paragraphs 29 and 38).
Regarding claim 15, Wang teaches a semiconductor device comprising:
a first plurality of vertical-transport field-effect transistors transistor (VTFETs) (left-side vertical transport field effect transistors VTFETS) on a wafer (a substrate 202), each of the first plurality of VTFETs including a gate (a gate stack 212), wherein a distance between centers of the gates in adjacent VTFETs in the first plurality of gates is a first distance that is a contact poly pitch (CPP) (a distance between 212 as a contact poly pitch (CPP) between 212 with 106 therebetween in a x-direction) (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34);
a second plurality of VTFETs (right-side VTFETs) on the wafer that are adjacent to the first plurality of VTFETs (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34);
a first bottom source/drain region of the first plurality of VTFETs (a bottom source/drain layer 206 for the left-side VTFETs) extending at least the first distance away from a center of the gate of a first one of the first plurality of VTFETs, wherein the bottom source/drain region of first plurality of VTFETs is connected to each VTFET of the first plurality of VTFETs (Figs. 1-2 and 15 and paragraph 31);
a second bottom source/drain region of the second plurality of VTFETs (a bottom source/drain layer 206 for the right-side VTFETs), wherein the second bottom source/drain region of second plurality of VTFETs extends across and is connected to each VTFET of the second plurality of VTFETs (Figs. 1-2 and 15 and paragraph 31); and
a top contact (a common top source/drain metal contact 108) connected to a top source/drain region (a top source/drain layer 216) of the second plurality of VTFETs (Figs. 1-2 and 15 and paragraphs 36-38), a center of the top contact being positioned at least the first distance away from a center of the gate of a second VTFET of the second plurality of VTFETs that is adjacent to the top contact (a center of 108 being positioned at least the CPP away from a center of 212 of the right-side VTFETs adjacent to 108 in a x-direction as shown in an annotated Fig. 15 below) (Figs. 1-2 and 15 and paragraphs 38-39).
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Regarding claim 17, Wang teaches further comprising: an active region (an active region surrounded by 208) within the first distance adjacent to the first plurality of VTFET and the second plurality of VTFET (Fig. 15 and paragraphs 30-31); wherein the active region connects to a metal line in a first metal layer (a buried power rail (BPR) layer 102); wherein the first bottom source/drain region is connected to the active region (Fig. 15); and wherein the top contact is connected to the active region (Fig. 15).
Regarding claim 18, Wang teaches wherein the first plurality of VTFETs are connected in series (the left-side VTFETs are connected in series with the right-side VTFETs) (Fig. 15).
Regarding claim 20, Wang teaches a third plurality of VTFETs adjacent to the first plurality of VTFETs (top left-side of VTFETs as p-type VTFETs) (Figs. 14 and 16 and paragraph 56-58); and an active region of the third plurality of VTFETs (an active region within 204 under the top left-side p-type VTFETs and covered by 208) (Fig. 16), wherein the active region extends inside the first distance of the second plurality of VTFETs (Fig. 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding claim 16, Wang teaches further comprising: a bottom contact (250) connected to the first bottom source/drain region (Fig. 15 and paragraph 38). Wang does not further teach a metal line in a first metal layer with the top contact (108) (Fig. 15). However, it would have been obvious to one of ordinary skill in the art that the semiconductor device would readily include the metal line structure as a back-end of the line structure such that the metal line structure provide the electrical connection to the top contact (108) for the desired electrical connection.
Regarding claim 19, while Wang does not explicitly teach that the top contact is an output connection, it would have been obvious to one of ordinary skill in the art to utilize the top source/drain metal contact 108 to be the output connection with the bottom source/drain metal contact 110 from Wang as an input connection (Fig. 15) as a design choice (it is noted that the limitation of claim 19 is considered as the top contact connected to the top source/drain region as previously recited. Also see the rejection of claim 19 under 35 U.S.C. 112(b) as discussed above).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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