DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do (US 2020/0144260 A1).
Regarding claim 1, Do teaches a semiconductor device comprising: a plurality of vertical-transport field-effect transistors (VTFETs) (n-type VFETs) on a wafer (100), each of the VTFETs including a gate (each of the n-type VFETs having 18), wherein a distance between centers of the gates in adjacent VTFETs is a first distance that is a contact poly pitch (CPP) (either a contact poly pitch CPP between 18 of adjacent n-type VFETs or a contact poly pitch between 18 with 14_N therebetween) (Figs. 8-9A and paragraphs 43 and 57-58); a bottom source/drain region of a first one of the VTFETs (12_N) extending at least the first distance away from the first one of the VTFETs (Figs. 8-9A and paragraphs 44 and 57-58); and a contact (33) connected to the bottom source/drain region, a center of the contact being positioned at least the first distance away from a center of the gate of the first one of the VTFETs that is adjacent to the contact (a center of 33 being positioned at least the CPP away from a center of one of the n-type VFETs adjacent to 33) (Figs. 8-9A and paragraphs 57-58).
Regarding claim 2, Do teaches wherein the contact is connected to the bottom source/drain region on a frontside of the bottom source/drain region (a frontside of 12_N) and extends toward a frontside of the VTFETs (a topside of the n-type VFETs) (Fig. 9A).
Regarding claim 5, Do teaches wherein the contact is an output connection (33 connecting to 44_O) (paragraph 48).
Claims 1-11, 13-15, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0280474 A1; hereinafter “Wang”).
Regarding claim 1, Wang teaches a semiconductor device comprising: a plurality of vertical-transport field-effect transistors (VTFETs) (vertical transport field effect transistors VTFETS) on a wafer (202), each of the VTFETs including a gate (212), wherein a distance between centers of the gates in adjacent VTFETs is a first distance that is a contact poly pitch (CPP) (a distance between 212 as a contact poly pitch (CPP) between 212 with 106 therebetween in a x-direction) (Figs. 1-2 and paragraphs 1-3 and 30-34); a bottom source/drain region of a first one of the VTFETs (a right-side one of VTFETs having 206) extending at least the first distance away from the first one of the VTFETs (Figs. 1-2 and paragraph 31); and a contact (110) connected to the bottom source/drain region, a center of the contact being positioned at least the first distance away from a center of the gate of the first one of the VTFETs that is adjacent to the contact (a center of 110 being positioned at least the CPP away from a center of 212 of the VTFETs adjacent to 110) (Figs. 1-2 and paragraphs 38-39).
Regarding claim 2, Wang teaches wherein the contact is connected to the bottom source/drain region on a frontside of the bottom source/drain region (a frontside of 206) and extends toward a frontside of the VTFETs (a topside of the VTFETs in a z-direction) (Fig. 2).
Regarding claim 3, Wang teaches wherein the contact is connected to the bottom source/drain region on a backside of the bottom source/drain region (110 connected to 206 on a backside of 206) and extends toward a backside of the VTFETs (110 in combination with 250 partially extends toward backside of 100 in a z-direction) (Fig. 2).
Regarding claim 4, Wang teaches wherein the contact is greater than the first distance (W2, which is equal to WC, is greater than the CPP of 212) (Fig. 2).
Regarding claim 5, Wang teaches wherein the contact is an output connection (paragraphs 29 and 38).
Regarding claim 6, Wang teaches a semiconductor device comprising: a first plurality of vertical-transport field-effect transistors (VTFETs) (right-side vertical transport field effect transistors VTFETS) on a wafer (200), each of the first plurality of VTFETs including a gate (212), wherein a distance between centers of the gates in adjacent VTFETs of the first plurality of VTFETs is a first distance that is a contact poly pitch (CPP) (a distance between 212 as a contact poly pitch (CPP) between 212 with 106 therebetween in a x-direction) (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34); a second plurality of VTFETs (left-side VTFETs) adjacent to the first plurality of VTFETs on the wafer, wherein each of the second plurality of VTFETs includes one of the gates (212), wherein a distance between centers of the gates in adjacent VTFETs of the second plurality of VTFETs is the first distance (the CPP between 212) (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34); a shared top contact (108), wherein the shared top contact is connected to each top source/drain region (216) of the first plurality of VTFETs and the second plurality of VTFETs (Fig. 15 and paragraphs 36 and 58); a bottom source/drain region (206 for the right-side VTFETs) of the first plurality of VTFETs extending at least the first distance away from a center of the gate of a first one of the first plurality of VTFETs, wherein the bottom source/drain region of first plurality of VTFETs is connected to each VTFET of the first plurality of VTFETs (Figs. 1-2 and 15 and paragraph 31); and a contact (110) connected to the bottom source/drain region of the first plurality of VTFETs, a center of the contact being positioned at least the first distance away from a center of the gate of the first one of the first plurality of VTFETs that is adjacent to the contact (a center of 110 being positioned at least the CPP away from a center of 212 of the right-side VTFETs adjacent to 110) (Figs. 1-2 and paragraphs 38-39).
Regarding claim 7, Wang teaches wherein the contact is connected to the bottom source/drain region of the first plurality of VTFETs on a frontside of the bottom source/drain region (a frontside of 206) and extends toward a frontside of the VTFETs (a topside of the VTFETs in a z-direction) (Fig. 2).
Regarding claim 8, Wang teaches wherein the contact is connected to the bottom source/drain region of the first plurality of VTFETs on a backside of the bottom source/drain region (110 connected to 206 on a backside of 206) and extends toward a backside of the VTFETs (110 in combination with 250 partially extends toward backside of 100 in a z-direction) (Fig. 2).
Regarding claim 9, Wang teaches wherein the first plurality of VTFET are in parallel (the right-side VTFETs are in parallel) (Fig. 15).
Regarding claim 10, Wang teaches wherein the second plurality of VTFET are in parallel (the left-side VTFETs are in parallel) (Fig. 15).
Regarding claim 11, Wang teaches wherein the first plurality of VTFET and the second plurality of VTFET are connected in series (the right-side VTFETs and the left-side VTFETs are in series connection through 108) (Fig. 15).
Regarding claim 13, Wang teaches wherein a width of the contact is greater than the first distance (W2, which is equal to WC, is greater than the CPP of 212) (Fig. 2).
Regarding claim 14, Wang teaches wherein the contact is an output connection (paragraphs 29 and 38).
Regarding claim 15, Wang teaches a semiconductor device comprising: a first plurality of vertical-transport field-effect transistors transistor (VTFETs) (left-side vertical transport field effect transistors VTFETS) on a wafer (200), each of the first plurality of VTFETs including a gate (212), wherein a distance between centers of the gates in adjacent VTFETs in the first plurality of gates is a first distance that is a contact poly pitch (CPP) (a distance between 212 as a contact poly pitch (CPP) between 212 with 106 therebetween in a x-direction) (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34); a second plurality of VTFETs (right-side VTFETs) on the wafer that are adjacent to the first plurality of VTFETs (Figs. 1-2 and 15 and paragraphs 1-3 and 30-34); a bottom source/drain region of the first plurality of VTFETs (the left-side VTFETs having 206) extending at least the first distance away from a center of the gate of a first VTFET of the first plurality of VTFETs; and a top contact (108) connected to a top source/drain region (216) of the second plurality of VTFETs (Figs. 1-2 and 15 and paragraphs 36-38), a center of the top contact being positioned at least the first distance away from a center of the gate of a second VTFET of the second plurality of VTFETs that is adjacent to the top contact (a center of 108 being positioned at least the CPP away from a center of 212 of the right-side VTFETs adjacent to 108 in a x-direction) (Figs. 1-2 and 15 and paragraphs 38-39).
Regarding claim 17, Wang teaches further comprising: an active region (an active region surrounded by 208) within the first width adjacent to the first plurality of VTFET and the second plurality of VTFET (Fig. 15 and paragraphs 30-31); wherein the active region connects to a metal line in a first metal layer (102); wherein the bottom source/drain region is connected to the active region (Fig. 15); and wherein the top contact is connected to the active region (Fig. 15).
Regarding claim 18, Wang teaches wherein the first plurality of VTFETs are connected in series (the left-side VTFETs are connected in series with the right-side VTFETs) (Fig. 15).
Regarding claim 20, Wang teaches a third plurality of VTFETs adjacent to the first plurality of VTFETs (top left-side of VTFETs as p-type VTFETs) (Figs. 14 and 16 and paragraph 56-58); and an active region of the third plurality of VTFETs (an active region within 204 under the top left-side p-type VTFETs and covered by 208) (Fig. 16), wherein the active region extends inside the first distance of the second plurality of VTFETs (Fig. 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding claim 16, Wang teaches further comprising: a bottom contact (250) connected to the bottom source/drain region (Fig. 15 and paragraph 38). Wang does not further teach a metal line in a first metal layer with the top contact (110) (Fig. 15). However, it would have been obvious to one of ordinary skill in the art that the semiconductor device would readily include the metal line structure as a back-end of the line structure such that the metal line structure provide the electrical connection to the top contact (110) for the desired electrical connection.
Regarding claim 19, while Wang does not explicitly teach that the top contact is an output connection, it would have been obvious to one of ordinary skill in the art to utilize the top source/drain metal contact 108 to be the output connection with the bottom source/drain metal contact 110 from Wang as an input connection (Fig. 15) as a design choice.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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