Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/27/2026 has been entered.
Remarks
This Office Action is responsive to Applicants' Amendment filed on February 27, 2026, in which claims 1 and 11 are currently amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to rejection of claims 1-20 under 35 U.S.C. 102/103 based on amendment have been considered. The argument is moot in view of a new ground of rejection set forth below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 10, "being reconfigurable, via hardware elements within the ASIC and without resynthesis of the ASIC" does not contain support in the instant specification. The instant specification does not mention resynthesis at all such that one of ordinary skill in the art could not reasonably determine what is meant by resynthesis, or how the ASIC is reconfigurable without resynthesis. For at least these reasons the claim limitation is seen as introducing new matter.
The remaining claims are rejected with respect to their dependence on the rejected claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 and 10 are rejected under U.S.C. §103 as being unpatentable over the combination of Li (“The Storage Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC”, 2018) and Nakahara (“ReNA: A Reconfigurable Neural-Network Accelerator for AI Edge Computing”, 2021).
Regarding claim 1, Li teaches An artificial intelligence (AI) network on an application specific integrated circuit (ASIC) operable as a reconfigurable multilayer image processor comprising:([Abstract] "The Storage Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC […] we propose a new high performance multi-precision reconfigurable architecture (MPRA) and optimize it for recent CNNs" [p. 326] "the AlexNet convolution layers")
multiple layers comprising an input layer that receives an image input, an output layer that produces an image output, and at least one intermediate layer between the input layer and the output layer; ([p. 324] "In Fig.2 it is shown that, 56 × 56 image is applied as input to, 3×3 convolution layer of AlexNet" [p. 325] "As shown in Fig. 3, 28 × 28 image is applied as input to, 5×5 convolution layer of AlexNet." [p. 324] "The output results, representing different output feature maps")
each layer comprising a plurality of multiplier-accumulator (MAC) units; and([p. 324 §3] "In Fig.2 it is shown that, 56 × 56 image is applied as input to, 3×3 convolution layer of AlexNet […] When the 3 × 3 convolutions are conducted, the 24 PEs simultaneously read the same data corresponding to the 3 rows by 3 columns of input image data" [p. 326] "The designed structure consists of combination of 24 parallel PEs where each engine can contain 9(16bit×16bit) MAC or 18(16bit×8bit) MAC, or 36(8bit×8bit) MAC" Li explicitly discloses that each layer is processed using a plurality of PEs, each PE having a plurality of MAC units)
at least one layer is partitioned into a plurality of blocks of MAC units,([p. 323] "The PE array consists of 24 parallel PEs" [p. 324 §3] "In Fig.2 it is shown that, 56 × 56 image is applied as input to, 3×3 convolution layer of AlexNet […] When the 3 × 3 convolutions are conducted, the 24 PEs simultaneously read the same data
corresponding to the 3 rows by 3 columns of input image data" [p. 326] "The designed structure consists of combination of 24 parallel PEs where each engine can contain 9(16bit×16bit) MAC or 18(16bit×8bit) MAC, or 36(8bit×8bit) MAC" PE interpreted as block of MAC units)
the plurality of blocks of MAC units being reconfigurable, via hardware elements within the ASIC ([p. 324] "By reconfiguring the PE array, the combination of 3 PEs can perform a 5×5 convolution operation, therefore, this array can simultaneously perform eight 5×5 convolutions. Therefore, the PE array is able to calculate different shapes of convolutions through combinations of PEs")
to operate independently or to operate in one or more combinations of blocks of MAC units, wherein reconfiguration of the plurality of blocks of MAC units via the hardware elements within the ASIC executes changes in an AI model for the image processing.([p. 323] "CNNs models also adopts different kernel sizes" [p. 324] "single PE can compute a 3×3(16-bit) convolution or four 3×3(8-bit) convolution. By reconfiguring the PE array, the combination of 3 PEs can perform a 5×5 convolution operation").
However, Li does not explicitly teach and without resynthesis of the ASIC, .
Nakahara, in the same field of endeavor, teaches and without resynthesis of the ASIC ([p. 202] "connections between PBs are reconfigurable by the configuration register […] without retraining" [p. 203] "This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters.").
Li as well as Nakahara are directed towards reconfigurable ASICs for CNN (specifically AlexNet). Therefore, Li as well as Nakahara are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Li with the teachings of Nakahara by performing reconfiguration at runtime through configuration registers (without resynthesis). Nakahara provides as additional motivation for combination ([p. 205] “Retraining incurs costs in terms of time and equipment. Therefore, the ReNA method of processing fully connected layers is useful, because it improves performance without retraining”).
Regarding claim 2, the combination of Li and Nakahara teaches The AI network of claim 1, wherein the image processing comprises image scaling.(Li [p. 323] "The PE array consists of 24 parallel PEs" [p. 324 §3] "In Fig.2 it is shown that, 56 × 56 image is applied as input to, 3×3 convolution layer of AlexNet […] When the 3 × 3 convolutions are conducted, the 24 PEs simultaneously read the same data
corresponding to the 3 rows by 3 columns of input image data" [p. 326] "The designed structure consists of combination of 24 parallel PEs where each engine can contain 9(16bit×16bit) MAC or 18(16bit×8bit) MAC, or 36(8bit×8bit) MAC" Alexnet scales images by definition).
Regarding claim 3, the combination of Li and Nakahara teaches The AI network of claim 1, wherein the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units enables implementation of one or more virtual layers in addition to the multiple layers.(Nakahara [p. 203] "PB can independently perform activation transfers from SRAM, the operation, and the output transfer to SRAM, and so can always perform calculations [...] Figure 5 shows processing in the convolutional layer for a3×3 PBarray. First, row activations for different channels are transferred to the PB array (Figure 5(a)). Note that the PB connection forms a circle" [p. 204] "The PB connection connects the PB performing calculations to a daisy chain (Figure 6(b)). Each PB performs MAC operations using the transferred weight and PB activation. [...] the shortest daisy chain is constructed by changing the PB connection, minimizing the number of calculations." virtual mapping in FIG. 5 and 6 interpreted as virtual layers).
Regarding claim 4, the combination of Li and Nakahara teaches The AI network of claim 1, wherein the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units enables reconfiguration of an input depth size, output feature map size, or a combination thereof for the at least one layer partitioned into the plurality of blocks of MAC units.(Li [p. 324] "By reconfiguring the PE array, the combination of 3 PEs can perform a 5×5 convolution operation, therefore, this array can simultaneously perform eight 5×5 convolutions. Therefore, the PE array is able to calculate different shapes of convolutions through combinations of PEs").
Regarding claim 5, the combination of Li and Nakahara teaches The AI network of claim 4, wherein different blocks of MAC units in the plurality of blocks of MAC units support different input depth sizes, different output feature map sizes, or a combination thereof.(Li [p. 324] "By reconfiguring the PE array, the combination of 3 PEs can perform a 5×5 convolution operation, therefore, this array can simultaneously perform eight 5×5 convolutions. Therefore, the PE array is able to calculate different shapes of convolutions through combinations of PEs").
Regarding claim 6, the combination of Li and Nakahara teaches The AI network of claim 1, wherein multiple layers are partitioned into the plurality of blocks of MAC units.(Nakahara [p. 202] "The PB array size and memory size are determined so that AlexNet [12] can be implemented." [p. 204] "Fig. 5. Example of convolutional layer processing […] Fig. 6. Example of fully connected layer processing." See also FIG. 5 and FIG. 6).
Regarding claim 7, the combination of Li and Nakahara teaches The AI network of claim 1, wherein each MAC unit comprises a two-dimensional (2D) filter.(Nakahara [p. 3] "The size of the PB array is 64 × 64 […] Figure 5 shows processing in the convolutional layer for a3×3 Pb array" See FIG. 5-7 which shows MAC unit 2D filter).
Regarding claim 10, the combination of Li and Nakahara teaches The AI network of claim 1, wherein each layer comprises sets of memories associated with each layer for tap generation, wherein any combination of blocks of MAC units is receivable by any set of memories and a tap output from any set of memories is receivable by any combination of blocks of MAC units.(Nakahara [p. 203] "The other function receives activations from SRAM during calculations. The PB has two registers for storing activations, one storing activations from PB connections and the other storing activations from SRAM. The select unit determines which register stores which activation. Thus, while one register supplies the MAC operator with operation activations, the other can supply the next activation from SRAM to the PB" See also FIG. 3(a-b) showing processing block with registers with bidirectional accessibility of surrounding PBs).
Claims 8 and 9 are rejected under U.S.C. §103 as being unpatentable over the combination of Li and Nakahara as evidenced by Krizhevsky (“ImageNet Classification with Deep Convolutional Neural Networks”, 2012).
Regarding claim 8, the combination of Li and Nakahara teaches The AI network of claim 1, wherein: each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs; and(Nakahara [p. 203] "chi is the number of channel inputs, cho is the channel output, i and j are x- and y-axes of the input feature map, k is the filter size, w is the convolution coefficient, u is the output feature map, and bcho is bias" [p. 205] "Table I shows estimated results for processing speed and power consumption when AlexNet is executed" input feature map is from preceding layer.)
the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units enables at least one of: implementation of one or more virtual layers between the input layer and the output layer, (Nakahara [pp. 202-203] "Using these lines, the PB gets new activations for each calculation, while supplying activations for other PBs. This allows data sharing between PBs, reducing the amount of data transfer from SRAM. The direction of data reception can be dynamically reconfigured for each PB. This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters" Layer-wise PB arrangement interpreted as virtual layer. PB arrangement for intermediate AlexNet layer interpreted as virtual layer between the input and output layer.)
reconfiguration of the input depth size of the at least one intermediate layer, reconfiguration of the output feature map size of the at least one intermediate layer, or a combination thereof.(Nakahara [p. 203] "When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations").
While the combination of Li and Nakahara doesn't explicitly teach each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs;
Both Li and Nakahara implement the well-known AlexNet CNN model by Krizhevsky, AlexNet not only relies upon sequential model layers including intermediate layers but also explicitly describes the importance of the intermediate layers.
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Krizhevsky, in the same field of endeavor, teaches each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs; and ([pp. 4-5] "The first convolutional layer filters the 224×224×3 input image with 96 kernels of size 11×11×3 with a stride of 4 pixels (this is the distance between the receptive field centers of neighboring neurons in a kernel map). The second convolutional layer takes as input the (response-normalized and pooled) output of the first convolutional layer and filters it with 256 kernels of size 5 × 5 × 48" [p. 2] “we found that removing any convolutional layer (each of which contains no more than 1% of the model’s parameters) resulted in inferior performance.”).
The combination of Li and Nakahara as well as Krizhevsky are directed towards AlexNet convolutional neural networks. Therefore, the combination of Li and Nakahara as well as Krizhevsky are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of the combination of Li and Nakahara with the teachings of Krizhevsky by using the AlexNet model architecture. Both Li and Nakahara explicitly implement AlexNet and Krizhevsky reinforces the architecture.
Regarding claim 9, the combination of Li, Nakahara and Krizhevsky teaches The AI network of claim 8, wherein the image output comprises a plurality of pixels for each respective pixel in the image input.(Li [p. 324] "n Fig.2 it is shown that, 56 × 56 image is applied as input to, 3×3 convolution layer of AlexNet. All 56 rows of image data are grouped into set of eight rows (r0… r7), where each set contains seven independent lines of pixels i.e. (a0 to a6) and one redundant line (a7). The redundant line comes from the first line of the next set. All entities of same column in one set are stored sequentially in the Data Buffer, as shown in the figure. First column entities as denoted by D0 are stored in the Data Buffer unit at address 0 and similarly others can be stored, this facilitates data reuse and reduces the time computations. When the 3 × 3 convolutions are conducted, the 24 PEs simultaneously read the same data corresponding to the 3 rows by 3 columns of input image data, and different parameter values corresponding to different filters. The output results, representing different output feature maps, are stored in the corresponding P_SRAM units.").
Claims 11-20 are rejected under U.S.C. §103 as being unpatentable over the combination of Nakahara and Krizhevsky.
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Regarding claim 11, Nakahara teaches A method of reconfiguring an artificial intelligence (AI) network on an application specific integrated circuit (ASIC) operable as a reconfigurable multilayer image processor, comprising:([p. 201] "we propose a reconfigurable neural network accelerator (ReNA), an AI chip that can process convolutional and fully connected layers with the same structure by reconfiguring the circuit […] designed as application-specific integrated circuits for processing convolutional neural networks" [p. 205] "We performed layout design with a TSMC 22-nm process standard cell")
receiving an artificial intelligence (AI) model for image processing; configuring the AI network based on the AI model, ([p. 2 §B.1] "The PB array size and memory size are determined so that AlexNet [12] can be implemented.")
wherein the AI network comprises: multiple layers comprising an input layer that receives an image input, an output layer that produces an image output, and at least one intermediate layer between the input layer and the output layer, each layer comprising a plurality of multiplier-accumulator (MAC) units;([p. 202] "The PB array size and memory size are determined so that AlexNet [12] can be implemented" [p. 203] "chi is the number of channel inputs, cho is the channel output, i and j are x- and y-axes of the input feature map, k is the filter size, w is the convolution coefficient, u is the output feature map, and bcho is bias. In the convolutional layer, one datum is used to calculate multiple outputs. Therefore, ReNA reduces data transfer by sharing data with multiple PBs, allowing highly parallel operations with limited bandwidth [...] When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations" See also Table I, FIG. 5 and FIG. 6 which show the layers mapped to PB arrays having MAC units)
at least one layer being partitioned into a plurality of blocks of MAC units, ([p. 202 §B.1] "Figure 2 shows a block diagram for ReNA. ReNA has three SRAM types, those for the input (MEMX), weight (MEMW), and controller (MEMI). PB ARRAY is composed of 64 ×64 processing blocks (PBs) with multiply accumulate (MAC) circuits […] This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters." See also FIG. 5 and FIG. 6)
the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units;([p. 203] "PB can independently perform activation transfers from SRAM, the operation, and the output transfer to SRAM, and so can always perform calculations [...] Figure 5 shows processing in the convolutional layer for a3×3 PBarray. First, row activations for different channels are transferred to the PB array (Figure 5(a)). Note that the PB connection forms a circle" [p. 204] "The PB connection connects the PB performing calculations to a daisy chain (Figure 6(b)). Each PB performs MAC operations using the transferred weight and PB activation. [...] the shortest daisy chain is constructed by changing the PB connection, minimizing the number of calculations.")
receiving changes in the AI model for the image processing; and reconfiguring the plurality of blocks of MAC units, via hardware elements within the ASIC and without resynthesis of the ASIC, to execute the changes in the AI model for the image processing via the hardware elements within the ASIC.([p. 202] "connections between PBs are reconfigurable by the configuration register. The controller supports microcode instructions and generates control signals for different processing layers." [p. 203] "This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters." [p. 205] "the ReNA method of processing fully connected layers is useful, because it improves performance without retraining" Different processing layers and layer hyperparameters are interpreted as changes).
However, Nakahara does not explicitly teach multiple layers comprising an input layer that receives an image input, an output layer that produces an image output, and at least one intermediate layer between the input layer and the output layer,.
Krizhevsky, in the same field of endeavor, teaches multiple layers comprising an input layer that receives an image input, an output layer that produces an image output, and at least one intermediate layer between the input layer and the output layer,([p. 5] "The second convolutional layer takes as input the (response-normalized and pooled) output of the first convolutional layer and filters it with 256 kernels of size 5 × 5 × 48. The third, fourth, and fifth convolutional layers are connected to one another without any intervening pooling or normalization layers. The third convolutional layer has 384 kernels of size 3 × 3 × 256 connected to the (normalized, pooled) outputs of the second convolutional layer. The fourth convolutional layer has 384 kernels of size 3 × 3 × 192 , and the fifth convolutional layer has 256 kernels of size 3 × 3 × 192. The fully-connected layers have 4096 neurons each" See FIG. 2).
Nakahara as well as Krizhevsky are directed towards AlexNet convolutional neural networks. Therefore, Nakahara as well as Krizhevsky are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Nakahara with the teachings of Krizhevsky by using the AlexNet model architecture. Nakahara explicitly implements AlexNet and Krizhevsky reinforces the architecture.
Regarding claim 12, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein the image processing comprises image scaling.(Nakahara [p. 302] "The PB array size and memory size are determined so that AlexNet [12] can be implemented" AlexNet scales image by definition).
Regarding claim 13, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units enables implementation of one or more virtual layers in addition to the multiple layers.(Nakahara [p. 203] "PB can independently perform activation transfers from SRAM, the operation, and the output transfer to SRAM, and so can always perform calculations [...] Figure 5 shows processing in the convolutional layer for a3×3 PBarray. First, row activations for different channels are transferred to the PB array (Figure 5(a)). Note that the PB connection forms a circle" [p. 204] "The PB connection connects the PB performing calculations to a daisy chain (Figure 6(b)). Each PB performs MAC operations using the transferred weight and PB activation. [...] the shortest daisy chain is constructed by changing the PB connection, minimizing the number of calculations." virtual mapping in FIG. 5 and 6 interpreted as virtual layers).
Regarding claim 14, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein reconfiguring the plurality of blocks of MAC units reconfigures an input depth size, output feature map size, or a combination thereof for the at least one layer partitioned into the plurality of blocks of MAC units.(Nakahara [p. 203] "This process is per formed multiple times if the filter size k is larger than 1 or if the input channels are larger than the array size. After the operation, outputs of one row of different channels are generated (Figure 5(d)). This process is repeated until all outputs have been computed. When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations. Thus, it can process a layer of any hyperparameter. When the image size of the input feature map is smaller than the array size, multiple lines of output can be simultaneously computed. Therefore, ReNA can process input feature maps of various sizes with high parallelism").
Regarding claim 15, the combination of Nakahara and Krizhevsky teaches The method of claim 14, wherein different blocks of MAC units in the plurality of blocks of MAC units support different input depth sizes, different output feature map sizes, or a combination thereof.(Nakahara [p. 203] "This process is per formed multiple times if the filter size k is larger than 1 or if the input channels are larger than the array size. After the operation, outputs of one row of different channels are generated (Figure 5(d)). This process is repeated until all outputs have been computed. When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations. Thus, it can process a layer of any hyperparameter. When the image size of the input feature map is smaller than the array size, multiple lines of output can be simultaneously computed. Therefore, ReNA can process input feature maps of various sizes with high parallelism").
Regarding claim 16, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein multiple layers are partitioned into the plurality of blocks of MAC units.(Nakahara [p. 204] "Fig. 5. Example of convolutional layer processing […] Fig. 6. Example of fully connected layer processing." See also FIG. 5 and FIG. 6).
Regarding claim 17, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein each MAC unit comprises a two-dimensional (2D) filter.(Nakahara [p. 3] "The size of the PB array is 64 × 64 […] Figure 5 shows processing in the convolutional layer for a3×3 Pb array" See FIG. 5-7 which shows MAC unit 2D filter).
Regarding claim 18, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein: each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs;(Krizhevsky [pp. 4-5] "The first convolutional layer filters the 224×224×3 input image with 96 kernels of size 11×11×3 with a stride of 4 pixels (this is the distance between the receptive field centers of neighboring neurons in a kernel map). The second convolutional layer takes as input the (response-normalized and pooled) output of the first convolutional layer and filters it with 256 kernels of size 5 × 5 × 48. The third, fourth, and fifth convolutional layers are connected to one another without any intervening pooling or normalization layers. The third convolutional layer has 384 kernels of size 3 × 3 × 256 connected to the (normalized, pooled) outputs of the second convolutional layer. The fourth convolutional layer has 384 kernels of size 3 × 3 × 192 , and the fifth convolutional layer has 256 kernels of size 3 × 3 × 192. The fully-connected layers have 4096 neurons each." See FIG. 2)
reconfiguring the plurality of blocks of MAC units to execute the changes in the AI model for the image processing comprises arranging the plurality of blocks of MAC units to operate independently or to operate in one or more combinations of blocks of MAC units to enable at least one of implementation of one or more virtual layers between the input layer and the output layer, reconfiguration of the input depth size of the at least one intermediate layer, reconfiguration of the output feature map size of the at least one intermediate layer, or a combination thereof.(Nakahara [p. 202] "connections between PBs are reconfigurable by the configuration register. The controller supports microcode instructions and generates control signals for different processing layers." [p. 203] "This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters." [p. 205] "the ReNA method of processing fully connected layers is useful, because it improves performance without retraining" Different processing layers and layer hyperparameters are interpreted as changes).
Regarding claim 19, the combination of Nakahara and Krizhevsky teaches The method of claim 18, wherein the image output comprises a plurality of pixels for each respective pixel in the image input. (Krizhevsky [pp. 4-5] "The first convolutional layer filters the 224×224×3 input image with 96 kernels of size 11×11×3 with a stride of 4 pixels (this is the distance between the receptive field centers of neighboring neurons in a kernel map). The second convolutional layer takes as input the (response-normalized and pooled) output of the first convolutional layer and filters it with 256 kernels of size 5 × 5 × 48").
Regarding claim 20, the combination of Nakahara and Krizhevsky teaches The method of claim 11, wherein each layer comprises sets of memories associated with each layer for tap generation, wherein any combination of blocks of MAC units is receivable by any set of memories and a tap output from any set of memories is receivable by any combination of blocks of MAC units.(Nakahara [p. 203] "The other function receives activations from SRAM during calculations. The PB has two registers for storing activations, one storing activations from PB connections and the other storing activations from SRAM. The select unit determines which register stores which activation. Thus, while one register supplies the MAC operator with operation activations, the other can supply the next activation from SRAM to the PB" See also FIG. 3(a-b) showing processing block with registers with bidirectional accessibility of surrounding PBs).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (“Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices”, 2019) is directed towards a reconfigurable ASIC for convolutional neural networks, the reconfigurable ASIC having arrays of MAC units.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY VINCENT BOSTWICK whose telephone number is (571)272-4720. The examiner can normally be reached M-F 7:30am-5:00pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Miranda Huang can be reached on (571)270-7092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIDNEY VINCENT BOSTWICK/Examiner, Art Unit 2124
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