Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
This Office Action is responsive to Applicants' Amendment filed on July 15, 2026, in which claims 1, 5, 11, and 15 are currently amended. Claims 3, 4, 13, and 14 are canceled. Claims 1, 2, 5-12, and 15-20 are currently pending.
Response to Arguments
The rejections to claims 13-20 under 35 U.S.C. § 112(a) are hereby withdrawn, as necessitated by applicant's amendments and remarks made to the rejections.
Applicant’s arguments with respect to rejection of claims 1, 2, 5-12, and 15-20 under 35 U.S.C. 103 based on amendment have been considered and are persuasive. The argument is moot in view of a new ground of rejection set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5-12, and 15-20 are rejected under U.S.C. §103 as being unpatentable over the combination of Boesch (US20180189641A1) and Nakahara (“ReNA: A Reconfigurable Neural-Network Accelerator for AI Edge Computing”, 2021).
Regarding claim 1, Boesch teaches An artificial intelligence (AI) network on an application specific integrated circuit (ASIC) ([¶0135] "The illustrated SoC 110 includes a plurality of SoC controllers 120, a configurable accelerator framework (CAF) 400 (e.g., an image and DCNN co-processor subsystem)" [¶0133] "at least part of the SoC 110, and additionally more or fewer circuits of the SoC 110 and mobile device 100, may be provided in an integrated circuit" Boesch explicitly describes a dedicated integrated circuit for the specific application of neural network processing)
operable as a reconfigurable multilayer image processor comprising:([¶0135] "The illustrated SoC 110 includes a plurality of SoC controllers 120, a configurable accelerator framework (CAF) 400 (e.g., an image and DCNN co-processor subsystem)" [¶0071] "The reconfigurable dataflow accelerator fabric allows the definition of any desirable, determined number of concurrent, virtual processing chains at run time")
multiple layers comprising an input layer that receives an image input, ([¶0316] "the SoC 110 is enabled to perform image recognition on input image data." [¶0318] "processing of an image through the DCNN layers")
an output layer that produces an image output, ([¶0044] "the pooled output map in FIG. 1" [¶0316] "to perform image recognition on input image data." [¶0318] "processing of an image through the DCNN layers" Any output resulting from the input image is interpreted as an image output)
and at least one intermediate layer between the input layer and the output layer; ([¶0316] "the SoC 110 is enabled to perform image recognition on input image data." [¶0318] "processing of an image through the DCNN layers" [¶0062] "The first convolutional layer CL1 in the AlexNet architecture of FIG. 1A filters a 224×224×3 input image with 96 kernels of size 11×11×3 with a stride of 4 pixels. This stride is the distance between the receptive field centers of neighboring neurons in a kernel map. The second convolutional layer CL2 takes as input the response-normalized and pooled output of the first convolutional layer CL1 and filters the output of the first convolutional layer with 256 kernels of size 5×5×48. The third, fourth, and fifth convolutional layers CL3, CL4, CL5 are connected to one another without any intervening pooling or normalization layers. The third convolutional layer CL3 has 384 kernels of size 3×3×256 connected to the normalized, pooled outputs of the second convolutional layer CL2. The fourth convolutional layer CL4 has 384 kernels of size 3×3×192, and the fifth convolutional layer CL5 has 256 kernels of size 3×3×192. The fully connected layers have 4096 neurons each.")
each layer comprising a plurality of multiplier-accumulator (MAC) units; and([¶0073] " the configuration of a CA is defined manually for each DCNN layer" [¶0156] "A different acceptably optimal configuration of CAs 600 in the CAF 400 is determined for each DCNN layer. These configurations may be determined or adjusted using a holistic tool that starts with a DCNN description format, such as Caffe′ or TensorFlow" [¶0072] "The CA includes a line buffer to fetch a plurality (e.g., up to 12) of feature map data words in parallel with a single memory access. A register based kernel buffer provides a plurality (e.g., up to 36 read ports), while a plurality (e.g., 36) of multi-bit (e.g., 16-bit) fixed point multiply-accumulate (MAC) units perform a plurality (e.g., up to 36) of MAC operations per clock cycle" [¶0265] "each MAC cluster contains three (3) MAC units ")
at least one layer is partitioned into a plurality of blocks of MAC units,([¶0265] "the CA MAC units 620 are arranged to include a stack of 12 MAC clusters of which each MAC cluster contains three (3) MAC units and wherein each MAC unit is capable of performing one 16-bit MAC operation per cycle.")
the plurality of blocks of MAC units being reconfigurable, via multiplexers ([¶0266] " the CA feature buffer switch 628 includes a set of programmable multiplexers")
and layer tap selectors within the ASIC([¶0266] "The CA feature switch 628 allows various ones of the MAC units of CA MAC 620 (e.g., each MAC cluster) to select a particular output port (e.g., one of the 12 output ports) of the fifth CA internal buffer 618 feature strip buffer. The selected output port will correspond to a particular feature lines or row." [¶0197] "A selection mechanism 508 is arranged to determine which input data is passed through the data switch 506. That is, based on the selection mechanism 508, the input data from one of input ports A, B, C, D is passed through the data switch 506 to an output of the data switch 506. The output data will be passed on NA . . . D unidirectional communication path conduits, which will match the number of unidirectional communication path conduits of the selected input port." [¶0198] "The selection mechanism 508 is directed according to stream switch configuration logic 510" stream switch 500 and feature switch 628 interpreted as layer tap selectors within the ASIC. Both are responsible for routing layer stream data)
to operate independently or to operate in one or more combinations of blocks of MAC units, ([¶0236] "the 5×5 kernel of Layer 2 in Table 5 can be handled by chaining two MAC clusters. In CAF 400, this feature may be automatically applied when multiple clusters of the same kernel are assigned to the same processing row." For Layer 2's 5x5 kernel, Boesch explicitly combines two MAC clusters. More generally, CA 600 can select a number N of two or more clusters and chain them to produce an output value)
wherein reconfiguration of the plurality of blocks of MAC units via the multiplexers and layer tap selectors within the ASIC executes changes in an AI model for the image processing([¶0071] "The reconfigurable dataflow accelerator fabric allows the definition of any desirable, determined number of concurrent, virtual processing chains at run time" [¶0119] "FIG. 7 is a high level block diagram illustrating the path of data for training a deep convolution neural network (DCNN) and configuring a system on chip (SoC) with the trained DCNN")
by implementing at least one of: one or more virtual layers in addition to the multiple layers; or reconfiguration of an input depth size, output feature map size, or a combination thereof for the at least one layer partitioned into the plurality of blocks of MAC units([¶0072] "Kernel sets may be partitioned in batches and processed sequentially" [¶0232] "the batch may divide the number of channels by an integer number" partitioning kernels into batches interpreted as reconfiguration of an input depth/channel size).
While Boesch explicitly describes a dedicated integrated circuit for the specific application of neural network processing, Boesch does not explicitly use the term application specific integrated circuit (ASIC).
Nakahara, in the same field of endeavor, teaches an application specific integrated circuit (ASIC) ([p. 201] "we propose a reconfigurable neural network accelerator (ReNA), an AI chip that can process convolutional and fully connected layers with the same structure by reconfiguring the circuit […] designed as application-specific integrated circuits for processing convolutional neural networks" [p. 205] "We performed layout design with a TSMC 22-nm process standard cell").
Boesch as well as Nakahara are directed towards reconfigurable integrated circuits for CNN (specifically AlexNet). Therefore, Boesch as well as Nakahara are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Boesch with the teachings of Nakahara by calling the integrated circuit an ASIC. Nakahara provides as additional motivation for combination ([p. 201] "we propose a reconfigurable neural network accelerator (ReNA), an AI chip that can process convolutional and fully connected layers with the same structure by reconfiguring the circuit […] designed as application-specific integrated circuits for processing convolutional neural networks"). This motivation for combination also applies to the remaining claims which depend on this combination.
Regarding claim 2, the combination of Boesch and Nakahara teaches The AI network of claim 1, wherein the image processing comprises image scaling.(Boesch [¶0011] "In FIG. 1C, several variations of different forms of ones and zeroes are shown. In these images, the average human viewer would easily recognize that the particular numeral is translated or scaled" [¶0062] "The first convolutional layer CL1 in the AlexNet architecture of FIG. 1A" Alexnet scales images by definition).
Regarding claim 5, the combination of Boesch and Nakahara teaches The AI network of claim 1, wherein different blocks of MAC units in the plurality of blocks of MAC units support different input depth sizes, different output feature map sizes, or a combination thereof.(Nakahara [p. 203] "This process is per formed multiple times if the filter size k is larger than 1 or if the input channels are larger than the array size. After the operation, outputs of one row of different channels are generated (Figure 5(d)). This process is repeated until all outputs have been computed. When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations. Thus, it can process a layer of any hyperparameter. When the image size of the input feature map is smaller than the array size, multiple lines of output can be simultaneously computed. Therefore, ReNA can process input feature maps of various sizes with high parallelism").
Regarding claim 6, the combination of Boesch and Nakahara teaches The AI network of claim 1, wherein multiple layers are partitioned into the plurality of blocks of MAC units.(Nakahara [p. 202] "The PB array size and memory size are determined so that AlexNet [12] can be implemented." [p. 204] "Fig. 5. Example of convolutional layer processing […] Fig. 6. Example of fully connected layer processing." See also FIG. 5 and FIG. 6).
Regarding claim 7, the combination of Boesch and Nakahara teaches The AI network of claim 1, wherein each MAC unit comprises a two-dimensional (2D) filter.(Nakahara [p. 3] "The size of the PB array is 64 × 64 […] Figure 5 shows processing in the convolutional layer for a3×3 Pb array" See FIG. 5-7 which shows MAC unit 2D filter).
Regarding claim 8, the combination of Boesch and Nakahara teaches The AI network of claim 1, wherein: each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs; and(Nakahara [p. 203] "chi is the number of channel inputs, cho is the channel output, i and j are x- and y-axes of the input feature map, k is the filter size, w is the convolution coefficient, u is the output feature map, and bcho is bias" [p. 205] "Table I shows estimated results for processing speed and power consumption when AlexNet is executed" input feature map is from preceding layer.)
each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs; and(Boesch [¶0224] " Feature data in many cases consists of two or more channels of two-dimensional data structure" [¶0225] "kernel depth is often identical to the number of channels of the feature data set that will be processed." [¶0229] " the feature input data for the next layer is generated" See also Table 5 showing the feature sizes)
the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units enables at least one of: implementation of one or more virtual layers between the input layer and the output layer, (Nakahara [pp. 202-203] "Using these lines, the PB gets new activations for each calculation, while supplying activations for other PBs. This allows data sharing between PBs, reducing the amount of data transfer from SRAM. The direction of data reception can be dynamically reconfigured for each PB. This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters" Layer-wise PB arrangement interpreted as virtual layer. PB arrangement for intermediate AlexNet layer interpreted as virtual layer between the input and output layer.)
reconfiguration of the input depth size of the at least one intermediate layer, reconfiguration of the output feature map size of the at least one intermediate layer, or a combination thereof. (Nakahara [p. 203] "When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations").
Regarding claim 9, the combination of Boesch and Nakahara teaches The AI network of claim 8, wherein the image output comprises a plurality of pixels for each respective pixel in the image input.(Boesch [¶0224] "feature data comprises image frames and associated pixel data of the image frames" [¶0232] "the feature data of Layer 3 (Table 5) can be divided by 16, which will generate 16 feature batches of 13×13×16 pixels and 16 kernel batches of 3×3×16 for one kernel [...] in Layer 2a, the CA 600 will perform convolution operation on six (6) feature batches with 27×27×8 pixels").
Regarding claim 10, the combination of Boesch and Nakahara teaches The AI network of claim 1, wherein each layer comprises sets of memories associated with each layer for tap generation, wherein any combination of blocks of MAC units is receivable by any set of memories and a tap output from any set of memories is receivable by any combination of blocks of MAC units.(Nakahara [p. 203] "The other function receives activations from SRAM during calculations. The PB has two registers for storing activations, one storing activations from PB connections and the other storing activations from SRAM. The select unit determines which register stores which activation. Thus, while one register supplies the MAC operator with operation activations, the other can supply the next activation from SRAM to the PB" See also FIG. 3(a-b) showing processing block with registers with bidirectional accessibility of surrounding PBs).
Regarding claim 11, Boesch teaches A method of reconfiguring an artificial intelligence (AI) network on an application specific integrated circuit (ASIC) ([¶0135] "The illustrated SoC 110 includes a plurality of SoC controllers 120, a configurable accelerator framework (CAF) 400 (e.g., an image and DCNN co-processor subsystem)" [¶0133] "at least part of the SoC 110, and additionally more or fewer circuits of the SoC 110 and mobile device 100, may be provided in an integrated circuit" Boesch explicitly describes a dedicated integrated circuit for the specific application of neural network processing)
operable as a reconfigurable multilayer image processor, comprising:([¶0135] "The illustrated SoC 110 includes a plurality of SoC controllers 120, a configurable accelerator framework (CAF) 400 (e.g., an image and DCNN co-processor subsystem)" [¶0071] "The reconfigurable dataflow accelerator fabric allows the definition of any desirable, determined number of concurrent, virtual processing chains at run time")
receiving an artificial intelligence (AI) model for image processing; ([¶0062] "The first convolutional layer CL1 in the AlexNet architecture of FIG. 1A")
configuring the AI network based on the AI model, ([¶0135] "The illustrated SoC 110 includes a plurality of SoC controllers 120, a configurable accelerator framework (CAF) 400 (e.g., an image and DCNN co-processor subsystem)" [¶0071] "The reconfigurable dataflow accelerator fabric allows the definition of any desirable, determined number of concurrent, virtual processing chains at run time")
wherein the AI network comprises: multiple layers comprising an input layer that receives an image input, ([¶0316] "the SoC 110 is enabled to perform image recognition on input image data." [¶0318] "processing of an image through the DCNN layers")
an output layer that produces an image output, ([¶0044] "the pooled output map in FIG. 1" [¶0316] "to perform image recognition on input image data." [¶0318] "processing of an image through the DCNN layers" Any output resulting from the input image is interpreted as an image output)
and at least one intermediate layer between the input layer and the output layer, ([¶0316] "the SoC 110 is enabled to perform image recognition on input image data." [¶0318] "processing of an image through the DCNN layers" [¶0062] "The first convolutional layer CL1 in the AlexNet architecture of FIG. 1A filters a 224×224×3 input image with 96 kernels of size 11×11×3 with a stride of 4 pixels. This stride is the distance between the receptive field centers of neighboring neurons in a kernel map. The second convolutional layer CL2 takes as input the response-normalized and pooled output of the first convolutional layer CL1 and filters the output of the first convolutional layer with 256 kernels of size 5×5×48. The third, fourth, and fifth convolutional layers CL3, CL4, CL5 are connected to one another without any intervening pooling or normalization layers. The third convolutional layer CL3 has 384 kernels of size 3×3×256 connected to the normalized, pooled outputs of the second convolutional layer CL2. The fourth convolutional layer CL4 has 384 kernels of size 3×3×192, and the fifth convolutional layer CL5 has 256 kernels of size 3×3×192. The fully connected layers have 4096 neurons each.")
each layer comprising a plurality of multiplier-accumulator (MAC) units; ([¶0073] " the configuration of a CA is defined manually for each DCNN layer" [¶0156] "A different acceptably optimal configuration of CAs 600 in the CAF 400 is determined for each DCNN layer. These configurations may be determined or adjusted using a holistic tool that starts with a DCNN description format, such as Caffe′ or TensorFlow" [¶0072] "The CA includes a line buffer to fetch a plurality (e.g., up to 12) of feature map data words in parallel with a single memory access. A register based kernel buffer provides a plurality (e.g., up to 36 read ports), while a plurality (e.g., 36) of multi-bit (e.g., 16-bit) fixed point multiply-accumulate (MAC) units perform a plurality (e.g., up to 36) of MAC operations per clock cycle" [¶0265] "each MAC cluster contains three (3) MAC units ")
at least one layer being partitioned into a plurality of blocks of MAC units, ([¶0265] "the CA MAC units 620 are arranged to include a stack of 12 MAC clusters of which each MAC cluster contains three (3) MAC units and wherein each MAC unit is capable of performing one 16-bit MAC operation per cycle.")
the plurality of blocks of MAC units being reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units; ([¶0236] "the 5×5 kernel of Layer 2 in Table 5 can be handled by chaining two MAC clusters. In CAF 400, this feature may be automatically applied when multiple clusters of the same kernel are assigned to the same processing row." For Layer 2's 5x5 kernel, Boesch explicitly combines two MAC clusters. More generally, CA 600 can select a number N of two or more clusters and chain them to produce an output value)
receiving changes in the AI model for the image processing; ([¶0071] "The reconfigurable dataflow accelerator fabric allows the definition of any desirable, determined number of concurrent, virtual processing chains at run time" [¶0119] "FIG. 7 is a high level block diagram illustrating the path of data for training a deep convolution neural network (DCNN) and configuring a system on chip (SoC) with the trained DCNN")
and reconfiguring the plurality of blocks of MAC units via multiplexers and layer tap selectors within the ASIC to execute the changes in the AI model for the image processing via multiplexers ([¶0236] "the 5×5 kernel of Layer 2 in Table 5 can be handled by chaining two MAC clusters. In CAF 400, this feature may be automatically applied when multiple clusters of the same kernel are assigned to the same processing row." For Layer 2's 5x5 kernel, Boesch explicitly combines two MAC clusters. More generally, CA 600 can select a number N of two or more clusters and chain them to produce an output value)
and layer tap selectors within the ASIC ([¶0071] "The reconfigurable dataflow accelerator fabric allows the definition of any desirable, determined number of concurrent, virtual processing chains at run time" [¶0119] "FIG. 7 is a high level block diagram illustrating the path of data for training a deep convolution neural network (DCNN) and configuring a system on chip (SoC) with the trained DCNN")
by implementing at least one of: one or more virtual layers in addition to the multiple layers; or reconfiguration of an input depth size, output feature map size, or a combination thereof for the at least one layer partitioned into the plurality of blocks of MAC units ([¶0072] "Kernel sets may be partitioned in batches and processed sequentially" [¶0232] "the batch may divide the number of channels by an integer number" partitioning kernels into batches interpreted as reconfiguration of an input depth/channel size).
While Boesch explicitly describes a dedicated integrated circuit for the specific application of neural network processing, Boesch does not explicitly use the term application specific integrated circuit (ASIC).
Nakahara, in the same field of endeavor, teaches an application specific integrated circuit (ASIC) ([p. 201] "we propose a reconfigurable neural network accelerator (ReNA), an AI chip that can process convolutional and fully connected layers with the same structure by reconfiguring the circuit […] designed as application-specific integrated circuits for processing convolutional neural networks" [p. 205] "We performed layout design with a TSMC 22-nm process standard cell").
Boesch as well as Nakahara are directed towards reconfigurable integrated circuits for CNN (specifically AlexNet). Therefore, Boesch as well as Nakahara are analogous art in the same field of endeavor. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Boesch with the teachings of Nakahara by calling the integrated circuit an ASIC. Nakahara provides as additional motivation for combination ([p. 201] "we propose a reconfigurable neural network accelerator (ReNA), an AI chip that can process convolutional and fully connected layers with the same structure by reconfiguring the circuit […] designed as application-specific integrated circuits for processing convolutional neural networks"). This motivation for combination also applies to the remaining claims which depend on this combination.
Regarding claim 12, the combination of Boesch and Nakahara teaches The method of claim 11, wherein the image processing comprises image scaling. (Nakahara [p. 302] "The PB array size and memory size are determined so that AlexNet [12] can be implemented" AlexNet scales image by definition).
Regarding claim 15, the combination of Boesch and Nakahara teaches The method of claim 11, wherein different blocks of MAC units in the plurality of blocks of MAC units support different input depth sizes, different output feature map sizes, or a combination thereof.(Nakahara [p. 203] "This process is per formed multiple times if the filter size k is larger than 1 or if the input channels are larger than the array size. After the operation, outputs of one row of different channels are generated (Figure 5(d)). This process is repeated until all outputs have been computed. When the image size or the number of input feature-map channels exceeds the array size, the operation is split into multiple operations. Thus, it can process a layer of any hyperparameter. When the image size of the input feature map is smaller than the array size, multiple lines of output can be simultaneously computed. Therefore, ReNA can process input feature maps of various sizes with high parallelism").
Regarding claim 16, the combination of Boesch and Nakahara teaches The method of claim 11, wherein multiple layers are partitioned into the plurality of blocks of MAC units.(Nakahara [p. 204] "Fig. 5. Example of convolutional layer processing […] Fig. 6. Example of fully connected layer processing." See also FIG. 5 and FIG. 6).
Regarding claim 17, the combination of Boesch and Nakahara teaches The method of claim 11, wherein each MAC unit comprises a two-dimensional (2D) filter.(Nakahara [p. 3] "The size of the PB array is 64 × 64 […] Figure 5 shows processing in the convolutional layer for a3×3 Pb array" See FIG. 5-7 which shows MAC unit 2D filter).
Regarding claim 18, the combination of Boesch and Nakahara teaches The method of claim 11, wherein: each of the at least one intermediate layer has an input depth size for receiving a plurality of feature maps from a preceding layer and an output feature map size for producing a plurality of feature map outputs; (Boesch [¶0224] " Feature data in many cases consists of two or more channels of two-dimensional data structure" [¶0225] "kernel depth is often identical to the number of channels of the feature data set that will be processed." [¶0229] " the feature input data for the next layer is generated" See also Table 5 showing the feature sizes)
reconfiguring the plurality of blocks of MAC units to execute the changes in the AI model for the image processing comprises arranging the plurality of blocks of MAC units to operate independently or to operate in one or more combinations of blocks of MAC units to enable at least one of implementation of one or more virtual layers between the input layer and the output layer, reconfiguration of the input depth size of the at least one intermediate layer, reconfiguration of the output feature map size of the at least one intermediate layer, or a combination thereof.(Nakahara [p. 202] "connections between PBs are reconfigurable by the configuration register. The controller supports microcode instructions and generates control signals for different processing layers." [p. 203] "This reconfiguration is performed layer-by-layer, and connections are changed based on layer hyperparameters." [p. 205] "the ReNA method of processing fully connected layers is useful, because it improves performance without retraining" Different processing layers and layer hyperparameters are interpreted as changes).
Regarding claim 19, the combination of Boesch and Nakahara teaches The method of claim 18, wherein the image output comprises a plurality of pixels for each respective pixel in the image input.(Boesch [¶0224] "feature data comprises image frames and associated pixel data of the image frames" [¶0232] "the feature data of Layer 3 (Table 5) can be divided by 16, which will generate 16 feature batches of 13×13×16 pixels and 16 kernel batches of 3×3×16 for one kernel [...] in Layer 2a, the CA 600 will perform convolution operation on six (6) feature batches with 27×27×8 pixels").
Regarding claim 20, the combination of Boesch and Nakahara teaches The method of claim 11, wherein each layer comprises sets of memories associated with each layer for tap generation, wherein any combination of blocks of MAC units is receivable by any set of memories and a tap output from any set of memories is receivable by any combination of blocks of MAC units.(Nakahara [p. 203] "The other function receives activations from SRAM during calculations. The PB has two registers for storing activations, one storing activations from PB connections and the other storing activations from SRAM. The select unit determines which register stores which activation. Thus, while one register supplies the MAC operator with operation activations, the other can supply the next activation from SRAM to the PB" See also FIG. 3(a-b) showing processing block with registers with bidirectional accessibility of surrounding PBs).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SIDNEY VINCENT BOSTWICK/Examiner, Art Unit 2124
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