DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 16 and 20.
Pending: 1-4 and 6-20.
Amended: 1, 16, and 20
Canceled: 5.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 9-15 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nishida US Patent 10283493 B1;in view of Hazue 20180076085 A1; further in view of Chen et al., US PG pub. 20230005856 A1.
Re: Independent Claim 1, Nishida discloses a substrate (8, fig. 17) including a first region (100, fig. 17) and a second region (200 and 400, fig. 17);
first and second stacks (132/146 and 232/246, fig. 17), each of which includes interlayer insulating layers (132 and 232, fig. 17) and gate electrodes (146 and 246, fig. 17) stacked alternately with the interlayer insulating layers (132 and 232, fig. 17) on the substrate (8, fig. 17) and has a stepped structure (step formed by 132/146, fig. 17) on the second region (200 and 400, fig. 17);
an insulating layer (165 and 265, fig. 17) on the stepped structure (step formed by 132/146, fig. 17) of the first stack (132 and 146, fig. 17);
a plurality of vertical channel structures (60, fig. 12A) on the first region (100, fig. 17) to penetrate the first stack (132 and 146, fig. 17); and
a separation structure (180, fig. 17) separating the first and second stacks (132/146 and 232/246, fig. 17) from each other
Nishida is silent regarding: wherein the insulating layer (165 and 265, fig. 17) comprises one or more dopants, and
a dopant concentration of the insulating layer (165 and 265, fig. 17) decreases as a distance from the substrate (8, fig. 17) increases.
Hazue discloses insulating layer (45, fig. 23B; ¶[0080]-¶[0085]) comprises one or more dopants, and a dopant concentration (¶[0085]) of the insulating layer (¶[0080] insulating layer 45 has a gradient in the thickness direction, ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation) decreases as a distance from the substrate (10, fig. 23B) increases.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Nishida and Hazue silent regarding: wherein the insulating layer comprises one or more dopants, wherein the one or more dopants comprise N, F, P, B, C, Ge, As, Cl, and/or Br,
Chen discloses insulating layer such as a ILD layer comprises one or more dopants comprise N, F, P, B, C, Ge, As, Cl, and/or Br (¶0183 ILD layer can include dielectric material with silicon nitride or low-k dielectrics material).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include low-k dielectric material or silicon nitride since this can reduce current leakage and reduced capacitance allow signal travel faster.
Re: Claim 2, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida further discloses: wherein the separation structure (180, fig. 17) extends longitudinally in a first direction (horizontal direction parallel to the substrate 8, fig. 17), and a side surface of the separation structure (180, fig. 17) comprises a plurality of recesses (recess in layer 180 as shown in figure 9H) arranged along the first direction (horizontal direction parallel to the substrate 8, fig. 17).
Re: Claim 3, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida further discloses: wherein the separation structure (180, fig. 17) has a unitary structure (layer 180 is a single layer structure) including a single insulating material (column 12, lines 34-35).
Re: Claim 4, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida is silent regarding: wherein the dopant concentration of the insulating layer (165 and 265, fig. 17) varies linearly as the distance from the substrate (8, fig. 17) increases.
Hazue discloses insulating layer (45, fig. 23B; ¶[0080]-¶[0085]) comprises one or more dopants, and a dopant concentration (¶[0085]) of the insulating layer (¶[0080] insulating layer 45 has a gradient in the thickness direction, ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Re: Claim 5, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida is silent regarding: wherein the one or more dopants comprise N, F, P, B, C, Ge, As, Cl, and/or Br.
Hazue discloses in ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Re: Claim 6, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida is silent regarding: wherein the insulating layer (165 and 265, fig. 17) comprises a first doped insulating material, and each of the interlayer insulating layers (132 and 232, fig. 17) comprises a second doped insulating material.
Hazue discloses in ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation, wherein the first and second doped insulating material could be the same material such as in region 46 and 47.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Re: Claim 9, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida further discloses: wherein the first stack (132 and 146, fig. 17) comprises a lower stack comprising a lower stepped structure (step formed by 132/146, fig. 17) on the substrate (8, fig. 17) and an upper stack comprising an upper stepped structure (step formed by 132/146, fig. 17) on the lower stack, the insulating layer (165 and 265, fig. 17) comprises a first insulating layer (165, fig. 17) on the lower stepped structure (step formed by 132/146, fig. 17) of the lower stack, and a second insulating layer (265, fig. 17) on the upper stepped structure (step formed by 132/146, fig. 17) of the upper stack.
Nishida is silent regarding: a dopant concentration in each of the first and second insulating layer (265, fig. 17)s decreases as a distance from the substrate (8, fig. 17) increases.
Hazue discloses insulating layer (45, fig. 23B; ¶[0080]-¶[0085]) comprises one or more dopants, and a dopant concentration (¶[0085]) of the insulating layer (¶[0080] insulating layer 45 has a gradient in the thickness direction, ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation) decreases as a distance from the substrate (10, fig. 23B) increases.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Re: Claim 10, Nishida and Hazue discloses all the limitations of claim 9 on which this claim depends. Nishida is silent regarding: wherein the dopant concentration in an uppermost portion of the first insulating layer (165, fig. 17) is higher than the dopant concentration of a lowermost portion of the second insulating layer (265, fig. 17).
Hazue discloses insulating layer (45, fig. 23B; ¶[0080]-¶[0085]) comprises one or more dopants, and a dopant concentration (¶[0085]) of the insulating layer (¶[0080] insulating layer 45 has a gradient in the thickness direction, ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation) decreases as a distance from the substrate (10, fig. 23B) increases.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Re: Claim 11, Nishida and Hazue discloses all the limitations of claim 9 on which this claim depends. Nishida further discloses: wherein a side surface of each of the vertical channel structures (60, fig. 12A) has a stepped portion adjacent an interface between the first and second insulating layer (165, 265, fig. 17)
Re: Claim 12, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida further discloses: wherein the separation structure (180, fig. 17) extends longitudinally in a first direction (horizontal direction parallel to the substrate 8, fig. 17) and comprises a first separation structure (180 in region 100, fig. 17) on the first region (100, fig. 17) and a second separation structure (180 in region 200, fig. 17) that is on the second region (200 and 400, fig. 17) and extends from the first separation structure (180 in region 100, fig. 17) in the first direction (horizontal direction parallel to the substrate 8, fig. 17), and
the second separation structure (180 in region 200, fig. 17) comprises a straight side surface extending in the first direction (horizontal direction parallel to the substrate 8, fig. 17).
Re: Claim 13, Nishida and Hazue discloses all the limitations of claim 12 on which this claim depends. Nishida further discloses: wherein a width of the second separation structure (180 in region 200, fig. 17) in a second direction (vertical direction, fig. 17) that is perpendicular to the first direction (horizontal direction parallel to the substrate 8, fig. 17) is substantially uniform along the first direction (horizontal direction parallel to the substrate 8, fig. 17).
Re: Claim 14, Nishida and Hazue discloses all the limitations of claim 1 on which this claim depends. Nishida further discloses: a source structure (6, fig. 17) between the substrate (8, fig. 17) and the first stack (132 and 146, fig. 17), wherein each of the vertical channel structures (60, fig. 12A) comprises a data storage pattern and a vertical semiconductor pattern (58, fig. 17) in the data storage pattern, and
the source structure (6, fig. 17) is in contact with the vertical semiconductor pattern (58, fig. 17) of each of the vertical channel structures (60, fig. 12A).
Re: Claim 15, Nishida and Hazue discloses all the limitations of claim 14 on which this claim depends. Nishida further discloses: wherein the source structure (6, fig. 17) is in contact with a side surface of the vertical semiconductor pattern (58, fig. 17) of each of the vertical channel structures (60, fig. 12A).
Re: Independent Claim 20, Nishida discloses a substrate (8, fig. 17) including a first region (100, fig. 17) and a second region (200 and 400, fig. 17);
first and second stacks (132/146 and 232/246, fig. 17), each of which includes interlayer insulating layers (132 and 232, fig. 17) and gate electrodes (146 and 246, fig. 17) stacked alternately with the interlayer insulating layers (132 and 232, fig. 17) on the substrate (8, fig. 17) and has a stepped structure (step formed by 132/146, fig. 17) on the second region (200 and 400, fig. 17);
an insulating layer (165 and 265, fig. 17) on the stepped structure (step formed by 132/146, fig. 17) of the first stack (132 and 146, fig. 17);
a plurality of vertical channel structures (60, fig. 12A) on the first region (100, fig. 17) and penetrate the first stack (132 and 146, fig. 17); and
a separation structure (180, fig. 17) separating the first and second stacks (132/146 and 232/246, fig. 17) from each other.
Nishida is silent regarding: a three-dimensional semiconductor memory device; and
a controller electrically connected to the three-dimensional semiconductor memory device and configured to control the three-dimensional semiconductor memory device, wherein the three-dimensional semiconductor memory device comprises:
wherein the insulating layer (165 and 265, fig. 17) comprises one or more dopants, and
a dopant concentration of the insulating layer (165 and 265, fig. 17) decreases as a distance from the substrate (8, fig. 17) increases.
Hazue discloses a three-dimensional semiconductor memory device (MC, fig. 29); and
a controller (¶[0144]-¶[0145]) electrically connected to the three-dimensional semiconductor memory device and configured to control the three-dimensional semiconductor memory device, wherein the three-dimensional semiconductor memory device, and an insulating layer (45, fig. 23B; ¶[0080]-¶[0085]) comprises one or more dopants, and a dopant concentration (¶[0085]) of the insulating layer (¶[0080] insulating layer 45 has a gradient in the thickness direction, ¶[0085] the insulating layer 45 is formed by chemical vapor deposition (CVD) for example, carbon or nitrogen is implanted into the upper layer portion 46 of the insulating layer 45 by ion implantation) decreases as a distance from the substrate (10, fig. 23B) increases.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a gradient of carbon or nitrogen concentration I the insulation layer 45 since this can improve the controlling of acceleration voltage thereby improving performance for the memory device (¶[0115]-¶[0116]; ¶[0120]).
Nishida and Hazue silent regarding: wherein the insulating layer comprises one or more dopants, wherein the one or more dopants comprise N, F, P, B, C, Ge, As, Cl, and/or Br,
Chen discloses insulating layer such as a ILD layer comprises one or more dopants comprise N, F, P, B, C, Ge, As, Cl, and/or Br (¶0183 ILD layer can include dielectric material with silicon nitride or low-k dielectrics material).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include low-k dielectric material or silicon nitride since this can reduce current leakage and reduced capacitance allow signal travel faster.
Allowable Subject Matter
Claims 16-19 are allowed.
Re: Independent Claim 16 (and its dependent claim(s) 17-19), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: lower insulating patterns in the second substrate; first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the second substrate and the lower insulating patterns and has a stepped structure on the second region; a source structure between the second substrate and the first stack; an insulating layer on the stepped structure of the first stack; a plurality of vertical channel structures on the first region of the first stack, penetrate the first stack and in contact with the second substrate; a first contact plug that is on the second region and penetrates the insulating layer, the first stack, the source structure, and one of the lower insulating patterns, wherein the first contact plug is electrically connected to a first one of the peripheral circuit transistors of the peripheral circuit structure and is in contact with one of the gate electrodes of the first stack; a second contact plug that is on the second region to penetrate the insulating layer and is electrically connected to a second one of the peripheral circuit transistors of the peripheral circuit structure; and a separation structure separating the first and second stacks from each other and the separation structure extending vertically to the second substrate and extending in a first direction such that the first and second stacks are spaced apart from each other in the second direction with the separation structure between them, wherein the separation structure comprises opposing side surfaces, each of which comprises a recess, and the recesses of the opposing side surfaces of the separation structure are aligned with each other along a second direction crossing the first direction and define a narrow portion having a narrower width than adjacent portions thereof in the second direction, and the insulating layer comprises one or more dopants.
Claim(s) 7-8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 7, (and its dependent claim 8) the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a remaining portion that is between the substrate and the separation structure and comprises a portion of the interlayer insulating layers and a portion of the gate electrodes of the first stack, and the remaining portion has a width decreasing as a distance from the substrate increases.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6, 9-15 and 20 have been considered but are moot in view of the new ground(s) of rejection further in view of Chen et al., US PG pub. 20230005856 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898