Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
3. Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding independent claims 1 and 11, the claims recite a limitation for “(c) continuing until each of the additional circuits have been added to the second set of circuits.” The limitation specifically, but also the claim when read as a whole, is entirely silent as to what is being continued, thereby rendering the limitation and the claim vague and indefinite.
The dependent claims include the same or similar limitations as discussed here, by virtue of their depending from claims 1 and 11, and thereby inherit their deficiencies without otherwise curing them; hence, they too are rejected under the same rationale.
By way of a clarifying amendment and indication of support, applicants should make clear what is being continued per limitation (c) to overcome the present rejection.
4. Claims 10 and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. The claims recite a limitation “wherein z=5 and the SPAn sequence of CX gates comprises a WPA-TDGn” without any indication in these claims, or the claims from which they depend, what z represents and what it being equal to 5 indicates. A review of the claims as a whole reveal no other mention of z as recited here, and hence the limitation’s bolded language above is vague and indefinite.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0390235 (“Bravyi”) in view of Non-Patent Literature “The Controlled-NOT (CNOT) Gate in Quantum Computing” (“Marin”).
Regarding claim 1, BRAVYI teaches A ... quantum circuit on n wires ([0006] establishing the inventive framework as a circuit generation component for building circuits from 1 to N two-qubit gates (where each qubit as taught is akin to a wire as recited)) comprising:
a first set of circuits and a plurality of CX gates appended to the first set of circuits to generate a plurality of additional circuits, wherein each of the additional circuits is formed by appending a CX gate of the plurality of CX gates in a corresponding one of a plurality of configurations to one circuit of a first set of circuits (FIG. 6 step 604 discussing the generation of a first set of quantum circuits comprising 2-qubit gates, e.g. CNOT gates per [0117] (which the Examiner understands to be the equivalent of the recited CX gate), where the first set is iteratively grown by adding one gate at a time to a circuit from a prior iteration (e.g., as is discussed in [0107] for example)); and
a second set of circuits ([0118] and FIG. 6 step 606: “second set of quantum circuits”), wherein the second set of circuits is generated by:
(a) sequentially adding, ones of the additional circuits to the second set of circuits (the Examiner understands this set of circuits to be grown iteratively per [0118] by a sequential adding of gates as was discussed per [0107]) when a number of circuits in the second set of circuits is less than a first threshold number ([0119] mentioning that the number of gates should be one that matches the desired quantum circuit representation, and it reasons that if gates are being added one at a time, then this iterative gate addition and hence the iterative circuit generation is capped by the number that “matches”);
(b) when the number of circuits in the second set of circuits reaches the first maximum number, scoring the circuits added to the second set of circuits (FIG. 6 step 612’s benchmarking algorithm, as mentioned per [0121] and discussed per [0090], evaluates each of the generated circuits against the desired circuit (i.e., a comparison which the Examiner equates with the recited scoring)), removing a circuit from the second set of circuits based on a scoring criteria, and adding a next one of the additional circuits to the second set of circuits ();
(c) continuing until each of the additional circuits have been added to the second set of circuits (circuits are generated per [0121] in accordance with each iteration adding a gate corresponding to a qubit, up to that matching the desired circuit);
(d) remove duplicate circuits from the second set of circuits (FIG. 6 step 606 screens out circuits generated by the adding of redundant operations);
(e) when the number of circuits in the second set of circuits is greater than a second threshold number, removing circuits from the second set of circuits based on the scoring criteria until the number of circuits in the second set of circuits is equal to the second threshold number (FIG. 6 step 612’s benchmarking algorithm, as mentioned per [0121] and discussed per [0090], could be understood to remove circuits that do not meet the requirements represented by the desired circuit);
(f) scoring the second set of circuits based on a scoring threshold (FIG. 6 step 612’s benchmarking algorithm, as mentioned per [0121] and discussed per [0090], evaluates each of the generated circuits against the desired circuit (i.e., a comparison which the Examiner equates with the recited scoring));
(g) when none of the second set of circuits reaches the scoring threshold, updating the first set of circuits as the second set of circuits, and repeating steps (a)-(f) and (h) when one of the second set of circuits reaches the scoring threshold, selecting a ... sequence of CX gates as the one of the second set of circuits that reaches the scoring threshold (the Examiner understands the circuit generation process to repeat until the benchmarking succeeds, e.g. see FIG. 7’s steps 710 and 712).
The Examiner acknowledges that the claims clarify that the recited quantum circuit in the preamble is a TDGn quantum circuit and that the selected sequence of CX gates per limitations (h) (and (i) as to be discussed next) is a TDGn sequence of CX gates. “TDGn” is not a term of art and does not appear to have any meaning apart from Applicants’ discussion of the term in its specification. For purposes of present examination, the Examiner equates any quantum circuit that otherwise meets the requirements of the claims to be equivalent to a TDGn quantum circuit and any sequence of CX gates that otherwise meets the requirements of the claims to be equivalent to a TDGn sequence. The Examiner notes that “TDG” is merely an abbreviation or acronym for the first letters of the first named inventors of this application. If the term has any further meaning, particularly since it appears to be not known in the state of the art, then Applicants should take this opportunity to amend the claim to give it that particular meaning.
Bravyi does not teach the further limitation of (i) adding a plurality of phase gates, wherein each of the phase gates is inserted after a corresponding one of the CX gates of the TDGn sequence of CX gates on a corresponding one of the n wires. Rather, the Examiner relies upon MARIN to teach what Bravyi lacks, see e.g., Marin’s page 7: “It turns out that any multi-qubit quantum operation can be decomposed into a network of CNOT gates plus single-qubit gates (such as rotations, Hadamards, and phase gates). For example, a CNOT can entangle qubits, while single-qubit gates can create superpositions and adjust phases. This is sufficient to build up any quantum computation. The CNOT by itself isn’t universal (just as XOR alone isn’t universal classically – you can’t get an AND from just XORs without some constant bits), but {CNOT + all single-qubit gates} is universal for quantum computing.” The Examiner understands this to mean that quantum computing operations, should they involve CNOT gates, would also involve a single-qubit gate with it, such as a phase gate.
Bravyi and Marin both relate to quantum circuit generation that is mindful of gate minimization as a means to reduce/promote efficiency and performance concerns (see, e.g., Brayvi [0024]). Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Marin’s use of phase gates with the added CNOT gates of Bravyi’s circuit generation process, e.g. to build quantum computing circuits in a manner that is universally accepted and provided error correction advantages.
Regarding claim 11, the claim includes the same or similar limitations as claim 1 discussed above, and is therefore rejected under the same rationale.
Regarding claims 2-10 and 12-20, the Examiner understands these claims to essentially clarify the independent claims in two regards:
A clarification as to how many wires (i.e., how many qubits, based on the Examiner’s reading of Applicants’ specification [0019]) are involved in the adding of how many CX gates, and then a sequence for the gate insertion/addition (which the Examiner believes is taught in accordance with Bravyi’s iterative circuit generation process that adds gates and hence qubits iteratively from 0 or 1 up to some number n), and
A clarification that phase gate insertion/addition per claim 1 is to be after a CX gate (which the Examiner believes Marin as cited provides with its teaching that it is universally understood that adding a phase gate for example to a CNOT gate helps with error correction).
While the number n may vary across the different dependent claims, the rationale in each instance remains the same. As the Examiner understands it, n merely serves to define a particular size or scale for the circuit in terms of qubits, and the rationale provided by the Examiner for the present claims does not vary in accordance with n.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure:
US 11200360-B1
US 20210334079-A1
US 20180144262-A1
US 11194946-B2
US 20200184024-A1
US 20070266347-A1
US 12118432-B2
US 10740689-B2
US 10664249-B2
US 20190332731-A1
US 20190095561-A1
US 20060123363-A1
Non-Patent Literature “Optimization of Quantum Circuit Mapping using Gate Transformation and Commutation”
Non-Patent Literature “Canonicalizing H+S+CNOT+T Circuits”
Non-Patent Literature “Quantum circuits of CNOT gates”
Non-Patent Literature “Constructing quantum circuits with global gates”
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHOURJO DASGUPTA whose telephone number is (571)272-7207. The examiner can normally be reached M-F 8am-5pm CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tamara Kyle can be reached at 571 272 4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHOURJO DASGUPTA/Primary Examiner, Art Unit 2144