DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 10-13, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara.
As to claim 1, Donovan teaches a processor comprising:
a global scheduler comprising circuitry configured to distribute work items (Work Items 72/74/76) for execution (Work Queue Assignment Functions 62/64/66/Work Schedulers 42/44/46);
at least one local scheduler comprising circuitry configured to send the work items (Work Items 72/74/76) to one or more processors for execution (Work Queue Assignment Functions 62/64/66/Work Schedulers 42/44/46) (“…each WQAF assigns each work item created by its own virtual machine to any work queue 52, 54 or 56 in shared memory based on its assignment algorithm. The assignment algorithm may be based on work load balancing, which virtual machines are specially adapted to handle certain types of work items, etc. Each WQAF also monitors and updates a status of each virtual machine as "idle" or "not idle" as described below. Each scheduler schedules the execution of work items on its nominal work queue according to its scheduling algorithm. The scheduling algorithm may be based on a priority level assigned to the work item, the time the work item was assigned to the work queue, etc…Consequently, each WQAF can access all the work queues to add a work item to any of the work queues. In the first embodiment of the present invention, each scheduler is programmed to only remove work items from its "semi-dedicated" work queue, i.e. work queue 52 for virtual machine 12 and scheduler 42, work queue 54 for virtual machine 14 and scheduler 44 and work queue 56 for virtual machine 16 and scheduler 46. Each of these work queues is "semi-dedicated" in the first embodiment of the present invention because only the scheduler in the respective virtual machine removes work items from it but any of the WQAFs can add work items to it. (However, in another embodiment of the present invention, each scheduler can be programmed to access the other semi-dedicated work queues to remove a work item when its semi-dedicated work queue is empty.) In the state illustrated in FIG. 1, work queue 52 has one work item 70 which was acquired from virtual machine 14 by action of WQAF 64, work queue 54 is empty, and work queue 56 has three work items 72, 74 and 76. Work item 72 was acquired from virtual machine 12 by action of WQAF 62. Although not shown, work items 74 and 76 were acquired from virtual machine 14 by action of WQAF 64. Also in the state illustrated in FIG. 1, virtual machine 12 is acquiring work item 70 from work queue 52 by action of scheduler 42, and virtual machine 16 is acquiring work item 76 from work queue 56 by action of scheduler 46. A control block 58 indicates the current state, "idle" or "non idle", of the virtual machines and which, if any, of the work items from each work queue is the next to be scheduled. In the state illustrated in FIG. 1, virtual machine 12 is idle with its work queue pointer in scheduler 42 pointing to work item 70. After virtual machine 12 acquires work item 70, its work queue pointer will be "null" because there will be no work items left in work queue 52 (unless one was added in the interim). Also in the state illustrated in FIG. 1, virtual machine 14 is idle with its work queue pointer in scheduler 44 indicating "null" because there are currently no work items in work queue 54. Also in the state illustrated in FIG. 1, virtual machine 16 is "not idle"; it is currently performing a work item previously acquired from one of the work queues. The work queue pointer of scheduler 66 within virtual machine 16 is currently indicating work item 76, so this work item has not yet been removed by scheduler 46 for execution by virtual machine 16…” Col. 4 Ln. 34-45, 55-67, Col. 5 Ln. 1-31); and
at least a first mailbox dedicated to supporting direct point-to-point message passing between the global scheduler and a corresponding one of the at least one local schedulers (Work Queue 52), the first mailbox comprising one or more memory locations (pointer) that are readable by the global scheduler and writable by the corresponding local scheduler (Control Block 58 ) (“…For purposes of illustration, assume the scheduler decides to fetch a work item from its semi-dedicated work queue (step 201). Next, the scheduler 42 checks the control block 58 to determine if there is a work item or a group of work items on the work queue 52 for the virtual machine 12 (decision 202). If there is a group of work items on the work queue, then a pointer in the control block indicates which is the next work item to be scheduled. The determination of which work item in the work queue to be scheduled next is determined by the order they appear on the work queue. The WQAF of the virtual machine that created the work item determines where in the work queue to position the work item. The WQAF also determined on which work queue to place the work item. If the work queue is not empty (which is the case illustrated in FIG. 1 for work queue 52), the virtual machine is marked "not idle" (step 203) and scheduler 42 removes the work item from the queue indicated by the pointer in the control block (step 204). In the example illustrated in FIG. 1, the pointer points to work item 70. Then, the scheduler 42 parses the work item to determine its nature and what function to call within virtual machine 12 to perform the work item. After removal of work item 70, the work queue 52 will be empty (unless a new work item was very recently added), so the pointer for work queue 52 will indicate "null". Then, the recipient function performs the work item (step 206). After the work item is completed (step 208), control is returned to the scheduler to repeat steps 200, 201 and 202…” Col. 6 Ln. 22-49);
wherein the corresponding local scheduler writes a first set of messages to the first mailbox to communicate with the global scheduler (add a work item) (“…Consequently, each WQAF can access all the work queues to add a work item to any of the work queues. In the first embodiment of the present invention, each scheduler is programmed to only remove work items from its "semi-dedicated" work queue, i.e. work queue 52 for virtual machine 12 and scheduler 42, work queue 54 for virtual machine 14 and scheduler 44 and work queue 56 for virtual machine 16 and scheduler 46. Each of these work queues is "semi-dedicated" in the first embodiment of the present invention because only the scheduler in the respective virtual machine removes work items from it but any of the WQAFs can add work items to it. (However, in another embodiment of the present invention, each scheduler can be programmed to access the other semi-dedicated work queues to remove a work item when its semi-dedicated work queue is empty.) In the state illustrated in FIG. 1, work queue 52 has one work item 70 which was acquired from virtual machine 14 by action of WQAF 64, work queue 54 is empty, and work queue 56 has three work items 72, 74 and 76. Work item 72 was acquired from virtual machine 12 by action of WQAF 62. Although not shown, work items 74 and 76 were acquired from virtual machine 14 by action of WQAF 64. Also in the state illustrated in FIG. 1, virtual machine 12 is acquiring work item 70 from work queue 52 by action of scheduler 42, and virtual machine 16 is acquiring work item 76 from work queue 56 by action of scheduler 46. A control block 58 indicates the current state, "idle" or "non idle", of the virtual machines and which, if any, of the work items from each work queue is the next to be scheduled. In the state illustrated in FIG. 1, virtual machine 12 is idle with its work queue pointer in scheduler 42 pointing to work item 70. After virtual machine 12 acquires work item 70, its work queue pointer will be "null" because there will be no work items left in work queue 52 (unless one was added in the interim). Also in the state illustrated in FIG. 1, virtual machine 14 is idle with its work queue pointer in scheduler 44 indicating "null" because there are currently no work items in work queue 54. Also in the state illustrated in FIG. 1, virtual machine 16 is "not idle"; it is currently performing a work item previously acquired from one of the work queues. The work queue pointer of scheduler 66 within virtual machine 16 is currently indicating work item 76, so this work item has not yet been removed by scheduler 46 for execution by virtual machine 16…” Col. 4 Ln. 55-67, Col. 5 Ln. 1-31).
Donovan silent with reference to at least a first mailbox that is independent of a main memory subsystem and
one or more memory locations in a global shared cache.
Alla teaches at least a first mailbox (Frame Buffer 128) that is independent of a main memory subsystem (System Memory 124) (“…GPU 120 may be directly coupled to GMEM 121. In other words, GPU 120 may process data locally using a local storage, instead of off-chip memory. This allows GPU 120 to operate in a more efficient manner by eliminating the need of GPU 120 to read and write data via, e.g., a shared bus, which may experience heavy bus traffic. GMEM 121 may include one or more volatile or non-volatile memories or storage devices, such as, e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), and one or more registers. [0036] Processing unit 127 and/or GPU 120 may store rendered image data in a frame buffer 128, which may be may be an independent memory or may be is allocated within system memory 124. A display processor may retrieve the rendered image data from frame buffer 128 and display the rendered image data on a display…” paragraph 0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan with the teaching of Alla because the teaching of Alla would improve the system of Donovan by providing a technique for using a buffer that is independent the system memory such that the system memory allowed concentrate on other functions.
Atara teaches one or more memory locations in a global shared cache (Shared Cache Memory 512) (“…The cache operations component 510 may also be configured to receive one or more cache read requests to read a previously cached data item based on a provided data item key. Each cache read request may include a data item key. In response, the cache operations component 510 may be configured search or locate the provided data item key in the cache key component 514 and provide a cache read response to a requesting component, application, and/or device. If the search finds the provided data item key in the cache component 514, cache operations component 510 may be configured to use the data item key (e.g., use a pointer or reference in the data item key, etc.) to retrieve the cached data item from the shared cache memory 512. When the search finds the provided data item key, the cache read response may include the cached data item. Otherwise, the cache read response may be a null or empty response….In an embodiment, the cache key component 514 may be generally arranged to store and manage one or more data item keys 528-m-n, where each data item key (e.g., data item keys 528-1-1, etc.)) may be associated with a cached data item stored in the shared cache memory 512 (e.g., cached data item 522-1-1, etc.) and may also identify the stored cached data item (e.g., cached data item 522-1-1, etc.). To identify and/or locate a data item cached in the shared cache memory 512, each data item key may also include a pointer or reference that may point to the location where the associated data item is stored in the shared cache memory 512…” paragraph 0082/0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan and Alla with the teaching of Atara because the teaching of Atara would improve the system of Donovan and Alla by providing a hardware or software component that stores data so that future requests for that data can be served faster.
As to claim 2, Donovan teaches the processor as recited in claim 1, further comprising:
a second mailbox dedicated to supporting direct point-to-point message passing between the global scheduler and the corresponding local scheduler, the second mailbox comprising one or more memory locations in the shared memory, the second mailbox being readable by the corresponding local scheduler and writable by the global scheduler; wherein the global scheduler writes a second set of messages to the second mailbox in response to a message of the first set of messages (Work Queues 54/56). See the claim 1 for shared cache.
As to claim 3, Donovan teaches the processor as recited in claim 2, wherein the first mailbox comprises a command queue configured to store the first set of messages received from the at least one corresponding local scheduler (add a work item/add work).
As to claim 5, Donovan teaches the processor as recited in claim 2, wherein the second mailbox is configured to return an empty message when no pending messages are stored in the second mailbox wherein a message of the first set of messages comprises an indication that the second mailbox is empty (Work Queue Empty).
As to claim 10, Donovan teaches a method comprising:
receiving (add work items), at a first mailbox a dedicated (Work Queue 52) to supporting direct point-to-point message passing between a global scheduler and a corresponding local scheduler, the first mailbox comprising one or more memory locations that are readable by the global scheduler and writable by the corresponding local scheduler (“…each WQAF assigns each work item created by its own virtual machine to any work queue 52, 54 or 56 in shared memory based on its assignment algorithm. The assignment algorithm may be based on work load balancing, which virtual machines are specially adapted to handle certain types of work items, etc. Each WQAF also monitors and updates a status of each virtual machine as "idle" or "not idle" as described below. Each scheduler schedules the execution of work items on its nominal work queue according to its scheduling algorithm. The scheduling algorithm may be based on a priority level assigned to the work item, the time the work item was assigned to the work queue, etc…Consequently, each WQAF can access all the work queues to add a work item to any of the work queues. In the first embodiment of the present invention, each scheduler is programmed to only remove work items from its "semi-dedicated" work queue, i.e. work queue 52 for virtual machine 12 and scheduler 42, work queue 54 for virtual machine 14 and scheduler 44 and work queue 56 for virtual machine 16 and scheduler 46. Each of these work queues is "semi-dedicated" in the first embodiment of the present invention because only the scheduler in the respective virtual machine removes work items from it but any of the WQAFs can add work items to it. (However, in another embodiment of the present invention, each scheduler can be programmed to access the other semi-dedicated work queues to remove a work item when its semi-dedicated work queue is empty.) In the state illustrated in FIG. 1, work queue 52 has one work item 70 which was acquired from virtual machine 14 by action of WQAF 64, work queue 54 is empty, and work queue 56 has three work items 72, 74 and 76. Work item 72 was acquired from virtual machine 12 by action of WQAF 62. Although not shown, work items 74 and 76 were acquired from virtual machine 14 by action of WQAF 64. Also in the state illustrated in FIG. 1, virtual machine 12 is acquiring work item 70 from work queue 52 by action of scheduler 42, and virtual machine 16 is acquiring work item 76 from work queue 56 by action of scheduler 46. A control block 58 indicates the current state, "idle" or "non idle", of the virtual machines and which, if any, of the work items from each work queue is the next to be scheduled. In the state illustrated in FIG. 1, virtual machine 12 is idle with its work queue pointer in scheduler 42 pointing to work item 70. After virtual machine 12 acquires work item 70, its work queue pointer will be "null" because there will be no work items left in work queue 52 (unless one was added in the interim). Also in the state illustrated in FIG. 1, virtual machine 14 is idle with its work queue pointer in scheduler 44 indicating "null" because there are currently no work items in work queue 54. Also in the state illustrated in FIG. 1, virtual machine 16 is "not idle"; it is currently performing a work item previously acquired from one of the work queues. The work queue pointer of scheduler 66 within virtual machine 16 is currently indicating work item 76, so this work item has not yet been removed by scheduler 46 for execution by virtual machine 16…” Col. 4 Ln. 34-45, 55-67, Col. 5 Ln. 1-31), a first message from the local scheduler coupled to one or more processors, wherein:
the global scheduler comprises circuitry configured to distribute work items for execution (Work Queue Assignment Functions 62/64/66/Work Schedulers 42/44/46); and
the corresponding local scheduler comprises circuitry configured to send the work items to the one or more processors for execution (Work Queue Assignment Functions 62/64/66/Work Schedulers 42/44/46);
retrieving (acquires/removes work items), responsive to the first message by the global scheduler, one or more work items from the shared memory; and communicating, by the global scheduler, the one or more work items for execution by the one or more processors coupled to the local scheduler (acquires/removes work items) (“…each WQAF assigns each work item created by its own virtual machine to any work queue 52, 54 or 56 in shared memory based on its assignment algorithm. The assignment algorithm may be based on work load balancing, which virtual machines are specially adapted to handle certain types of work items, etc. Each WQAF also monitors and updates a status of each virtual machine as "idle" or "not idle" as described below. Each scheduler schedules the execution of work items on its nominal work queue according to its scheduling algorithm. The scheduling algorithm may be based on a priority level assigned to the work item, the time the work item was assigned to the work queue, etc…Consequently, each WQAF can access all the work queues to add a work item to any of the work queues. In the first embodiment of the present invention, each scheduler is programmed to only remove work items from its "semi-dedicated" work queue, i.e. work queue 52 for virtual machine 12 and scheduler 42, work queue 54 for virtual machine 14 and scheduler 44 and work queue 56 for virtual machine 16 and scheduler 46. Each of these work queues is "semi-dedicated" in the first embodiment of the present invention because only the scheduler in the respective virtual machine removes work items from it but any of the WQAFs can add work items to it. (However, in another embodiment of the present invention, each scheduler can be programmed to access the other semi-dedicated work queues to remove a work item when its semi-dedicated work queue is empty.) In the state illustrated in FIG. 1, work queue 52 has one work item 70 which was acquired from virtual machine 14 by action of WQAF 64, work queue 54 is empty, and work queue 56 has three work items 72, 74 and 76. Work item 72 was acquired from virtual machine 12 by action of WQAF 62. Although not shown, work items 74 and 76 were acquired from virtual machine 14 by action of WQAF 64. Also in the state illustrated in FIG. 1, virtual machine 12 is acquiring work item 70 from work queue 52 by action of scheduler 42, and virtual machine 16 is acquiring work item 76 from work queue 56 by action of scheduler 46. A control block 58 indicates the current state, "idle" or "non idle", of the virtual machines and which, if any, of the work items from each work queue is the next to be scheduled. In the state illustrated in FIG. 1, virtual machine 12 is idle with its work queue pointer in scheduler 42 pointing to work item 70. After virtual machine 12 acquires work item 70, its work queue pointer will be "null" because there will be no work items left in work queue 52 (unless one was added in the interim). Also in the state illustrated in FIG. 1, virtual machine 14 is idle with its work queue pointer in scheduler 44 indicating "null" because there are currently no work items in work queue 54. Also in the state illustrated in FIG. 1, virtual machine 16 is "not idle"; it is currently performing a work item previously acquired from one of the work queues. The work queue pointer of scheduler 66 within virtual machine 16 is currently indicating work item 76, so this work item has not yet been removed by scheduler 46 for execution by virtual machine 16…” Col. 4 Ln. 34-45, 55-67, Col. 5 Ln. 1-31).
Donovan silent with reference to at least a first mailbox that is independent of a main memory subsystem and
one or more memory locations in a global shared cache.
Alla teaches at least a first mailbox (Frame Buffer 128) that is independent of a main memory subsystem (System Memory 124) (“…GPU 120 may be directly coupled to GMEM 121. In other words, GPU 120 may process data locally using a local storage, instead of off-chip memory. This allows GPU 120 to operate in a more efficient manner by eliminating the need of GPU 120 to read and write data via, e.g., a shared bus, which may experience heavy bus traffic. GMEM 121 may include one or more volatile or non-volatile memories or storage devices, such as, e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), and one or more registers…Processing unit 127 and/or GPU 120 may store rendered image data in a frame buffer 128, which may be may be an independent memory or may be is allocated within system memory 124. A display processor may retrieve the rendered image data from frame buffer 128 and display the rendered image data on a display…” paragraphs 0035/0036).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan with the teaching of Alla because the teaching of Alla would improve the system of Donovan by providing a technique for using a buffer that is independent the system memory such that the system memory allowed concentrate on other functions.
Atara teaches one or more memory locations in a global shared cache (Shared Cache Memory 512) (“…The cache operations component 510 may also be configured to receive one or more cache read requests to read a previously cached data item based on a provided data item key. Each cache read request may include a data item key. In response, the cache operations component 510 may be configured search or locate the provided data item key in the cache key component 514 and provide a cache read response to a requesting component, application, and/or device. If the search finds the provided data item key in the cache component 514, cache operations component 510 may be configured to use the data item key (e.g., use a pointer or reference in the data item key, etc.) to retrieve the cached data item from the shared cache memory 512. When the search finds the provided data item key, the cache read response may include the cached data item. Otherwise, the cache read response may be a null or empty response….In an embodiment, the cache key component 514 may be generally arranged to store and manage one or more data item keys 528-m-n, where each data item key (e.g., data item keys 528-1-1, etc.)) may be associated with a cached data item stored in the shared cache memory 512 (e.g., cached data item 522-1-1, etc.) and may also identify the stored cached data item (e.g., cached data item 522-1-1, etc.). To identify and/or locate a data item cached in the shared cache memory 512, each data item key may also include a pointer or reference that may point to the location where the associated data item is stored in the shared cache memory 512…” paragraph 0082/0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan and Alla with the teaching of Atara because the teaching of Atara would improve the system of Donovan and Alla by providing a hardware or software component that stores data so that future requests for that data can be served faster.
As to claim 11, see the rejection of claim 2 above.
As to claim 12, see the rejection of claim 1 above.
As to claim 13, see the rejection of claim 3 above.
As to claim 19, see the rejection of claim 1 above, expect for a central processing circuit, a memory controller; and a graphics processing circuit.
Donovan teaches a central processing circuit (CPU 23), a memory controller (Shared Memory 25); and a graphics processing circuit (Computer System 10).
As to claim 20, Donovan teaches computing system of claim 19, wherein the graphics processing circuit further comprises one or more other local schedulers comprising circuitry, and wherein the first mailbox is not writable by the one or more other local schedulers (Lock 91) (“…FIG. 7 figuratively illustrates a synchronization data structure generally designated 90 within the shared memory 25 of computer system 10. In the illustrated example, virtual machine 14 holds lock 91, virtual machine 12 has a place holder 92 waiting for the lock from virtual machine 14, and virtual machine 16 has a place holder 93 waiting for the lock from virtual machine 12. This is actually recorded in control block 58 which indicates that virtual machine 14 holds the lock and virtual machines 12 and 16 are currently waiting for the lock. The "waiter list" 95 of control block 58 indicates the order of the waiters, i.e. virtual machine 12 is first in line for the lock and virtual machine 16 will attempt to obtain the lock after virtual machine 12 obtains the lock. In the example, virtual machine 14 holds lock 91 exclusively, that is, no other virtual machine may concurrently hold this lock. Virtual machine 12 and 16 are waiting for the lock and willing to hold the lock shared, that is, they may concurrently hold the lock with each other…” Col. 8 Ln. 61-67, Col. 9 Ln. 1-11).
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara as applied to claim 3 above, and further in view of U.S. Pub. No. 2013/0155080 A1 to Nordlund et al.
As to claim 4, Donovan as modified by Alla and Atara teaches the processor as recited in claim 3, however it is silent with reference to wherein the command queue is configured to store a predetermined number of messages in a first-in-first-out mode.
Nordlund teaches wherein the command queue is configured to store a predetermined number of messages in a first-in-first-out mode (first in first out (FIFO) registers) (“… According to aspects of this disclosure, command processor 56 may initially parse the received command stream and identify each task that is to be performed by GPU 48. In addition to parsing the tasks from the command stream, command processor 56 may maintain a command queue for organizing each of the tasks to be executed by the components of GPU 48. For example, command processor 56 may schedule tasks to be executed by the components of GPU 48 (such as shader processor 52 and/or fixed function units 54) using the command queue. In some examples, the command queues may be fixed function hardware units (e.g., first in first out (FIFO) registers, or the like). In other examples, the command queues may be general memory or register units…” paragraph 0064).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Nordlund because the teaching of Nordlund would improve the system of Donovan, Alla and Atara by providing a technique for processing tasks or messages in a preferred order.
As to claim 14, see the rejection of claim 4 above.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara as applied to claim 1 above, and further in view of U.S. Pub. No. 2020/0020156 A1 to Howson et al.
As to claim 6, Donovan as modified by Alla and Atara teaches the processor as recited in claim 1, however it is silent with reference to wherein the corresponding local scheduler activates a blocking send to the global processor when a predetermined number of messages in the first mailbox is reached.
Howson teaches wherein the corresponding local scheduler activates a blocking send to the global processor when a predetermined number of messages in the first mailbox is reached (a buffer threshold is not met) (“…The scheduler 521 is configured to control the reading from and writing to the buffer 522 to ensure that the buffer does not overflow whilst also attempting to minimise the amount of time that the buffer is empty. This allows the tessellation module 500 to maximise the amount of time that the first and second tessellation stages 510 and 530 are operating to optimise throughput. In particular, the scheduler 521 monitors the number of entries currently in the buffer. If the buffer is not full (e.g. a buffer threshold is not met), the scheduler 521 sends a signal to the geometry source 300 to emit another patch of data for processing by the first tessellation stage 510. Moreover, the scheduler 521 is configured to control the tessellation instance distributor 523 by sending a control signal to send data for a tessellation instance to a tessellation pipeline in the second tessellation stage 530. The scheduler 521 controls the tessellation instance distributor 523 based on the availability of tessellation pipelines received as status information from the second tessellation stage 530…” paragraph 0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Howson because the teaching of Howson would improve the system of Donovan, Alla and Atara by providing a mechanism for controlling how messages or tasks are organized and retrieved from a data structure to allow for seamless access and retrieval.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara as applied to claims 1 and 11 above, and further in view of U.S Pub. No. 2012/0020368 A1 to Sundararaman et al.
As to claim 7, Donovan as modified by Alla and Atara teaches the processor as recited in claim 1, however it is silent with reference to wherein the corresponding local scheduler pauses execution of an instruction until an acknowledgment of successful transmission and storage of a message to the first mailbox is received.
Sundararaman teaches wherein the corresponding local scheduler pauses execution of an instruction until an acknowledgment of successful transmission and storage of a message to the first mailbox is received (Step 1014) (“…At step 1008, if the child scheduler has been scheduled, but a response has not yet been sent to root scheduler 402, then the child scheduler is pending, and SDWRR algorithm 1000 proceeds to step 1014. At step 1014, root scheduler 402 waits for an acknowledgment signal from the child scheduler before processing the corresponding child scheduler.…” paragraph 0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Sundararaman because the teaching of Sundararaman would improve the system of Donovan, Alla and Atara by providing an acknowledgment signal for acknowledge the successful or failure of a computer processing.
As to claim 16, see the rejection of claim 7 above.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara as applied to claim 1 above, and further in view of U.S. Pub. No. 2017/0185435 A1 to Dewan et al.
As to claim 8, Donovan as modified by Alla and Atara teaches the processor as recited in claim 1, however it is silent with reference to wherein the global scheduler periodically checks for new messages in the first mailbox for new messages until a predetermined timeout period is reached.
Dewan teaches wherein the global scheduler periodically checks for new messages in the first mailbox for new messages (work queue/a shared memory) until a predetermined timeout period is reached (“…In various embodiments, when an interrupt is received from a device having work associated with a secure virtual machine, a work queue is created in a shared memory. The creation of the work queue may require an exit to a virtual-machine manager, but subsequent interrupts from the device are submitted to the work queue and may not require exiting to the virtual-machine manager, thus eliminating or reducing processing overhead involved with exiting to the virtual-machine manager on each subsequent interrupt. A task-priority register may be updated to filter interrupts from the device such that interrupts from the device to the secure virtual machine are passed while interrupts from the device or other devices to other virtual machines are blocked. In some embodiments, the task-priority register remains at the updated priority until the work queue is empty; in other embodiments, a timer is configured to start when the first work request is received and to expire after a number of cycles have elapsed. The task-priority register may, upon expiration of the timer, restore the previous priority. While the work queue is not empty and while the timer is not expired, however, the secure virtual machine polls the work queue for additional pending work…Once the secure virtual machine is launched, it polls (610) the work queue 414 in the shared memory buffer for work to be executed by the secure virtual machine until the work queue 414 is empty or until the timer 408 expires…” paragraphs 0009/0027/0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Dewan because the teaching of Dewan would improve the system of Donovan, Alla and Atara by providing a technique for controlling access to a shared memory and thus optimally managing computing resources.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara as applied to claim 3 above, and further in view of U.S. Pub. No. 2006/0179436 A1 to Yasue.
As to claim 9, Donovan as modified by Alla and Atara teaches the processor as recited in claim 1, however it is silent with reference to wherein the direct point-to-point message passing between the global scheduler and the corresponding local scheduler bypasses the main memory subsystem associated with the processor wherein the point-to-point communication is initialized independent of a main memory subsystem associated with the processor.
Yasue teaches wherein the direct point-to-point message passing between the global scheduler and the corresponding local scheduler bypasses the main memory subsystem associated with the processor wherein the point-to-point communication is initialized independent of a main memory subsystem associated with the processor (“…Each processor includes a local memory within which to execute the processing tasks without resort to the main memory. In response to the application programming interface code(s), a change from the current processing task to the subsequent processing task is invoked within a given processor while maintaining the output data unit from the current processing task within the local memory of the given processor…” paragraph 0014).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Yasue because the teaching of Yasue would improve the system of Donovan, Alla and Atara by providing a technique for processing tasks without the use of a main memory and as such unburdening the processing of the main memory.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 7,251,815 B2 issued to Donovan et al. in view of W.O. No. 2022072104 A1 to Alla et al. and further in view of U.S. No. 2017/0192884 A1 to Atara as applied to claim 10 above, and further in view of U.S. Pub. No. 2017/0083364 A1 to Zhao et al.
As to claim 15, Donovan as modified by Alla and Atara teaches the method as claimed in claim 10, however it is silent with reference to wherein the first message comprises an indication that the corresponding local scheduler is in a drained state.
Zhao teaches wherein the first message comprises an indication that the corresponding local scheduler is in a drained state (empty/figure 2A) (“…In general, work stealing can be implemented in various ways, depending on the nature of the parallel processing computing system. For example, a shared memory multi-processor system may employ a shared data structure (e.g., a tree representation of the work sub-ranges) to represent the sub-division of work across the processing units. In such a system, stealing may require work-ready tasks to concurrently access and update the shared data structure via locks or atomic operations. As another example, a processing unit may utilize associated work-queues such that, when the queues are empty, the processing unit may steal work items from another processing unit and add the stolen work items the work queues of the first processing unit. In a similar manner, another processing unit may steal work items from the first processing unit's work-queues. Conventional work-stealing schemes are often rather simplistic, such as merely enabling one processing unit to share (or steal) an equally-subdivided range of a workload from a victim processing unit…In some embodiments, the heterogeneous multi-processor computing device 101 may include a runtime functionality module 210, such as an operating system (OS) level process, service, application, routine, instruction set, or thread that executes via an application processor (e.g., CPU_A 102). The runtime functionality module 210 may be configured to at least perform operations for managing work-stealing policies within the heterogeneous multi-processor computing device 101. For example, the runtime functionality module 210 may be configured to add and/or remove identifiers from the work-ready processor queues 240a-240d in response to determining tasks queues 220a-220d are empty, as well as perform operations for evaluating operating states and determining relative priorities between processing units and/or associated tasks…” paragraphs 0024/0068).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Zhao because the teaching of Zhao would improve the system of Donovan, Alla and Atara by providing a technique for determining when queues are empty and using a processing unit to steal work items from another processing unit and add the stolen work items to the work queues of the processing unit for processing and therefore, allowing for efficiently management of computing resources or processing cycle.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over CN. No. 112114951 A to Chen et al. in view of in view of U.S. Pub. No. 2022/0291952 A1 to Milojicic et al. and further in view of U.S. Pub. No. 5,428,781 issued to Duault et al. as applied to claim 10 above, and further in view of U.S. Pub. No. 2016/0054780 A1 to Bodas et al.
As to claim 17, Donovan as modified by Alla and Atara teaches the method as claimed in claim 10, however it is silent with reference to periodically checking, by the global processor, arrival of one or more new messages in the mailbox associated with the global scheduler, until at least one new message is received from the local scheduler.
Bodas teaches periodically checking (periodically), by the global processor, arrival of one or more new messages in the mailbox (job queue) associated with the global scheduler, until at least one new message is received from the local scheduler (“…Generally, a user submits a program to be executed (“job”) to a queue. The job queue refers to a data structure containing jobs to run. In one embodiment, the power aware job scheduler 302 examines the job queue at appropriate times (periodically or at certain events e.g., termination of previously running jobs) and determines if resources including the power needed to run the job can be allocated. In some cases, such resources can be allocated only at a future time, and in such cases the job is scheduled to run at a designated time in future…” paragraph 0072).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla and Atara with the teaching of Bodas because the teaching of Bodas would improve the system of Donovan, Alla and Atara by providing a mechanism for making sure that all arriving messages or tasks are processed promptly.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over CN. No. 112114951 A to Chen et al. in view of in view of U.S. Pub. No. 2022/0291952 A1 to Milojicic et al. and further in view of U.S. Pub. No. 5,428,781 issued to Duault et al. and further in view of U.S. Pub. No. 2016/0054780 A1 to Bodas et al. as applied to claim 17 above further in view of U.S. Pub. No. 2017/0185435 A1 to Dewan et al.
As to claim 18, Donovan as modified by Alla, Atara and Bodas teaches the method as claimed in claim 17, however it is silent with reference to periodically checking, by the global processor, arrival of one or more new messages in the mailbox associated with the global scheduler, until a predetermined timeout period is expired.
Dewan teaches periodically checking, by the global processor, arrival of one or more new messages in the mailbox (work queue/shared memory) associated with the global scheduler, until a predetermined timeout period is expired (“…In various embodiments, when an interrupt is received from a device having work associated with a secure virtual machine, a work queue is created in a shared memory. The creation of the work queue may require an exit to a virtual-machine manager, but subsequent interrupts from the device are submitted to the work queue and may not require exiting to the virtual-machine manager, thus eliminating or reducing processing overhead involved with exiting to the virtual-machine manager on each subsequent interrupt. A task-priority register may be updated to filter interrupts from the device such that interrupts from the device to the secure virtual machine are passed while interrupts from the device or other devices to other virtual machines are blocked. In some embodiments, the task-priority register remains at the updated priority until the work queue is empty; in other embodiments, a timer is configured to start when the first work request is received and to expire after a number of cycles have elapsed. The task-priority register may, upon expiration of the timer, restore the previous priority. While the work queue is not empty and while the timer is not expired, however, the secure virtual machine polls the work queue for additional pending work…Once the secure virtual machine is launched, it polls (610) the work queue 414 in the shared memory buffer for work to be executed by the secure virtual machine until the work queue 414 is empty or until the timer 408 expires…” paragraphs 0009/0027/0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Donovan, Alla, Atara and Bodas with the teaching of Dewan because the teaching of Dewan would improve the system of Donovan, Alla, Atara and Bodas as modified by Alla and Atara by providing a technique for controlling access to a shared memory and thus optimally managing computing resources.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on additional references not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHARLES E ANYA/Primary Examiner, Art Unit 2194
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