DETAILED ACTION
This Office Action is in response to the Remarks and Amendments filed on 26 March 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 10, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2022/0384202 A1; hereinafter Lin).
In regards to claim 1, Lin teaches a semiconductor device, comprising:
a backside power rail (fig. 29: (291)) formed in a backside of a wafer (e.g. (32)) [0081];
a via-to-backside power rail (VBPR) gate contact connecting the backside power rail to at least one gate of a first transistor (e.g. fig. 5A: evidenced by (150)) [0030]; and
at least one via-to-backside power rail (VBPR) source/drain (S/D) contact (fig. 20: (240)) [0040] configured to connect the backside power rail to at least one S/D region of a second transistor, wherein the VBPR gate contact at least partially vertically overlaps a gate cut region between the first transistor and the second transistor (e.g. fig. 29) [0081-0082].
In regards to claim 9, Lin teaches the limitations discussed above in addressing claim 1. Lin further teaches the limitations further comprising a backside power distribution network (BSPDN) connected to the backside power rail (fig. 29) [0081].
In regards to claim 10, Lin teaches the limitations discussed above in addressing claim 9. Lin further teaches the limitations further comprising an interlayer dielectric (ILD) fill (210) arranged at least between a portion of an edge of the BSPDN, the backside power rail and at least a respective shallow trench isolation (STI) connected to the first transistor and/or the second transistor (fig. 15) [0060].
In regards to claim 20, Lin teaches a method of forming a semiconductor device, comprising:
forming a backside power rail (fig. 29: (291)) in a backside of a wafer (e.g. (32)) [0081];
connecting a via-to-backside power rail (VBPR) gate contact to at least one gate of a first transistor (e.g. fig. 5A: evidenced by (150)) [0030];
connecting at least one via-to-backside power rail (VBPR) source/drain (S/D) contact (fig. 20: (240)) [0040] to at least one S/D region of a second transistor; and
arranging the VBPR gate contact to at least partially vertically overlap a gate cut region between the first transistor and the second transistor (e.g. fig. 29) [0081-0082].
Claim Rejections - 35 USC § 103
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
Claim(s) 2-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 above, in view of Xie et al. (US 2023/0086033 A1; hereinafter Xie).
In regards to claim 2, Lin teaches the limitations discussed above in addressing claim 1. Lin appears to be silent as to, but does not preclude, the limitations wherein the VBPR gate contact is adjacent an continuous RX region. Xie teaches the limitations wherein the VBPR gate contact is adjacent an continuous RX region ([0061]: gates contacts over multiple continuous active regions). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lin with the aforementioned limitations taught by Xie such that the device of Lin has the layout taught by Xie to have a layout that prevents shorts (Lin [0061]).
In regards to claim 3, Lin teaches the limitations discussed above in addressing claim 1. Lin appears to be silent as to, but does not preclude, the limitations wherein the gate of the first transistor comprises a dummy gate tied-down to the backside power rail [0032]. Xie teaches the limitations wherein the gate of the first transistor comprises a dummy gate tied-down to the backside power rail [0032]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lin with the aforementioned limitations taught by Xie such that the device of Lin has the layout taught by Xie to have a layout that prevents shorts (Lin [0061]).
In regards to claim 4, the combination of Lin and Xie teaches the limitations discussed above in addressing claim 3. Lin further teaches the limitations wherein the dummy gate comprises a High-K Metal Gate (HKMG) (figs. 17: (220)) [0064].
In regards to claim 5, Lin teaches the limitations discussed above in addressing claim 1. Lin appears to be silent as to, but does not preclude, the limitations wherein a gate of the second transistor comprises an active gate. Xie teaches the limitations wherein a gate of the second transistor comprises an active gate ([0061]: gates contacts over multiple continuous active regions). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lin with the aforementioned limitations taught by Xie such that the device of Lin has the layout taught by Xie to have a layout that prevents shorts (Lin [0061]).
In regards to claim 6, Lin teaches the limitations discussed above in addressing claim 1. Lin appears to be silent as to, but does not preclude, the limitations further comprising a Middle-of-Line (MOL) connection to the active gate of the second transistor (figs. 8) ([0015], [0056-0057]). Xie teaches the limitations further comprising a Middle-of-Line (MOL) connection to the active gate of the second transistor (figs. 8) ([0015], [0056-0057]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lin with the aforementioned limitations taught by Xie such that the device of Lin has the layout taught by Xie to have a layout that prevents shorts (Lin [0061]).
In regards to claim 7, the combination of Lin and Xie teaches the limitations discussed above in addressing claim 6. Xie further teaches the limitations further comprising a Back-end-of-line (BEOL) connected to the MOL connection of the second transistor (figs. 8) ([0015], [0056-0057]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lin with the aforementioned limitations taught by Xie such that the device of Lin has the layout taught by Xie to have a layout that prevents shorts (Lin [0061]).
In regards to claim 8, the combination of Lin and Xie teaches the limitations discussed above in addressing claim 7. Lin further teaches the limitations further comprising a carrier wafer connected to the BEOL (fig. 21) [0074].
Response to Arguments
Applicant's arguments filed 26 March 2023 have been fully considered but they are not persuasive. Examiner thanks Applicant for the Remarks dated 26 March 2026 (hereinafter Remarks). Examiner acknowledges the Remarks pertaining to the Claim Objections set forth in the prior Office Action (hereinafter Office Action).
In regards to claim 1, the Remarks appear to assert that the prior art reference Lin (citation in the Office Action above) does not disclose "a via-to-backside power rail (VBPR) gate contact connecting the backside power rail to at least one gate of a first transistor" as recited in claim 1; however, Examiner respectfully submits that Lin teaches a VBPR connected to a gate of a transistor.
For further clarification, the prior Office Action states, on pages 2-3, in regards to claim 1, that a VBPR is "evidenced by (150)" in fig 5A. When Lin is taken as a whole (see also [0014]), it can be seen that (150) is used in a process to form backside power rails, backside metal vias, and backside contacts. In other words, (150) is a dummy structure that evidences the later formation of a VBPR gate contact. Furthermore, fig. 5A (see also [0017]) depicts a gate region.
In light of this discussion, Examiner respectfully submits that Lin teaches a VBPR (formed in an area evidenced by (150) connected to a gate ([0014], [0017], [0030])).
The Remarks appear to further assert that Lin does not mention overlapping of the VBPR gate with the gate cut region; however Lin teaches in paragraph [0081-0082] and fig. 29, the element (291), which is a backside power rail that overlaps multiple regions including a gate cut (gate separation/isolation) region (e.g. (291) overlaps (220) etc.).
In light of this discussion, Examiner respectfully submits that Lin teaches the limitations of claim1 and that claim 1 stand properly rejected.
Finally, Examiner acknowledges the Remarks pertaining to the claim rejections under 35 U.S.C. § 103 as being contingent on the assertions discussed above addressing the traversals of the rejections of claim 1 and that these Remarks are considered to have been addressed as a result of the discussions pertaining to the rejection of claim 1 above.
Allowable Subject Matter
Claims 11-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 11, Lin teaches a method of forming a semiconductor device, comprising:
forming a via-to-backside power rail (VBPR) gate contact in a frontside of a wafer at an edge of a gate of a first transistor (e.g. fig. 5A: evidenced by (150)) [0030];
filling the VBPR gate contact with a dummy gate material (154) [0031];
forming operations including performing gate patterning (e.g. fig. 5A: depicted by (150)) [0030], a bottom sacrificial layer removal (e.g. depicted by (152) being patterned) followed by bottom dielectric isolation (BDI) (e.g. fig. 5B: (152) is fully formed and patterned) [0031] and gate spacer formation (160) [0034] to recess exposed alternating layers of channel (fig. 6B: (124)) [0035] and sacrificial layers (122) [0035], selective sacrificial layer indentation (fig. 7B: (R2)) [0036] and inner spacer formation (figs. 8: (170)) [0037], source/drain (S/D) epitaxial growth (fig. 14: (200)) [0057], an interlayer dielectric (ILD) fill (fig. 15: (210)) [0060], dummy gate open chemical mechanical planarization (CMP) (figs. 17) ([0008], [0017], [0064]);
removing the dummy gate material from an opened dummy gate and VBPR gate contact, tie-down, selectively releasing sacrificial layers from channel layers (e.g. figs. 15-16) [0062] and forming a replacement High-K Metal Gate (HKMG) (220) in place of the dummy gate material (figs. 17) [0064];
forming, on the backside of the wafer, a power rail (fig. 29: (291)) [0081] connecting to the VBPR gate contact, and connecting a backside power distribution network (BSPDN) to the backside power rail [0081-0082].
Lin appears to be silent as to, but does not preclude, the limitations of forming a gate tie down comprising: a gate cut patterning. Xie (citation in the prior Office Action dated 29 December 2025) teaches the limitations of forming a gate tie down [0059] comprising: a gate cut patterning (figs. 8: (128)) [0056]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lin with the aforementioned limitations taught by Xie such that the device of Lin has the layout taught by Xie to have a layout that prevents shorts (Lin [0061]).
The combination of Lin and Xie does not appear to teach the limitations wherein the ILD fill is arranged at least between a portion of an edge of the BSPDN, the backside power rail, and at least a respective shallow trench isolation (STI) connected to the first transistor and/or a second transistor.
The claims of the application at hand that depend from allowable claims are allowable because they respectively depend, directly or indirectly, from the allowable claims of the application at hand. Therefore, the dependent claims in question incorporate the allowable limitations of the claims from which they depend.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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