Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 – 16, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US20020019970A1 (Araki) in view of US6665845B1 (Aingaran) and further in view of US20050055654A1 (Lin).
In regards to claim 1 (Araki) shows a wiring quality test method, comprising:
for each signal to be tested, comparing the wiring result topological structure with the expected topological structure, to obtain a topological structure comparison result corresponding to the signal to be tested; Araki [0031] teaches computing minimum distance required and verifying whether measured distance is shorter than required distance for comparison analysis. Araki [0048] teaches determining distance from segment to nearest plane edge for comparison evaluation.
in response to determining that the topological structure comparison result is greater than the preset threshold, determining a test result indicating that wiring for the signal to be tested is inappropriate; Araki [0031] teaches computing minimum distance required and verifying threshold-based comparison analysis for determining inappropriate wiring. Araki [0048] teaches determining distance from segment to nearest edge for comparison evaluation.
generating a quality test report based on test results of the signals to be tested; Araki [0057] teaches outputting countermeasure instruction message number 1 corresponding to wiring name for display.
Araki differs from the claimed invention in that it does not explicitly disclose determining, based on a wiring layout, a respective wiring result topological structure and a respective expected topological structure corresponding to each signal to be tested in a set of signals to be tested; wherein the expected topological structure is obtained based on a position of at least one connection point in the wiring layout; comparing the topological structure comparison result with a preset threshold;
Aingaran teaches determining, based on a wiring layout, a respective wiring result topological structure and a respective expected topological structure corresponding to each signal to be tested in a set of signals to be tested; Aingaran [Column 13 Lines 20 - 40] teaches traversing each possible victim metal line of the layout using a traversal window to identify and analyze topological structures. Aingaran [Column 14 Lines 65 - Column 15 Lines 20] teaches extracting topology-based data structure from layout including length, average width, and coupling length parameters for structural analysis.
Aingaran teaches wherein the expected topological structure is obtained based on a position of at least one connection point in the wiring layout; Aingaran [Table 4] teaches topology-based parameter estimation using position information including length, average width, and coupling length based on connection point positions.
Aingaran differs from the claimed invention in that it does not explicitly disclose comparing the topological structure comparison result with a preset threshold;
Lin teaches comparing the topological structure comparison result with a preset threshold; Lin [0031] teaches comparing area of each overlapped region to area threshold value. Lin [0034] teaches marking regions having area ratio smaller than threshold value.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
In regards to claim 11 (Araki) shows wiring quality test method according to claim 1:
wherein for each signal to be tested, comparing the wiring result topological structure with the expected topological structure, to obtain the topological structure comparison result corresponding to the signal to be tested comprises; Araki [0031] teaches computing minimum distance required and verifying whether measured distance is shorter than required distance for comparison analysis. Araki [0048] teaches determining distance from segment to nearest plane edge for comparison evaluation.
comparing the actual wiring length with the expected wiring length, to obtain the topological structure comparison result; Araki [0082] teaches comparing measured distances with calculated values, thereby teaching length comparison methodology.
Araki differs from the claimed invention in that it does not explicitly disclose calculating an actual wiring length corresponding to the wiring result topological structure and an expected wiring length corresponding to the expected topological structure;
Aingaran teaches calculating an actual wiring length corresponding to the wiring result topological structure and an expected wiring length corresponding to the expected topological structure; Aingaran [Table 4] teaches calculating total length and coupling length parameters for comprehensive topological analysis.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring length comparison methodology by integrating Aingaran's comprehensive length calculation capabilities with Araki's comparison and ratio-based analysis techniques for improved topological structure evaluation.
In regards to claim 12 (Araki) shows wiring quality test method according to claim 11:
wherein comparing the actual wiring length with the expected wiring length, to obtain the topological structure comparison result comprises; Araki [0082] teaches comparing measured distances with calculated values, thereby teaching length comparison methodology.
taking a ratio of the total actual wiring length to the total expected wiring length as the topological structure comparison result; Araki [0082] teaches comparing measured distance of 0.16 mm with calculated value K3×h=2.0 mm, thereby teaching ratio-based comparison calculations.
Araki differs from the claimed invention in that it does not explicitly disclose wherein the actual wiring length comprises a total actual wiring length, the total actual wiring length being a total length of all actual connection lines in the wiring result topological structure; the expected wiring length comprises a total expected wiring length, the total expected wiring length being a total length of all expected connection lines in the expected topological structure;
Aingaran teaches wherein the actual wiring length comprises a total actual wiring length, the total actual wiring length being a total length of all actual connection lines in the wiring result topological structure; Aingaran [Table 4] teaches calculating total length of net from source to destination for complete structural analysis.
Aingaran teaches the expected wiring length comprises a total expected wiring length, the total expected wiring length being a total length of all expected connection lines in the expected topological structure; Aingaran [Table 4] teaches determining expected length parameters based on topological analysis methodology.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring length comparison methodology by integrating Aingaran's comprehensive length calculation capabilities with Araki's comparison and ratio-based analysis techniques for improved topological structure evaluation.
In regards to claim 13 (Araki) shows wiring quality test method according to claim 11:
wherein comparing the actual wiring length with the expected wiring length, to obtain the topological structure comparison result comprises; Araki [0082] teaches comparing measured distances with calculated values, thereby teaching length comparison methodology.
comparing each layer-wise actual wiring length in the at least one-layer wise actual wiring length with a respective layer-wise expected wiring length in the at least one-layer wise expected wiring length to obtain at least one metal layer ratio; Araki [0082] teaches comparing measured distances with calculated values for ratio-based analysis methodology.
taking the at least one metal layer ratio as the topological structure comparison result; Araki [0082] teaches using ratio-based comparison results for structural evaluation methodology.
Araki differs from the claimed invention in that it does not explicitly disclose wherein the actual wiring length comprises at least one layer-wise actual wiring length, the at least one layer-wise actual wiring length being at least one actual connection line length corresponding to at least one metal layer in the wiring result topological structure; the expected wiring length comprises at least one layer-wise expected wiring length, the at least one layer-wise expected wiring length being at least one expected connection line length corresponding to the at least one metal layer;
Aingaran teaches wherein the actual wiring length comprises at least one layer-wise actual wiring length, the at least one layer-wise actual wiring length being at least one actual connection line length corresponding to at least one metal layer in the wiring result topological structure; Aingaran [Table 4] teaches measuring full coverage and half coverage portions of metal lines by orthogonal layers, thereby teaching layer-wise length determination.
Aingaran teaches the expected wiring length comprises at least one layer-wise expected wiring length, the at least one layer-wise expected wiring length being at least one expected connection line length corresponding to the at least one metal layer; Aingaran [Table 4] teaches calculating estimated capacitance parameters based on coverage length, thereby teaching expected layer-wise length calculation.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring length comparison methodology by integrating Aingaran's comprehensive length calculation capabilities with Araki's comparison and ratio-based analysis techniques for improved topological structure evaluation.
In regards to claim 14 (Araki) shows wiring quality test method according to claim 1, further comprising:
after generating the quality test report based on the test results of the signals to be tested; Araki [0057] teaches outputting messages after completing analysis, thereby teaching sequential report generation processing.
displaying the test result on the wiring layout based on the quality test report; Araki [0057] teaches outputting countermeasure instruction message number 1 corresponding to the wiring name for display. Araki [0084] teaches outputting the countermeasure instruction message corresponding to the wiring name E1 for display.
In regards to claim 15 (Araki) shows wiring quality test method according to claim 14:
wherein displaying the test result on the wiring layout based on the quality test report comprises; Araki [0057] teaches outputting countermeasure instruction message number 1 corresponding to the wiring name for display. Araki [0084] teaches outputting the countermeasure instruction message corresponding to the wiring name E1 for display.
receiving a selection operation for the set of signals to be tested, and determining a signal to be displayed; Araki [0075] teaches extracting the wiring name E1 of the board wiring from the database storing data regarding the circuit board to be checked.
determining a test result corresponding to the signal to be displayed based on the quality test report; Araki [0084] teaches determining output messages based on analysis results, thereby teaching result determination from reports.
in response to the test result indicating that wiring for the signal to be displayed is inappropriate, highlighting the inappropriate wiring on the wiring layout, thereby completing display of the test result on the wiring layout; Araki [0084] teaches outputting the countermeasure instruction message corresponding to the wiring name E1 for display to highlight problematic wiring.
In regards to claim 16 (Araki) shows a wiring quality test apparatus, comprising:
a memory, configured to store executable instructions; Araki [0030] teaches the system may be realized by a computer system including a CPU, a memory, and user interface units.
a processor, configured to execute the executable instructions stored in the memory to perform the following operations comprising; Araki [0104] teaches providing a computer program for executing the process steps according to the wiring configuration check system.
for each signal to be tested, comparing the wiring result topological structure with the expected topological structure, to obtain a topological structure comparison result corresponding to the signal to be tested; Araki [0031] teaches computing minimum distance required and verifying whether measured distance is shorter than required distance for comparison analysis. Araki [0048] teaches determining distance from segment to nearest plane edge for comparison evaluation.
in response to determining that the topological structure comparison result is greater than the preset threshold, determining a test result indicating that wiring for the signal to be tested is inappropriate; Araki [0102] teaches determination equation dist≦K3×h with predetermined constant K3. Araki [0103] teaches determination equation dist≦K4×a with predetermined constant K4. Araki [0031] teaches computing minimum distance required and verifying threshold-based comparison analysis for determining inappropriate wiring.
generating a quality test report based on test results of the signals to be tested; Araki [0057] teaches outputting countermeasure instruction message number 1 corresponding to the wiring name for display. Araki [0058] teaches outputting another countermeasure instruction message number 2 corresponding to the wiring name for display.
Araki differs from the claimed invention in that it does not explicitly disclose determining, based on a wiring layout, a respective wiring result topological structure and a respective expected topological structure corresponding to each signal to be tested in a set of signals to be tested; wherein the expected topological structure is obtained based on a position of at least one connection point in the wiring layout; comparing the topological structure comparison result with a preset threshold;
Aingaran teaches determining, based on a wiring layout, a respective wiring result topological structure and a respective expected topological structure corresponding to each signal to be tested in a set of signals to be tested; Aingaran [Column 13 Lines 20 - 40] teaches traversing each possible victim metal line of the layout using a traversal window to identify and analyze topological structures. Aingaran [Column 14 Lines 65 - Column 15 Lines 20] teaches extracting topology-based data structure from layout including length, average width, and coupling length parameters for structural analysis.
Aingaran teaches wherein the expected topological structure is obtained based on a position of at least one connection point in the wiring layout; Aingaran [Table 4] teaches topology-based parameter estimation using position information including length, average width, and coupling length based on connection point positions.
Aingaran differs from the claimed invention in that it does not explicitly disclose comparing the topological structure comparison result with a preset threshold;
Lin teaches comparing the topological structure comparison result with a preset threshold; Lin [0031] teaches comparing area of each overlapped region to area threshold value. Lin [0034] teaches marking regions having area ratio smaller than threshold value.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
In regards to claim 21 (Araki) does not show: wherein comparing the topological structure comparison result with a preset threshold comprises comparing a ratio of an actual wiring total length to an expected wiring total length corresponding to a signal to be tested with a preset total length ratio threshold;
Lin teaches wherein comparing the topological structure comparison result with a preset threshold comprises comparing a ratio of an actual wiring total length to an expected wiring total length corresponding to a signal to be tested with a preset total length ratio threshold; Lin [0033] teaches calculating the area ratio RA by the formula RA equals Avia divided by Aover for determining ratios between actual measured parameters and expected structural parameters. Lin [0034] teaches setting a threshold value in advance and marking output regions having area ratio RA smaller than the threshold value, thereby teaching comparison of calculated ratios against preset ratio threshold values for quality assessment.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
Claims 2 – 10, and 17 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over US20020019970A1 (Araki) in view of US6665845B1 (Aingaran) and in view of US20050055654A1 (Lin) as applied in claim 1 and 16 above, respectively, and further in view of US20040243964A1 (McElvain).
In regards to claim 2 (Araki) shows the wiring quality test method according to claim 1:
determining the at least one connection point corresponding to each signal to be tested based on the wiring layout and the wiring circuit diagram; Araki [0046-0047] teaches extracting and investigating wiring segments and connection points from the layout.
determining the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested; Araki [0046] teaches extracting a segment A from a group comprising a plurality of minimum configuration units of wiring. Araki [0047] teaches investigating a wiring configuration of the segment A to specify connection points.
determining the respective wiring result topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested; Araki [0047] teaches investigating wiring configuration to specify an edge of the plane nearest thereto based on connection point analysis. Araki [0046] teaches extracting actual wiring segments from the layout. Araki [0048] teaches determining actual distances from segments to plane edges for result structure analysis.
Araki differs from the claimed invention in that it does not explicitly disclose wherein determining, based on the wiring layout, the respective wiring result topological structure and the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested comprises; obtaining a wiring circuit diagram corresponding to the wiring layout;
Aingaran teaches wherein determining, based on the wiring layout, the respective wiring result topological structure and the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested comprises; Aingaran [Column 13 Lines 20 - 40] teaches traversing each possible victim metal line of the layout using a traversal window to identify and analyze topological structures for both actual and expected configurations.
Aingaran differs from the claimed invention in that it does not explicitly disclose obtaining a wiring circuit diagram corresponding to the wiring layout;
McElvain teaches obtaining a wiring circuit diagram corresponding to the wiring layout; McElvain [0040] teaches that a logic synthesis tool creates a logic element network and generates a technology specific netlist. McElvain [0041] teaches that a placement and routing tool uses the design result of the synthesis tool for design layout.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to improve wiring quality testing accuracy by incorporating McElvain's circuit diagram generation with Aingaran's topological analysis and Araki's connection point extraction for comprehensive layout-based quality assessment.
In regards to claim 3 (Araki) does not show the wiring quality test method according to claim 2: wherein the at least one connection point comprises connection points of N levels, N being greater than or equal to 1; wherein determining the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested comprises; in the wiring layout, taking the at least one connection point corresponding to each signal to be tested as at least one first-level connection point, and determining a first-level intermediate base line based on the at least one first-level connection point; determining connection points having an axial distance less than an ith-level preset threshold in (i-1)th-level connection points as ith-level connection points; determining an ith-level intermediate base line based on the ith-level connection points; wherein i is greater than or equal to 2 and less than or equal to N-1, the axial distance is a distance in a first axial direction or a second axial direction, and the first axial direction is perpendicular to the second axial direction; continuing to determine (i+1)th-level connection points and an (i+1)th-level intermediate base line until Nth-level connection points and an Nth-level intermediate base line are determined; determining an expected connection line of each level based on connection points of each level and an intermediate base line of each level in the connection points of N levels and intermediate base lines of N levels, thereby determining expected connection lines of N levels; using the at least one connection point and the expected connection lines of N levels to form the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested;
Aingaran teaches wherein determining the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested comprises; Aingaran [Column 13 Lines 20 - 40] teaches extracting topology-based data structure from layout for expected topological structure determination.
Aingaran differs from the claimed invention in that it does not explicitly disclose wherein the at least one connection point comprises connection points of N levels, N being greater than or equal to 1; in the wiring layout, taking the at least one connection point corresponding to each signal to be tested as at least one first-level connection point, and determining a first-level intermediate base line based on the at least one first-level connection point; determining connection points having an axial distance less than an ith-level preset threshold in (i-1)th-level connection points as ith-level connection points; determining an ith-level intermediate base line based on the ith-level connection points; wherein i is greater than or equal to 2 and less than or equal to N-1, the axial distance is a distance in a first axial direction or a second axial direction, and the first axial direction is perpendicular to the second axial direction; continuing to determine (i+1)th-level connection points and an (i+1)th-level intermediate base line until Nth-level connection points and an Nth-level intermediate base line are determined; determining an expected connection line of each level based on connection points of each level and an intermediate base line of each level in the connection points of N levels and intermediate base lines of N levels, thereby determining expected connection lines of N levels; using the at least one connection point and the expected connection lines of N levels to form the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested;
McElvain teaches wherein the at least one connection point comprises connection points of N levels, N being greater than or equal to 1; McElvain [0068] teaches calculating the instance sensitivity at every instance in the design. McElvain [0070] teaches performing a backward breadth first traversal to compute the backward path sensitivity at instance I that has drive instances. McElvain [0071] teaches performing a forward breadth first traversal to compute the forward path sensitivity at instance I that has load instances.
McElvain teaches in the wiring layout, taking the at least one connection point corresponding to each signal to be tested as at least one first-level connection point, and determining a first-level intermediate base line based on the at least one first-level connection point; McElvain [0105] teaches that the position of the drive element A and the positions of the load elements B, C and D determine the shape of the net, thereby teaching position-based baseline determination.
McElvain teaches determining connection points having an axial distance less than an ith-level preset threshold in (i-1)th-level connection points as ith-level connection points; McElvain [0070] teaches performing backward breadth first traversal to compute backward path sensitivity at instance I that has drive instances, thereby teaching hierarchical distance-based connection point determination.
McElvain teaches determining an ith-level intermediate base line based on the ith-level connection points; McElvain [0105] teaches that the position of the drive element A and the positions of the load elements B, C and D determine the shape of the net, thereby teaching intermediate base line determination based on connection points.
McElvain teaches wherein i is greater than or equal to 2 and less than or equal to N-1, the axial distance is a distance in a first axial direction or a second axial direction, and the first axial direction is perpendicular to the second axial direction; McElvain [0107] teaches that distance may be estimated as Manhattan distance plus twice the length of the short side of the bounding box, thereby teaching directional distance analysis with perpendicular axes.
McElvain teaches continuing to determine (i+1)th-level connection points and an (i+1)th-level intermediate base line until Nth-level connection points and an Nth-level intermediate base line are determined; McElvain [0071] teaches performing forward breadth first traversal to compute forward path sensitivity with iterative processing until completion.
McElvain teaches determining an expected connection line of each level based on connection points of each level and an intermediate base line of each level in the connection points of N levels and intermediate base lines of N levels, thereby determining expected connection lines of N levels; McElvain [0072] teaches determining the path sensitivity for instance I from the maximum of forward and backward path sensitivity calculations.
McElvain teaches using the at least one connection point and the expected connection lines of N levels to form the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested; McElvain [0072] teaches forming comprehensive path sensitivity analysis using multiple hierarchical levels for complete signal evaluation.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to enhance wiring quality testing with hierarchical analysis capabilities by integrating McElvain's multi-level sensitivity processing with Aingaran's topological structure determination and Araki's quality testing framework for comprehensive geometric construction and evaluation.
In regards to claim 4 (Araki modified by Aingaran) does not show the wiring quality test method according to claim 3: wherein determining the expected connection line of each level based on the connection points of each level and the intermediate base line of each level in the connection points of N levels and the intermediate base lines of N levels, thereby determining the expected connection lines of N levels comprises; determining an Nth-level expected connection line based on the Nth-level connection points and the Nth-level intermediate base line; determining a jth-level expected connection line based on jth-level connection points, a jth-level intermediate base line, and a (j+1)th-level expected connection line; wherein j is greater than or equal to 2 and less than or equal to N-1; continuing to determine a (j-1)th-level expected connection line until a first-level expected connection line is determined, thereby determining the expected connection lines of N levels.
McElvain teaches wherein determining the expected connection line of each level based on the connection points of each level and the intermediate base line of each level in the connection points of N levels and the intermediate base lines of N levels, thereby determining the expected connection lines of N levels comprises; McElvain [0072] teaches determining path sensitivity using hierarchical analysis across multiple levels, thereby teaching multi-level connection line determination methodology.
McElvain teaches determining an Nth-level expected connection line based on the Nth-level connection points and the Nth-level intermediate base line; McElvain [0072] teaches determining the path sensitivity for instance I from maximum forward and backward sensitivity calculations.
McElvain teaches determining a jth-level expected connection line based on jth-level connection points, a jth-level intermediate base line, and a (j+1)th-level expected connection line; McElvain [0071] teaches performing forward breadth first traversal to compute forward path sensitivity using hierarchical instance relationships.
McElvain teaches wherein j is greater than or equal to 2 and less than or equal to N-1; McElvain [0070] teaches performing backward breadth first traversal with hierarchical processing where instances have drive relationships, thereby teaching level-based processing with defined ranges.
McElvain teaches continuing to determine a (j-1)th-level expected connection line until a first-level expected connection line is determined, thereby determining the expected connection lines of N levels. McElvain [0070] teaches performing backward breadth first traversal to compute backward path sensitivity with iterative level-by-level processing until completion.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to enhance wiring quality testing with hierarchical analysis capabilities by integrating McElvain's multi-level sensitivity processing with Aingaran's topological structure determination and Araki's quality testing framework for comprehensive geometric construction and evaluation.
In regards to claim 5 (Araki modified by Aingaran) shows the wiring quality test method according to claim 3: wherein determining the first-level intermediate base line based on the at least one first-level connection point comprises; determining two first-level edge connection points having a largest distance in the first axial direction among the at least one first-level connection point; determining the first-level intermediate base line passing through a midpoint of a connection line between the two first-level edge connection points and in the second axial direction;
McElvain teaches wherein determining the first-level intermediate base line based on the at least one first-level connection point comprises; McElvain [0105] teaches determining net shape based on positions of drive and load elements for baseline establishment.
McElvain teaches determining two first-level edge connection points having a largest distance in the first axial direction among the at least one first-level connection point; McElvain [0105] teaches analyzing positions of drive element A and load elements B, C, D to determine maximum distance relationships for edge point identification.
McElvain teaches determining the first-level intermediate base line passing through a midpoint of a connection line between the two first-level edge connection points and in the second axial direction; McElvain [0107] teaches estimating wire length using Manhattan distance calculations, thereby teaching midpoint-based baseline determination methodology.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to enhance wiring quality testing with hierarchical analysis capabilities by integrating McElvain's multi-level sensitivity processing with Aingaran's topological structure determination and Araki's quality testing framework for comprehensive geometric construction and evaluation.
In regards to claim 6 (Araki modified by Aingaran) shows the wiring quality test method according to claim 5: wherein determining the ith-level intermediate base line based on the ith-level connection points comprises; determining two ith-level edge connection points having a largest distance in the first axial direction among the ith-level connection points; determining the ith-level intermediate base line passing through a midpoint of a connection line between the two ith-level edge connection points and in the second axial direction;
McElvain teaches wherein determining the ith-level intermediate base line based on the ith-level connection points comprises; McElvain [0105] teaches determining net shape based on element positions for hierarchical baseline establishment.
McElvain teaches determining two ith-level edge connection points having a largest distance in the first axial direction among the ith-level connection points; McElvain [0105] teaches analyzing element positions to determine maximum distance relationships for edge point identification.
McElvain teaches determining the ith-level intermediate base line passing through a midpoint of a connection line between the two ith-level edge connection points and in the second axial direction; McElvain [0107] teaches using geometric calculations for distance estimation, thereby teaching midpoint-based baseline determination for hierarchical levels.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to enhance wiring quality testing with hierarchical analysis capabilities by integrating McElvain's multi-level sensitivity processing with Aingaran's topological structure determination and Araki's quality testing framework for comprehensive geometric construction and evaluation.
In regards to claim 7 (Araki modified by Aingaran) shows the wiring quality test method according to claim 3: wherein determining the expected connection line of each level based on the connection points of each level and the intermediate base line of each level in the connection points of N levels and the intermediate base lines of N levels, thereby determining the expected connection lines of N levels comprises; for a first connection point that does not satisfy a preset distance condition in the connection points of each level in the connection points of N levels; connecting the first connection point of each level to the intermediate base line of the level corresponding to the first connection point to form a perpendicular segment, so as to obtain a first sub-expected connection line corresponding to the first connection point; for a second connection point that satisfies the preset distance condition in the connection points of each level in the connection points of N levels; connecting the intermediate base line of each level corresponding to the second connection point of the level to the intermediate reference line of a next level to form a common perpendicular segment, so as to obtain a second sub-expected connection line corresponding to the second connection point; wherein the first sub-expected connection line and the second sub-expected connection line are taken as the expected connection line of each level; until the connection points of N levels have been connected, determining the expected connection lines of N levels;
McElvain teaches wherein determining the expected connection line of each level based on the connection points of each level and the intermediate base line of each level in the connection points of N levels and the intermediate base lines of N levels, thereby determining the expected connection lines of N levels comprises; McElvain [0072] teaches determining path sensitivity using hierarchical analysis across multiple levels, thereby teaching multi-level connection line determination methodology.
McElvain teaches for a first connection point that does not satisfy a preset distance condition in the connection points of each level in the connection points of N levels; McElvain [0107] teaches estimating distance as Manhattan distance plus twice the length of the short side of the bounding box, thereby teaching distance-based connection methodologies.
McElvain teaches connecting the first connection point of each level to the intermediate base line of the level corresponding to the first connection point to form a perpendicular segment, so as to obtain a first sub-expected connection line corresponding to the first connection point; McElvain [0107] teaches distance estimation using Manhattan distance methodology, thereby teaching perpendicular segment formation for connection analysis.
McElvain teaches for a second connection point that satisfies the preset distance condition in the connection points of each level in the connection points of N levels; McElvain [0107] teaches that net is selected when estimated variation meets specific criteria, thereby teaching condition-based point selection.
McElvain teaches connecting the intermediate base line of each level corresponding to the second connection point of the level to the intermediate reference line of a next level to form a common perpendicular segment, so as to obtain a second sub-expected connection line corresponding to the second connection point; McElvain [0113] teaches partitioning sinks of net between original and replicated drive instances, thereby teaching multi-level connection methodologies.
McElvain teaches wherein the first sub-expected connection line and the second sub-expected connection line are taken as the expected connection line of each level; McElvain [0072] teaches combining path sensitivity analysis components into comprehensive connection line structures.
McElvain teaches until the connection points of N levels have been connected, determining the expected connection lines of N levels; McElvain [0072] teaches iterative processing until all hierarchical levels are completed for comprehensive analysis.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to enhance wiring quality testing with hierarchical analysis capabilities by integrating McElvain's multi-level sensitivity processing with Aingaran's topological structure determination and Araki's quality testing framework for comprehensive geometric construction and evaluation.
In regards to claim 8 (Araki) shows the wiring quality test method according to claim 2:
wherein determining the respective wiring result topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested comprises; Araki [0047] teaches investigating wiring configuration to specify an edge of the plane nearest thereto based on connection point analysis. Araki [0046] teaches extracting actual wiring segments from the layout. Araki [0048] teaches determining actual distances from segments to plane edges for result structure analysis.
Araki differs from the claimed invention in that it does not explicitly disclose determining at least one actual wiring pattern connected to the at least one connection point in the wiring layout; determining a type of each actual wiring pattern in the at least one actual wiring pattern, and simplifying each actual wiring pattern, to obtain at least one actual connection line corresponding to the at least one actual wiring pattern; using the at least one connection point and the at least one actual connection line to form the respective wiring result topological structure corresponding to each signal to be tested in the set of signals to be tested;
Aingaran teaches determining at least one actual wiring pattern connected to the at least one connection point in the wiring layout; Aingaran [Column 13 Lines 20 - 40] provides better coverage for actual wiring pattern determination through layout traversal methodology.
Aingaran teaches determining a type of each actual wiring pattern in the at least one actual wiring pattern, and simplifying each actual wiring pattern, to obtain at least one actual connection line corresponding to the at least one actual wiring pattern; Aingaran [Column 10 Lines 55 - Column 11 Lines 15] offers superior pattern analysis and network reduction techniques for pattern type determination and simplification.
Aingaran teaches using the at least one connection point and the at least one actual connection line to form the respective wiring result topological structure corresponding to each signal to be tested in the set of signals to be tested; Aingaran [Column 10 Lines 55 - Column 11 Lines 15] teaches combining connection points with connection lines to form complete topological structures through network reduction methodology.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to improve actual wiring pattern analysis by incorporating Aingaran's pattern determination and simplification techniques with Araki's connection point extraction for enhanced topological structure formation.
In regards to claim 9 (Araki) does not show wiring quality test method according to claim 8: in response to determining that the actual wiring pattern is a rectangle, taking a perpendicular bisector of a short side of the rectangle in the actual wiring pattern as at least one actual connection line corresponding to the actual wiring pattern; in response to determining that the actual wiring pattern is a polygon, which represents that the actual wiring pattern and a layer via are connected at a layer via connection line, taking a perpendicular bisector of the layer via connection line in the actual wiring pattern as at least one actual connection line corresponding to the actual wiring pattern; wherein determining the type of each actual wiring pattern in the at least one actual wiring pattern, and simplifying each actual wiring pattern, to obtain the at least one actual connection line corresponding to the at least one actual wiring pattern comprises; determining that each actual wiring pattern is one of a rectangle, a path, and a polygon; in response to determining that the actual wiring pattern is a path, connecting center points in axial directions of the path in the actual wiring pattern to form at least one actual connection line corresponding to the actual wiring pattern; thereby obtaining the at least one actual connection line corresponding to the at least one actual wiring pattern;
Aingaran teaches wherein determining the type of each actual wiring pattern in the at least one actual wiring pattern, and simplifying each actual wiring pattern, to obtain the at least one actual connection line corresponding to the at least one actual wiring pattern comprises; Aingaran [Column 10 Lines 55 - Column 11 Lines 15] teaches pattern analysis and network reduction to obtain simplified connection structures.
Aingaran teaches in response to determining that the actual wiring pattern is a path, connecting center points in axial directions of the path in the actual wiring pattern to form at least one actual connection line corresponding to the actual wiring pattern; Aingaran [Column 13 Lines 20 - 40] teaches connecting center points during path analysis in layout traversal methodology.
Aingaran teaches thereby obtaining the at least one actual connection line corresponding to the at least one actual wiring pattern; Aingaran [Column 10 Lines 55 - Column 11 Lines 15] teaches obtaining simplified connection structures through comprehensive pattern analysis methodology.
Aingaran differs from the claimed invention in that it does not explicitly disclose determining that each actual wiring pattern is one of a rectangle, a path, and a polygon; in response to determining that the actual wiring pattern is a rectangle, taking a perpendicular bisector of a short side of the rectangle in the actual wiring pattern as at least one actual connection line corresponding to the actual wiring pattern; in response to determining that the actual wiring pattern is a polygon, which represents that the actual wiring pattern and a layer via are connected at a layer via connection line, taking a perpendicular bisector of the layer via connection line in the actual wiring pattern as at least one actual connection line corresponding to the actual wiring pattern;
McElvain teaches determining that each actual wiring pattern is one of a rectangle, a path, and a polygon; McElvain [0105] teaches analyzing net shapes including rectangular shapes with short sides and long sides for route topology determination.
McElvain teaches in response to determining that the actual wiring pattern is a rectangle, taking a perpendicular bisector of a short side of the rectangle in the actual wiring pattern as at least one actual connection line corresponding to the actual wiring pattern; McElvain [0105] teaches analyzing net shapes including rectangular shapes with short sides and long sides for route topology determination, thereby teaching geometric pattern analysis for rectangular wiring configurations.
McElvain teaches in response to determining that the actual wiring pattern is a polygon, which represents that the actual wiring pattern and a layer via are connected at a layer via connection line, taking a perpendicular bisector of the layer via connection line in the actual wiring pattern as at least one actual connection line corresponding to the actual wiring pattern; McElvain [0105] teaches analyzing net shapes and geometric configurations for route topology determination, thereby teaching polygon pattern analysis with connection line methodologies.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to enhance pattern recognition capabilities by integrating McElvain's shape analysis with Aingaran's pattern processing and Igarashi's geometric construction methods for comprehensive wiring pattern classification and simplification.
In regards to claim 10 (Araki) shows wiring quality test method according to claim 2:
wherein determining the at least one connection point corresponding to each signal to be tested based on the wiring layout and the wiring circuit diagram comprises; Araki [0046-0047] teaches extracting and investigating wiring segments and connection points from the layout.
determining the at least one connection point corresponding to each signal to be tested based on the at least one connection object in the wiring layout; Araki [0047] teaches investigating wiring configuration to specify connection points based on layout objects.
Araki differs from the claimed invention in that it does not explicitly disclose obtaining, in the wiring circuit diagram, at least one connection object label corresponding to each signal to be tested; matching, in the wiring layout, at least one connection object corresponding to the at least one connection object label;
McElvain teaches obtaining, in the wiring circuit diagram, at least one connection object label corresponding to each signal to be tested; McElvain [0040] teaches that gate-level logic elements are mapped to vendor specific primitives to generate a technology specific netlist with component identification.
McElvain teaches matching, in the wiring layout, at least one connection object corresponding to the at least one connection object label; McElvain [0040] teaches that mapped components are assigned to various blocks on the chip, thereby teaching object matching between diagram and layout.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to improve connection point determination accuracy by incorporating McElvain's object labeling and matching techniques with Araki's layout-based connection point extraction for enhanced circuit diagram integration.
In regards to claim 17 (Araki) shows the wiring quality test apparatus according to claim 16, wherein the processor is configured to:
determine the at least one connection point corresponding to each signal to be tested based on the wiring layout and the wiring circuit diagram; Araki [0046-0047] teaches extracting and investigating wiring segments and connection points from the layout.
determine the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested; Araki [0046] teaches extracting a segment A from a group comprising a plurality of minimum configuration units of wiring. Araki [0047] teaches investigating a wiring configuration of the segment A to specify connection points.
determine the respective wiring result topological structure corresponding to each signal to be tested in the set of signals to be tested from the wiring layout based on the at least one connection point corresponding to each signal to be tested; Araki [0047] teaches investigating wiring configuration to specify an edge of the plane nearest thereto based on connection point analysis. Araki [0046] teaches extracting actual wiring segments from the layout. Araki [0048] teaches determining actual distances from segments to plane edges for result structure analysis.
Araki differs from the claimed invention in that it does not explicitly disclose obtain a wiring circuit diagram corresponding to the wiring layout;
McElvain teaches obtain a wiring circuit diagram corresponding to the wiring layout; McElvain [0040] teaches that a logic synthesis tool creates a logic element network and generates a technology specific netlist. McElvain [0041] teaches that a placement and routing tool uses the design result of the synthesis tool for design layout.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to provide comprehensive apparatus-based wiring quality testing by integrating Araki's testing framework with Aingaran's topological analysis and McElvain's hierarchical processing capabilities for complete system implementation.
In regards to claim 18 (Araki modified by Aingaran) does not show the wiring quality test apparatus according to claim 17: wherein the at least one connection point comprises connection points of N levels, N being greater than or equal to 1; and the processor is configured to; in the wiring layout, take the at least one connection point corresponding to each signal to be tested as at least one first-level connection point; determine a first-level intermediate base line based on the at least one first-level connection point; determine connection points having an axial distance less than an ith-level preset threshold in (i-1)th-level connection points as ith-level connection points; determine an ith-level intermediate base line based on the ith-level connection points; wherein i is greater than or equal to 2 and less than or equal to N-1, the axial distance is a distance in a first axial direction or a second axial direction; the first axial direction is perpendicular to the second axial direction; continue to determine (i+1)th-level connection points and an (i+1)th-level intermediate base line until Nth-level connection points and an Nth-level intermediate base line are determined; determine an expected connection line of each level based on connection points of each level and an intermediate base line of each level in the connection points of N levels and intermediate base lines of N levels, thereby determining expected connection lines of N levels; use the at least one connection point and the expected connection lines of N levels to form the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested;
McElvain teaches wherein the at least one connection point comprises connection points of N levels, N being greater than or equal to 1; and the processor is configured to; McElvain [0068] teaches calculating the instance sensitivity at every instance in the design. McElvain [0070] teaches performing a backward breadth first traversal to compute the backward path sensitivity at instance I that has drive instances. McElvain [0071] teaches performing a forward breadth first traversal to compute the forward path sensitivity at instance I that has load instances.
McElvain teaches in the wiring layout, take the at least one connection point corresponding to each signal to be tested as at least one first-level connection point; McElvain [0105] teaches taking drive and load element positions for analysis, thereby teaching first-level connection point designation.
McElvain teaches determine a first-level intermediate base line based on the at least one first-level connection point; McElvain [0105] teaches determining net shape based on element positions, thereby teaching baseline determination.
McElvain teaches determine connection points having an axial distance less than an ith-level preset threshold in (i-1)th-level connection points as ith-level connection points; McElvain [0070] teaches performing backward breadth first traversal to compute backward path sensitivity at instance I that has drive instances, thereby teaching hierarchical distance-based connection point determination.
McElvain teaches determine an ith-level intermediate base line based on the ith-level connection points; McElvain [0105] teaches that the position of the drive element A and the positions of the load elements B, C and D determine the shape of the net, thereby teaching intermediate base line determination based on connection points.
McElvain teaches wherein i is greater than or equal to 2 and less than or equal to N-1, the axial distance is a distance in a first axial direction or a second axial direction; McElvain [0107] teaches that distance may be estimated as Manhattan distance plus twice the length of the short side of the bounding box, thereby teaching directional distance analysis with perpendicular axes.
McElvain teaches the first axial direction is perpendicular to the second axial direction; McElvain [0106] teaches that route includes detour in the direction of the short side for positioning analysis, thereby teaching directional analysis with perpendicular axial directions.
McElvain teaches continue to determine (i+1)th-level connection points and an (i+1)th-level intermediate base line until Nth-level connection points and an Nth-level intermediate base line are determined; McElvain [0071] teaches performing forward breadth first traversal to compute forward path sensitivity with iterative processing until completion.
McElvain teaches determine an expected connection line of each level based on connection points of each level and an intermediate base line of each level in the connection points of N levels and intermediate base lines of N levels, thereby determining expected connection lines of N levels; McElvain [0072] teaches determining the path sensitivity for instance I from the maximum of forward and backward path sensitivity calculations.
McElvain teaches use the at least one connection point and the expected connection lines of N levels to form the respective expected topological structure corresponding to each signal to be tested in the set of signals to be tested; McElvain [0072] teaches forming comprehensive path sensitivity analysis using multiple hierarchical levels for complete signal evaluation.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to provide comprehensive apparatus-based wiring quality testing by integrating Araki's testing framework with Aingaran's topological analysis and McElvain's hierarchical processing capabilities for complete system implementation.
In regards to claim 19 (Araki modified by Aingaran) does not show the wiring quality test apparatus according to claim 18, wherein the processor is configured to: determine an Nth-level expected connection line based on the Nth-level connection points and the Nth-level intermediate base line; determine a jth-level expected connection line based on jth-level connection points, a jth-level intermediate base line, and a (j+1)th -level expected connection line, wherein j is greater than or equal to 2 and less than or equal to N-1; continue to determine a (j-1)th-level expected connection line until a first-level expected connection line is determined, thereby determining the expected connection lines of N levels;
McElvain teaches determine an Nth-level expected connection line based on the Nth-level connection points and the Nth-level intermediate base line; McElvain [0072] teaches determining the path sensitivity for instance I from maximum forward and backward sensitivity calculations.
McElvain teaches determine a jth-level expected connection line based on jth-level connection points, a jth-level intermediate base line, and a (j+1)th -level expected connection line, wherein j is greater than or equal to 2 and less than or equal to N-1; McElvain [0070] teaches performing backward breadth first traversal with hierarchical processing where instances have drive relationships, thereby teaching level-based processing with defined ranges.
McElvain teaches continue to determine a (j-1)th-level expected connection line until a first-level expected connection line is determined, thereby determining the expected connection lines of N levels; McElvain [0070] teaches performing backward breadth first traversal to compute backward path sensitivity with iterative level-by-level processing until completion.
The motivation to combine Araki and Aingaran at the effective filing date of the invention is to enhance wiring quality assessment by integrating Araki's threshold-based testing methodology with Aingaran's topological structure analysis capabilities to provide comprehensive quality evaluation of circuit layouts.
The motivation to combine Araki, Aingaran, and Lin at the effective filing date of the invention is to enhance wiring quality testing accuracy by integrating threshold-based comparison methodologies with topological structure analysis for comprehensive layout verification and quality assessment.
The motivation to combine Araki, Aingaran, and McElvain at the effective filing date of the invention is to provide comprehensive apparatus-based wiring quality testing by integrating Araki's testing framework with Aingaran's topological analysis and McElvain's hierarchical processing capabilities for complete system implementation.
Response to Argument
Applicant's arguments filed on January 03, 2026 have been fully considered but they are not persuasive.
With respect to independent claims 1 and 16, Applicant argues that the claimed invention requires a "two-step comparison process" that is structurally distinct from the prior art, contending that Araki teaches only "single-step distance comparison" rather than the claimed intermediate "topological structure comparison result" followed by threshold evaluation. However, this argument fails because it applies an overly narrow interpretation of the prior art teachings and mischaracterizes the obviousness analysis.
Araki [0031] teaches computing minimum distance required and verifying whether measured distance meets requirements, which constitutes obtaining a comparison result. Lin [0031] and [0034] teach comparing calculated area ratios against threshold values after intermediate ratio calculations, explicitly demonstrating the claimed two-step methodology where intermediate comparison results are generated and subsequently compared to preset thresholds. It would be obvious to a person of ordinary skill in the art to combine Araki's wiring quality testing framework with Lin's threshold-based comparison methodology to enhance layout verification accuracy through staged analysis, thereby achieving the claimed two-step comparison process.
With respect to Applicant's argument that Lin teaches "area calculations" rather than "topological structure comparison," this argument is unpersuasive because it treats the references in isolation rather than considering their combined teachings as required under obviousness analysis. Aingaran [Column 13 Lines 20-40] teaches topological structure extraction and analysis, while Lin [0033-0034] teaches the claimed ratio calculation and threshold comparison methodology. The combination provides all elements of the claimed invention with the motivation being to improve wiring quality testing accuracy by integrating topological structure analysis with staged threshold comparison techniques.
Regarding Applicant's assertion that the combination of three references is improper, this argument fails because obviousness may be established by combining multiple prior art references when there is motivation to do so. The motivation to combine Araki, Aingaran, and Lin is to enhance wiring quality assessment accuracy by integrating complementary testing and analysis methodologies from the same field of electronic design automation.
With respect to dependent claims 2-19 and 21, these claims remain unpatentable for the same reasons as their respective independent claims from which they depend.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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