CTFR 17/936,861 CTFR 99353 DETAILED ACTION This action is in response to the filing 02/19/2026. Claims 1-25 are pending and have been fully examined. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Claims Claims 1-7, 14-15, 21-22, and 24-25 are rejected under 35 U.S.C. 103. Claims 8-13, 16-20, and 23 contain allowable subject matter but are objected to as being dependent upon a rejected base claim. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3, 6-7, 14-15, 22, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kou et al. (U.S. PGPub No. 20070283222) in view of Tewari et al. (U.S. PGPub No. 20050216920) . Regarding Claim 1 , and similarly Claim 24 , Kou teaches, An apparatus for configuring a processing device, the apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to: obtain, via the interface circuitry, information on a failure related to a component of the processing device, the failure having occurred at runtime of the processing device (an error-check module collects information related to the error (error type, operation causing the error) [0050]; where the system checks for an error during an operation ("runtime") [0063]; see the communication between control registers (302) and error check module (310) of Fig. 3 ("interface circuitry")) ; determine information on a microcode update to be applied to the processing device to remedy the failure related to the component (where if an error occurs during runtime, information on a system control setting update is acquired [0064] where the information is obtained from a database or look-up table accessible by microcode [0041]; the system's knowledge database (part no. 108 [0034], 200 [0041], and 304 [0047]) is a list of one or more errors and corresponding system control settings ("microcode updates") [0017]), … Kou does not appear to disclose and Tewari teaches, the microcode update implementing an alternative execution flow that emulates at least a portion of a functionality of the component (where the system comprises emulation code (114) that facilitates functionality and configuration of the allocated resources as the processing element [0028]; where emulation code (114) includes microcode associated with the allocated resources [0029]; where a device VM is used to emulate a hardware device as needed ("alternate" execution flow), including launching a new VM if devices cannot be allocated as needed [0030]) ; and configure the processing device to trigger a runtime remediation handler to apply the microcode update (where the device emulation code (114) ("handler") loads the microcode [0029]) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the error-prompted, microcode-based updating as taught by Kou to incorporate particularly launching an emulation of a hardware device using microcode as taught by Tewari. The resulting combination allows for emulated devices to provide enhanced security and isolation, in addition to removing complexity and improving modularity [Tewari; 0029]; further, the emulation of hardware devices may occur in response to an error of all devices not being allocated [Tewari; 0030], thus preventing further functionality issues. Regarding Claim 2 , Kou teaches, The apparatus according to claim 1, wherein the information on the failure related to the component comprise information on a circuit-level failure affecting the component (the failure includes circuit-level failing as demonstrated exemplary by "design defects… in less frequently used logic paths" [0060]) . Regarding Claim 3 , Kou teaches, The apparatus according to claim 1, wherein the information on the failure related to the component is based on a failure related to the component occurring in a field deployment of the processing device (a discovered error is found during the operation ("a field deployment") of the device [0049]) . Regarding Claim 6 , Kou teaches, The apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to determine the information on the microcode update to be applied to the processing device to remedy the failure related to the component based on a mapping between failures and … microcode updates (the system includes knowledge database (part no. 108 [0034], 200 [0041], and 304 [0047]) including a list of one or more errors and corresponding system control settings ("microcode updates") [0017]) . Kou does not appear to disclose and Tewari teaches, the alternative execution flows implemented by microcode updates (a device VM is used to emulate a hardware device as needed ("alternate" execution flow) [0030], where the emulation code (114) includes microcode [0029]) . The same motivation for Claim 1 also applies to Claim 6. Regarding Claim 7, Kou teaches, The apparatus according to claim 6, wherein the machine-readable instructions comprise instructions to update the mapping between the failures and the … microcode updates (the system may update knowledge database (304) with new error entries and corresponding recovery settings based on the error that provided resolution [0066]) . Kou does not appear to disclose and Tewari teaches, the alternative execution flows implemented by microcode updates (a device VM is used to emulate a hardware device as needed ("alternate" execution flow) [0030], where the emulation code (114) includes microcode [0029]) . The same motivation for Claims 1/6 also applies to Claim 7. Regarding Claim 14 , Kou does not appear to disclose and Tewari teaches, The apparatus according to claim 1, wherein the microcode update comprises instructions to emulate a functionality originally provided by the component (where the system comprises emulation code (114) that facilitates functionality and configuration of the allocated resources as the processing element [0028]; where emulation code (114) includes microcode associated with the allocated resources [0029]; where a device VM is used to emulate a hardware device as needed ("alternate" execution flow), including launching a new VM if devices cannot be allocated as needed [0030]) . The same motivation for Claim 1 also applies to Claim 14. Regarding Claim 15 , Kou does not appear to disclose and Tewari teaches, The apparatus according to claim 1, wherein the microcode update affects a shared use of one or more components of the processing device in simultaneous multithreading (where the system comprises emulation code that includes microcode and the system loads a device VM to emulate hardware resources as needed [0028- 0030]; upon launching the device VM emulating a hardware device, the monitor allocates shared resources, including shared memory buffers and methods [0031]; the system processors may be multi-threaded [0016]). The same motivation for Claim 1 also applies to Claim 15. Regarding Claim 22 , Kou teaches, A computer system comprising the apparatus according to claim 1 and the processing device (the apparatus may be a system [0008]) . Regarding Claim 25 , Kou teaches, A non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method of claim 24 (the method [0008] may be performed by executable code [0029]) . 07-21-aia AIA Claim s 4-5 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kou in view of Tewari, further in view of Shanbhogue et al. (U.S. PGPub No. 20160364308) . Regarding Claim 4 , Kou in view of Tewari do not appear to disclose and Shanbhogue teaches, The apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to obtain the information on the failure related to the component of the processing device from an in-field scan circuitry of the processing device (where in-field diagnostics are performed [0014] and information in the form of a failure status is obtained from a field [0120]) . It would have been obvious, to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kou in view of Tewari's error detection and remediation via microcode emulation to include in-field testing as disclosed by Shanbhogue. The resulting combination allows for improved processor self-testing in the form of minimizing unplanned downtime and improved manufacturing by quicker system failure debugging [Shanbhogue; 0014]. Regarding Claim 5 , Kou teaches, The apparatus according to claim 1, wherein the machine-readable instructions comprise instructions to obtain the information on the failure related to the component after an interrupt being raised (the system includes obtaining an indication of failure by an interrupt alerting an error-check module to collect information indicative of the error (error type, operation causing the error) [0050]) Kou in view of Tewari do not appear to disclose and Shanbhogue teaches, by an in-field scan circuitry of the processing device (where in-field diagnostics are performed [0014]) . It would have been obvious, to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kou's error detection and remediation via microcode emulation to include in-field testing as disclosed by Shanbhogue. The resulting combination allows for improved processor self-testing in the form of minimizing unplanned downtime and improved manufacturing by quicker system failure debugging [Shanbhogue; 0014]. Regarding Claim 21 , Kou in view of Tewari do not appear to disclose and Shanbhogue teaches, The apparatus according to claim 1, wherein the processing device is an XPU, the XPU being one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), an Artificial Intelligence (AI) accelerator, an accelerator card and offloading circuitry (the component may be a graphics core [0058] where the processing engine may further include accelerators [0071]) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the integrated circuit debugging mechanics as disclosed by Kou in view of Tewari to be specifically processing integrated circuits as disclosed by Shanbhogue [0098]. The resulting combination results in a testing mechanism resilient to the complexity of performing core tests [Shanbhogue; 0017-0018]. Allowable Subject Matter Claims 6-13, 16-20, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s statement of reasons for indicating allowable subject matter: Regarding Claim 8, Kou teaches, the knowledge database (108) may receive commands, instructions, and microcode updates from a user ("operator") [0039] . Tewari teaches a device VM is used to emulate a hardware device as needed ("alternate" execution flow) [0030], where the emulation code (114) includes microcode [0029] . The prior art of record does not disclose, without the use of impermissible hindsight reasoning, the operator-defined policy specifying which alternative execution flows are to be triggered by the runtime remediation handler for respective failures [emph. added] . Regarding Claim 9 , Kou teaches, where if an error occurs durring runtime, information on a system control setting update is acquired [0064] where the information is obtained from a database or look-up table accessable by microcode [0041]; the system then enacts the collected control system update ("to apply") [0064]. The prior art of record does not disclose, without the use of impermissible hindsight reasoning, the machine-readable instructions comprise instructions to obtain second information on a failure of a component of the processing device occurring in other computer systems , to determine information on a microcode update to be applied to the processing device to remedy the failure related to the component included in the second information [emph. added]. Claims 10-11 depend from the allowable subject matter of Claim 9. Regarding Claim 12 , Kou teaches the system control settings ("microcode update") may serve to set the frequency of the system clock [0042] and Tewari teaches a device VM is used to emulate a hardware device as needed ("alternate" execution flow) [0030], where the emulation code (114) includes microcode [0029] . However, without the use of impermissible hindsight reasoning, the prior art of record does not disclose that the microcode update implementing the alternative execution flow [itself] affects an operating frequency of the component of the processing device [emphasis and note added] . Regarding Claim 13 , Kou teaches the system control settings ("microcode update") controls the behavior of subsystems [0042] and Tewari teaches a device VM is used to emulate a hardware device as needed ("alternate" execution flow) [0030], where the emulation code (114) includes microcode [0029] . However, without the use of impermissible hindsight reasoning, the prior art of record does not disclose that the microcode update implementing the alternative execution flow [itself] affects a use of one or more components of the processing device for performing an instruction being exposed by an instruction set architecture of the processing device [emphasis and note added] . Regarding Claim 16 , the prior art of record does not disclose, without the use of impermissible hindsight reasoning, wherein the microcode update affects the instructions being exposed by an instruction set architecture of the processing device. Regarding Claim 17 , Tewari teaches where the system comprises emulation code that includes microcode and the system loads a device VM to emulate hardware devices as needed [0028-0030]; where "hardware device" include I/O processors [0007] . The prior art of record does not disclose, without the use of impermissible hindsight reasoning, wherein the microcode update [as dependent from Claim 1] relates to an input/output controller of the processing device, affecting the use of at least a part of an interface being coupled to the processing device [emphasis added where not taught in light of the microcode update emulating hardware functions as claimed in Claim 1] . Regarding Claim 18 , Kou teaches the system control settings ("microcode update") may serve to disable one or more dynamic memory access engines [0042]; the examiner notes therefore affecting at least a portion of memory . The prior art of record does not disclose, without the use of impermissible hindsight reasoning wherein the microcode update [as dependent from Claim 1] relates to a memory controller of the processing device, affecting the use of at least a portion of memory included in a computer system comprising the processing device [emphasis added where not taught in light of the microcode update emulating hardware functions as claimed in Claim 1] . Regarding Claim 19 , the prior art of record does not disclose, without impermissible hindsight reasoning, wherein the microcode update relates to a storage controller of the processing device, affecting the use of at least a portion of storage circuitry included in a computer system comprising the processing device . Regarding Claim 20 , the prior art of record does not explicitly disclose, without impermissible hindsight reasoning, wherein the microcode update is configured to disable the component. Regarding Claim 23 , Shanbhogue discloses in [0028] that the method may be implemented by firmware and Tewari discloses in [0008] that the method may be implemented by firmware. However, the prior art of record does not disclose, without impermissible hindsight reasoning, wherein the apparatus is implemented as part of a system firmware of the computer system [emphasis added]. Response to Arguments Applicant’s arguments filed 02/19/2026 have been fully considered. The Examiner acknowledges the amendments made to Claims 3 and 10-11, previously rejected under 35 U.S.C. 112(b) for lack of antecedent basis, and agrees that the amendments overcome the previous rejection. Accordingly the rejection under 35 U.S.C. 112 is withdrawn. Applicant’s arguments on p. 8-11 regarding the previous rejection under 35 U.S.C. 101 have been fully considered. While the Examiner finds that the claims are still directed to a judicial exception under Step 2A Prong 1 from the limitation, “determine information…” [Claim 1], the Examiner finds that the amended claims are eligible under Step 2A Prong 2. The practical application of implementing an alternative execution flow recites a tangible change to the computer system resulting in significantly more than the judicial exception in conjunction with the abstract idea of Claim 1. As claimed, the step of applying an alternative execution flow (“the microcode update implementing an alternative execution flow… configure the processing device […] to apply the microcode update ”) is a direct consequence of the abstract idea of performing a determination as recited in Claim 1, therefore, applying an alternative execution flow is beyond generally linked to the use of the judicial exception and justifies a meaningful limit on practicing the abstract idea. The above limitation integrates the judicial exception into a practical application. Therefore, under Prong 2, Claim 20 is patent-eligible under 35 U.S.C. 101 and the previous rejection has been withdrawn. Applicant’s arguments on p. 11-14 regarding the previous rejection under 35 U.S.C. 102 have been fully considered and are found to be persuasive. The Examiner agrees that Kou does not appear to disclose “a microcode update… implementing an alternative execution flow that emulates at least a portion of a functionality of the components” or “a runtime remediation handler.” The Examiner further agrees that Shanbhogue does not appear to cure this deficiency. The Examiner points to the newly-used reference, Tewari, as teaching these limitations. Please see the rejection to Claims 1 / 24 above. Accordingly the previous rejection under 35 U.S.C. 102 is withdrawn and the rejection is now made under 35 U.S.C. 103. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUDREY E WHITESELL whose telephone number is (703)756-4767. The examiner can normally be reached 8:30am - 5:00pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 5712723655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113 Application/Control Number: 17/936,861 Page 2 Art Unit: 2113 Application/Control Number: 17/936,861 Page 3 Art Unit: 2113 Application/Control Number: 17/936,861 Page 4 Art Unit: 2113 Application/Control Number: 17/936,861 Page 5 Art Unit: 2113 Application/Control Number: 17/936,861 Page 6 Art Unit: 2113 Application/Control Number: 17/936,861 Page 7 Art Unit: 2113 Application/Control Number: 17/936,861 Page 8 Art Unit: 2113 Application/Control Number: 17/936,861 Page 9 Art Unit: 2113 Application/Control Number: 17/936,861 Page 10 Art Unit: 2113
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