CTNF 17/937,229 CTNF 100557 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Action is non-final and is in response to the claims filed September 30 th , 2022. Claims 1-25 are pending, of which claims 1-25 are currently rejected. Specification The disclosure is objected to because of the following informalities: [0392] line 8 “channel 1 2955-1, channel 2 2955-2” should be “channel 0 2955-0, channel 1 2955-1”. [0394] line 3 “Matrix A 20902” should be “Matrix A 2902”. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites a high split value and a low split value, each of which has a sign bit, an exponent bit, and 10 mantissa bits totaling 12 bits. However, claim 4 upon which claim 5 depends, claims the split values i.e., second precision format having 19 bits (FP19). It is unclear whether the second precision format should have 19 bits as claimed in claim 4 or 12 bits as claimed in claim 5. Appropriate correction is required. For examination purposes, claim 5 will be construed to be dependent on claim 3 instead so that each of claim 4 and claim 5 are branching scenarios, so that the second precision could have either 19 bits or 12 bits. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-3, 6, 10-12, 15-17, 20-22, and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Meyer et al. (US 2023/0004523 A1) (hereinafter “Meyer”) . Regarding claim 1, Meyer teaches: A processor comprising: systolic array hardware including a plurality of data processing units (Fig. 3; ¶ 0020) , wherein the systolic array hardware is to: receive data for performance of a matrix multiplication operation in a first precision format (Abstract, receives inputs at a higher precision, systolic array may be used for matrix multiplication ¶ 0021) ; convert an original value of the data into two split values with a second precision format having a lower precision than the first precision format (to be split in a lower and higher value in a lower precision than the original precision ¶ 0028) ; perform the matrix multiplication operation using the two split values in the second precision format (matrix multiplication occurs using the two split values ¶ 0028), the matrix multiplication operation comprising a split-term operation that utilizes two passes through the systolic array hardware with feedback wiring and local reduction (¶ 0028 multiple passes i.e., at least two passes needed in order to be able to carry out multiplications using feedback wiring and local reduction of systolic array shown in Fig. 3; local reduction further discussed in ¶ 0032) ; and generate an emulated result for the matrix multiplication operation in the first precision format (¶ 0045 - ¶ 0046 output by final aggregator, final output having higher original precision; ¶ 0025 user may not be aware of lower bit precisions being used for intermediate operations) . Regarding claim 2, Meyer teaches: The processor of claim1, wherein the matrix multiplication operation comprises a single precision floating general matrix multiply (SGEMM) operation (¶ 0021 matrix multiplication operation carried out on systolic array; ¶ 0028 discusses single precision single pass computations being computed on the device, as well as reduced-precision multiple-pass computations being computed on the device to increase efficiency and reduce computational resources needed) . Regarding claim 3, Meyer teaches: The processor of claim 1, wherein the first precision format is 32-bit floating point (FP32) (¶ 0144 first input precision may be 32 bit FP32) . Regarding claim 6, Meyer teaches: The processor of claim 1, wherein the systolic array hardware comprises selection circuitry to select one of the two split values based on a pass of the two passes being performed during the matrix multiplication operation (¶ 0023 - ¶ 0024 selection between first and second reduced input; also discussed in ¶ 0312, ¶ 0041, ¶ 0141) . Regarding claim 10, Meyer teaches: The processor of claim 1, wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine (systolic array of Meyer is under control of one control unit to provide one instruction for multiple data inputs across the systolic array as shown in Fig. 3, machine is SIMD, additional discussion provided at ¶ 0130 and ¶ 0133) . Claims 11-12 and 15 recite the method practiced by the apparatus of claims 1-2 and 6 respectively and are therefore rejected for the same reasons therein. Claims 16-17 and 20 recite the system containing the apparatus of claims 1-2 and 6 respectively and are therefore rejected for the same reasons therein. Meyer additionally recites memory for storing data (¶ 0183) necessary for the system and a processor (¶ 0180 - ¶ 0181) for executing the operations for the system. Claims 21-22 and 25 recite the non-transitory computer-readable medium having instructions to be executed by one or more processors for the method practiced by the apparatus of claims 1-2 and 6 respectively and are therefore rejected for the same reasons therein. Additionally, Meyer teaches the non-transitory computer-readable medium at ¶ 0181 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 4, 9, 13, 18, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer in view of NVIDIA (“NVIDIA A100 Tensor Core GPU Architecture”, 2016) (hereinafter “NVIDIA”) . Regarding claim 4, while Meyer teaches the processor of claim 3, Meyer does not explicitly teach the second precision format being FP 19. However, NVIDIA teaches the second precision being a value with 19 bits to represent floating point values (Pg. 27 Fig. 9 TF32 is a floating point value being represented by 19 bits, having 1 sign bit, 8 exponent bits, and 10 mantissa bits). It would be obvious before the effective filing date to combine the second precision being FP19 as taught by NVIDIA with the processor as taught by Meyer as both teachings are directed towards multi-processor systems for matrix multiplication with conversion of datatypes. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help accelerate larger precision inputs by using smaller precision values instead, and would enable for faster processing (NVIDIA: Pg. 9 Section Introducing NVIDIA A100 Tensor Cores paragraph 4). Regarding claim 9, while Meyer teaches the processor of claim 1, Meyer does not explicitly teach the processor comprising a GPU. However, NVIDIA teaches the processor containing a GPU (or several if needed) having thereon Tensor Cores (NVIDIA: Pg. 9). In combining NVIDIA with Meyer, the entire processor of Meyer could be a GPU as taught by NVIDIA, with the various processing elements of the systolic array within being Tensor Cores for the various operations. It would be obvious before the effective filing date of the claimed invention to combine the GPU as taught by NVIDIA with the processor as taught by Meyer as both teachings are directed towards multi-processor systems for matrix multiplication with conversion of datatypes. One with ordinary skill in the art would be motivated to combine the teachings because doing so would increase scalability of computations as well as provide the increased needed resources for graphics processing capabilities (NVIDIA: Pg. 9). Regarding claim 13, while Meyer teaches the first input precision being FP32 (Meyer: (¶ 0144 first input precision may be 32 bit FP32), and reduced second precision being a non- standard format (Meyer: ¶ 0126), Meyer does not explicitly teach the reduced second precision being FP19. However, NVIDIA teaches the second precision being a value with 19 bits to represent floating point values (Pg. 27 Fig. 9 TF32 is a floating point value being represented by 19 bits, having 1 sign bit, 8 exponent bits, and 10 mantissa bits). The motivation to combine with respect to claim 4 applies equally to claim 13. Claim 18 teaches the system that practices the method of claim 4 and is therefore rejected for the same reasons therein. Claim 23 teaches the non-transitory computer-readable medium having thereon instructions to cause a processor to perform the method recited by claim 13 and is therefore rejected for the same reasons therein . 07-21-aia AIA Claim s 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer in view of Gerwig et al. (5999960) (hereinafter “Gerwig”) . Regarding claim 7, while Meyer teaches the processor of claim 1, Meyer does not explicitly teach having DPAS hardware comprising multipliers, block normalized adders (BNAs) and adder circuitry. However, Gerwig teaches floating point processing having a multiply and add section, while having block normalization occuring via shifters and adders for proper alignment and computation of floating point values (Gerwig: Col. 4 Lines 41-51 block normalization; Fig.6 shows internals of processor with block normalization adder ADD-A, adder circuitry ADD-M, and multiplier M). In combining Meyer and Gerwig, each of the processing elements of Meyer would house the DPAS hardware (Fig. 6 of Gerwig) having the multipliers, BNAs, and adder circuitry. It would be obvious before the effective filing date of the claimed invention to combine the DPAS hardware as taught by Gerwig with the processor as taught by Meyer as both teachings are directed towards floating point computations for multiply-add operations. One with ordinary skill in the art would be motivated to combine the teachings because this would allow much faster normalization computations (Gerwig: Col. 4 Lines 41-51). Regarding claim 8, Meyer in view of Gerwig further teaches: The processor of claim 7, wherein the adder circuitry comprises at least one extra bit to avoid overflow in a second pass of the two passes through the systolic array hardware (Meyer: ¶ 0119 extra bits provided to prevent overflow in adder) . 07-21-aia AIA Claim s 5, 14, 19, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer in view of NVIDIA further in view of Lin (US 2023/0342419 A1) (hereinafter “Lin”) . Regarding claim 5, while Meyer teaches rounding down to zero and rounding a reduced second precision value (Meyer: ¶ 0096) and rounding off bits during the rounding process (¶ 0097), as well as splitting of weights into a high and low value (¶ 0028), Meyer does not explicitly teach these split values being rounded to 1 sign bit, 1 exponent bit, and 10 mantissa bits. However, Lin teaches dividing FP32 values into FP16 values having 1 sign bit, 5 exponent bits (including the one exponent bit), and 10 mantissa bits (Lin: ¶ 0124). It would be obvious to combine before the effective filing date of the claimed invention the splitting as taught by Lin with the processor as taught by Meyer in view of NVIDIA because all teachings are directed towards matrix multiplication using floating point values. One with ordinary skill in the art would be motivated to combine the teachings because this would improve calculation efficiency of the matrix (Lin: ¶ 0005). Claim 14 recites the method practiced by the apparatus of claims 1-2 and 6 respectively and are therefore rejected for the same reasons therein. Claim 19 recites the system containing the apparatus of claims 1-2 and 6 respectively and are therefore rejected for the same reasons therein. Meyer additionally recites memory for storing data (¶ 0183) necessary for the system and a processor (¶ 0180 - ¶ 0181) for executing the operations for the system. Claim 24 recites the non-transitory computer-readable medium having instructions to be executed by one or more processors for the method practiced by the apparatus of claims 1-2 and 6 respectively and are therefore rejected for the same reasons therein. Additionally, Meyer teaches the non-transitory computer-readable medium at ¶ 0181. Prior Art Made of Record 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pisha et al. (US 12475189) teaches matrix multiply accumulate circuitry for performing mathematical operations in portions using a first or second circuits for computations of floating point values . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.D.R./Examiner, Art Unit 2151 /James Trujillo/Supervisory Patent Examiner, Art Unit 2151 Application/Control Number: 17/937,229 Page 2 Art Unit: 2151 Application/Control Number: 17/937,229 Page 3 Art Unit: 2151 Application/Control Number: 17/937,229 Page 4 Art Unit: 2151 Application/Control Number: 17/937,229 Page 5 Art Unit: 2151 Application/Control Number: 17/937,229 Page 6 Art Unit: 2151 Application/Control Number: 17/937,229 Page 7 Art Unit: 2151 Application/Control Number: 17/937,229 Page 8 Art Unit: 2151 Application/Control Number: 17/937,229 Page 9 Art Unit: 2151 Application/Control Number: 17/937,229 Page 10 Art Unit: 2151
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