CTNF 17/937,248 CTNF 82548 DETAILED ACTION 1. Claims 1-25 are pending in the application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA 4. Claim(s) 1-25 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Shrivastava (US Pub. 2020/0311535) . 5. As to claim 1, Shrivastava discloses a computing system comprising: a memory array ([0065] arrays for analog memory); and an accelerator coupled to the memory array, the accelerator including: a multiply-accumulate (MAC) computation stage (fig. 5a and [0049], MACs), an analog amplifier stage coupled to an output of the MAC computation stage ([0007]-[0008] and [0052] amplifier circuit), and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage is to modify a quantization granularity of the ADC stage ([0043]-[0045] ADC). 6. As to claims 2, 10, and 19, Shrivastava discloses wherein the accelerator further includes an exponent quantizer stage coupled to the analog amplifier stage and the output of the MAC computation stage, wherein the exponent quantizer stage is to adjust the gain setting based on one or more operating parameters ([0044]). 7. As to claims 3, 11, and 20, Shrivastava discloses wherein the one or more operating parameters include a size of an activation value at the output of the MAC computation stage ([0040]). 8. As to claims 4, 12, and 21, Shrivastava discloses wherein the exponent quantizer stage is to: set the gain setting to a first level if the size of the activation value exceeds a threshold; and set the gain setting to a second level if the size of the activation value does not exceed the threshold, wherein the second level is greater than the first level ([0033]-[0034]). 9. As to claims 5, 13, and 22, Shrivastava discloses the one or more operating parameters include a type of neural network layer associated with the MAC computation stage ([0004] neural network). 10. As to claims 6, 14, and 23, Shrivastava discloses wherein the accelerator further includes a combination stage coupled to an output of the exponent quantizer stage and an output of the ADC stage, and wherein the combination stage is to combine the output of the exponent quantizer stage and the output of the ADC stage ([0007] and [0033]). 11. As to claims 7, 15 and 24, Shrivastava discloses wherein the gain setting is fixed ([0036]-[0038]). 12. As to claims 8 16, 17, and 25, Shrivastava discloses wherein the output of the MAC computation stage is to include one or more of single-ended activation values or differential activation values ([0040]). 13. As to claims 9 and 18, the claims are rejected for similar reasons as claim 1 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL D. YAARY/Primary Examiner, Art Unit 2151 Application/Control Number: 17/937,248 Page 2 Art Unit: 2151 Application/Control Number: 17/937,248 Page 3 Art Unit: 2151
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