Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-14 in the reply filed on 12/05/2025 is acknowledged.
Information Disclosure Statement
The references listed in the Information Disclosure Statement (IDS) filed on 10/03/2022 have been considered by the examiner (see attached PTO-1449 or PTO/SB/08A and 08B forms). Accordingly, claims 15-20 are withdrawn.
DRAWINGS
The Drawings filed on 10/03/2022 have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation, “The semiconductor device of claim 1, wherein the trench is disposed at a bottom of the cavity and extends from the cavity via a through hole”, as recited in claim 13, is unclear because the arrangement in claim 13 appears to contradict the arrangement recited in the parent (claim 1).
In addition, claim 14 suffers similar limitation as pointed it out in claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobvi0usness.
Claim(s) 1-2, 4, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dubey et al. (US 11,791,274 B2) in view of Goh et al. (US 12,341,121 B2).
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Regarding claim 1, Dubey teaches “A semiconductor device comprising;
a substrate (102 and 104 in combination; see Fig. 10) comprising a cavity (120); and
a first chip (130-1) and a second chip (130-2) (see Fig. 9) on the substrate;
a bridge chip (110) interconnecting the first and second chips and residing in the cavity; and
an underfill material (144, see Fig. 10) filling the cavity and surrounding the bridge chip. Dubey does not explicitly teach comprising a trench extended from the cavity.
Goh teaches in Fig. 6, (see col. 7, line 66 to col. 8, line 16) “a semiconductor device comprising; a substrate (110) comprising a cavity (190) and a trench (134) extended from the cavity. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a deep trench, accommodating the encapsulant and separating or partially separating the substrate into two distinct halves, in order to allow for thermal expansion of the two halves of the
substrates.
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Regarding claim 2, Dubey does not explicitly teach including ‘trench’ “wherein the trench is dimensioned as an ingress channel to provide a path for the underfill material to fill the cavity from a first side of the cavity”. However, this above limitation is met by Goh’s teachings in Fig. 6, col. 7, line 33-34, and col. 8, lines 12-16., for the same motivation as discussed above in the rejection of claim 1.
Regarding claim 4, Dubey does not explicitly teach including ‘trench’, “wherein the trench is dimensioned as an outflow channel to provide a path for air to leave the cavity from a second side of the cavity”. However, Goh teaches in Fig. 6, the trench/opening (134) located in a position for the underfill (132) to flow to provide a path for air to leave the cavity from a second side of the cavity, it is inherent in the design illustrated in Fig. 6, for the same motivation as discussed above in the rejection of
claim 1.
Regarding claim 12, the limitation, “The semiconductor device of claim 1, wherein the semiconductor device is a direct bonded heterogeneous integration package”, it is inherent in the design illustrated in Fig 10.
The prior art(s) of record fail to further teach and/or suggest::
“The semiconductor device of claim 2, wherein a depth of the trench is equal to a depth of the cavity”, as claimed in claim 3.
“The semiconductor device of claim 4, wherein a depth of the trench is at least half of a depth of the cavity”, as claimed in claim 5.
“The semiconductor device of claim 1, wherein a depth of the trench is a factor of C4 stand-off height, cavity size, or material viscosity”, as claimed in claim 6.
“The semiconductor device of claim 1, further comprising additional one or more trenches, wherein the trench and the additional one or more trenches form a plurality of trenches.”, as claimed in claim 7 (and dependent claims 8-10).
“The semiconductor device of claim 1, wherein a width of the trench is larger than 0.2mm”, as claimed in claim 11.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASMINE J CLARK whose telephone number is (571)272-1726. The examiner can normally be reached 8:30-5.30.
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/JASMINE J CLARK/Primary Examiner, Art Unit 2899