Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/14/2026 has been entered.
Specification
The disclosure is objected to because of the following informalities: Applicant’s Specification as filed, at paragraph [0039] of the published Application, contains the statement “Step (ii) of unloading the state of NOC element (105, 107) is performed using another second layer of configuration and debug NOC (D0, D1, D2, D3, D4, D5, D6, D7) that is independent of the existing first layer of NOC topology (101) as shown in Error! Reference source not found.”. The Specification should be amended to include the reference source that was intended by the Error phrase.
Appropriate correction is required.
Election by Original Presentation
Amended Claims 2, 6, and 10 are directed to a patentably distinct species from the originally claimed species:
Species I. Claims 1, 4, 5, 7-9, and 11-12, drawn to a method of debugging a network-on-chip based on a broadcast freeze, corresponding to the first embodiment of the invention (see paragraphs [0034]-[0035] of the publication of the instant Application, US. Pub. No. 2024/0070039), classified in G06F15/7825.
Species II. Claims 2, 6, and 10, drawn to a method of debugging a network-on-chip based on a targeted freeze, corresponding to the second embodiment of the invention (see paragraphs [0041]-[0043] of the publication of the instant Application, US. Pub. No. 2024/0070039), classified in G06F15/7807.
The species are independent or distinct from each other because they are mutually exclusive. In the instant case, the Species II includes a separate mechanism, i.e., debugging the NOC by triggering a targeted freeze, which is not performed in the Species I, which triggers a broadcast freeze to the entire NOC. See MPEP § 806.05(d). In addition, the species are not obvious variants of each other based on the current record.
Restriction for examination purposes as indicated is proper because all the species listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
Species I would be searched in at least CPC G06F15/7825, along with a unique text search. Species II would not be searched as above, and would instead require a search in at least CPC G06F15/7807, along with a unique text search.
Since Applicant has received an action on the merits for the originally presented Species I, this Species has been constructively elected by original presentation for prosecution on the merits. Accordingly, Species II (Claims 2, 6, and 10) is withdrawn from consideration as being directed to a non-elected species. See 37 CFR 1.142(b) and MPEP 821.03.
Claim Objections
The objections to claims 1 and 11 are withdrawn based on the amendment filed on 1/14/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 7 and 9, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (U.S. Pat. No. 6389557, hereinafter “Yu”) in view of Guo et al (U.S. Pub. No. 2013/0051397, hereinafter “Guo”).
Regarding independent Claim 1, Yu teaches a method of debugging a networking chip (column 2, lines 50-56, single-chip Ethernet controller), comprising: i. triggering said chip to enter into a freeze state where forward progress is prevented (column 4, lines 52-56, freeze; column 5, lines 9-15, debug mode); ii. at least one management unit unloading debug information of said chip (column 4, lines 52-56, internal registers can be examined; column 5, lines 9-15, debug mode; column 4, lines 36-47, logic analyzer); iii. triggering said chip to enter into an unfreeze state to allow forward progress to resume (Fig. 3, normal mode is resumed after debug mode, column 5, lines 17-64), wherein (i) is performed by at least one internal logic gating at least one clock causing an ingress link to stop sending data while said at least one internal logic gating said at least one clock causing a local egress link to stop accepting data (column 4, lines 52-56, clock control circuit freezes the network interface, which would stop sending of anything to any links or accepting of anything into any buffer, e.g., receive buffer 18a or transmit buffer 18b of Fig. 1).
Yu does not specifically teach that the networking chip is a network-on-chip (NOC), that the management unit is a NOC management unit, and that that the ingress link to stops sending data comprising at least one credit to an egress link of an adjacent NOC element, and the local egress link stops accepting data comprising new flits into a buffer associated with said local egress link, wherein said at least one internal logic comprises First in, First out (FIFO) storage in at least one predetermined NOC element in said NOC. However, Guo teaches in paragraph [0004] that a NoC, which would include a management unit, is a type of chip that is used for routing (i.e., a networking chip). Further, Guo teaches in paragraph [0004] that a NoC buffers incoming and outgoing flits using credit generation and tracking (i.e., the internal logic comprises buffers that hold flits and that would be located in NOC elements); it is noted that applying the freeze such as is taught in Yu would stop credits and flits in the NOC of Guo, and that the NOC stores flits on a FIFO basis in paragraphs [0057] and [0077]. It would have been obvious to one skilled in the art at the effective filing date of the invention to include an NoC that implements flits and credits such as is taught in Guo as the networking chip in the debugging system of Yu, in order to ensure that data is correctly routed from a source location to an intended destination location (see Guo, paragraph [0003]), and to identify subtle errors that can degrade performance of a communication device (see Yu, column 1, lines 9-22).
Regarding Claim 4, Yu in view of Guo teaches everything that is claimed above with respect to Claim 1. Yu further teaches wherein (i) is triggered by at least one internal mechanism, whereby said trigger is generated internally by any element in said networking chip that meets at least one trigger condition set by said at least one management unit (column 4, lines 52-56, freeze is triggered by user, which causes BYPASS MODE to cause entry into debug mode, which is equated to claimed trigger that is generated internally by an element, see column 5, lines 9-15); wherein said freezing is triggered to a predetermined element, before freezing is triggered to all elements in said networking chip (column 5, lines 36-48, signal B, which stops the internal clock and is equated to triggering a freeze to a predetermined element, goes high a clock cycle before STOP signal, which is equated to triggering a freeze to all elements).
Yu does not specifically teach that the networking chip is a NOC. However, Guo teaches in paragraph [0004] that a NoC is a type of chip that is used for routing (i.e., a networking chip). It would have been obvious to one skilled in the art at the effective filing date of the invention include an NoC such as is taught in Guo as the networking chip in the debugging system of Yu, in order to ensure that data is correctly routed from a source location to an intended destination location (see Guo, paragraph [0003]), and to identify subtle errors that can degrade performance of a communication device (see Yu, column 1, lines 9-22).
Regarding Claim 5, Yu in view of Guo teaches everything that is claimed above with respect to Claim 1. Yu further teaches wherein (i) is triggered by at least one external mechanism outside of said networking chip, whereby freezing is triggered by said at least one management unit to a predetermined element (no patentable weight due to “or”), or to all elements in said networking chip (column 4, lines 52-56, user freezes entire network interface via clock control circuit).
Yu does not specifically teach that the networking chip is a NOC. However, Guo teaches in paragraph [0004] that a NoC is a type of chip that is used for routing (i.e., a networking chip). It would have been obvious to one skilled in the art at the effective filing date of the invention to include an NoC such as is taught in Guo as the networking chip in the debugging system of Yu, in order to ensure that data is correctly routed from a source location to an intended destination location (see Guo, paragraph [0003]), and to identify subtle errors that can degrade performance of a communication device (see Yu, column 1, lines 9-22).
Regarding Claim 7, Yu teaches everything that is claimed above with respect to Claim 1. Yu further teaches wherein (ii) comprises: (a) upon ensuring all links within said networking chip are in idle state, selecting target elements (column 4, lines 52-56, freeze would ensure links are idle, and internal registers to be examiner are equated to claimed selected target element); (d) unloading said debug information; wherein (a), (b), (c) and (d) are repeated until a predetermined amount of debug information is unloaded from said elements within the networking chip (column 4, lines 52-56, data from registers is unloaded; this is equated to the predetermined amount of information, such that the substeps would not be repeated after data from registers is unloaded; it is noted that the claim does not specify that the debug information is specific to the selections).
Yu does not teach that the networking chip is a NOC; (b) selecting a channel, a virtual channel or combination thereof; and (c) selecting a link and a link direction. However, Guo teaches in paragraph [0004] a NoC is a type of chip that is used for routing (i.e., a networking chip), and that the NOC includes inter-router physical links (which would be incoming and outgoing), and virtual channels associated with each input port; any data corresponding to the NoC (such as debugging data, which is taught in Yu) would be associated with particular links and channels through which data is routed by the NoC. It would have been obvious to one skilled in the art at the effective filing date of the invention to include an NoC including links and channels such as is taught in Guo as the networking chip in the debugging system of Yu, in order to ensure that data is correctly routed from a source location to an intended destination location (see Guo, paragraph [0003]), and to identify subtle errors that can degrade performance of a communication device (see Yu, column 1, lines 9-22).
Regarding Claim 9, Yu in view of Guo teaches everything that is claimed above with respect to Claim 1. Yu further teaches (iii) is performed by at said least one internal logic ungating said at least one clock causing an ingress link to resume a return of data to the adjacent egress link while said at least one internal logic ungating said at least one clock causing the local egress link to resume accepting data into said local egress link's buffer (Fig. 3, normal mode is resumed after debug mode, column 5, lines 17-64, so that buffers 18a and 18b of Fig. 1 would resume accepting data).
Yu does not specifically teach that the ingress link resumes the return data comprising of at least one outstanding credit to adjacent egress link, and the egress link resumes accepting data comprising new flits into said egress link's buffer. However, Guo teaches in paragraph [0004] that a NoC buffers incoming and outgoing flits using credit generation and tracking during normal operation. It would have been obvious to one skilled in the art at the effective filing date of the invention include an NoC that implements flits and credits such as is taught in Guo as the networking chip in the debugging system of Yu, in order to ensure that data is correctly routed from a source location to an intended destination location (see Guo, paragraph [0003]), and to identify subtle errors that can degrade performance of a communication device (see Yu, column 1, lines 9-22).
Regarding Claim 11, Yu in view of Guo teaches everything that is claimed above with respect to Claim 1. Yu does not specifically teach wherein said debug information is a state of at least one element; wherein said state of said at least one element comprises ingress and egress buffer contents comprising route information or flit; read and write pointers of said buffer (no patentable weight due to “or”); ingress link requestors within said at least one NOC elements (no patentable weight due to “or”); or combination thereof (no patentable weight due to “or”). However, Yu does teach reading out of debug information (column 4, lines 52-56), and that the networking chip 10 includes transmit and receive buffers 18a-b that hold data (equated to the ingress and egress buffer contents). Further, Guo teaches in paragraph [0004] that a NoC acts as a router and includes data including routing information that is stored in buffers (no patentable weight for “flit” due to “or”). It would have been obvious to one skilled in the art at the effective filing date of the invention include an NoC including routing information from buffers such as is taught in Guo as the networking chip in the debugging system of Yu, in order to ensure that data is correctly routed from a source location to an intended destination location (see Guo, paragraph [0003]), and to identify subtle errors that can degrade performance of a communication device (see Yu, column 1, lines 9-22).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Guo and Ouyang (CN-105656773-A).
Regarding Claim 8, Yu in view of Guo teaches everything that is claimed above with respect to Claim 1. Yu does not specifically teach wherein said method further comprises swapping a content of a particular chosen flit to alter a routing path for debug purpose, after (i). However, Ouyang teaches in on page 4, in the 2nd to 4th full paragraphs, modifying a flit to re-route the flit in response to a fault (see also page 7, 5th and 6th paragraphs; page 8, last full paragraph; and page 9, claim 3). It would have been obvious to one skilled in the art before the effective filing date of the invention to include the flit modification of Ouyang in the system of Yu and Guo, in order to handle faults in the NoC (see Ouyang, Background Technology section, pages 2 and 3).
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
Poplingher, Britton, Muscavage, Bellippady, Selwan, Hong, Lee, and Schadt, “Method and Apparatus for freeze and readout during debug of elastic buffers” (December 26, 2013) teaches freezing a NoC for debug, and reading out buffer contents during the freeze.
Kim et al (U.S. Pub. No. 2008/0005402) teaches FIFO buffers in a NoC (Abstract).
Maruccia et al (U.S. Pub. No. 2008/0320161) teaches FIFO memory in a NoC (paragraphs [0053]-[0054]).
Tokuoka (U.S. Pub. No. 2012/0099475) teaches FIFOs in a NoC (paragraphs [0076]-[0077]).
Response to Arguments
Applicant's arguments filed 1/14/2026 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues on pages 5-6 that Yu does not teach “at least one internal logic gating at least one clock causing an ingress link to stop sending at least one credit….while….causing a local egress link to stop accepting new flits”. It is noted that Yu is not cited as teaching credits and flits. Further, Yu teaches freezing a chip for the purposes of debugging, which would stop all sending and accepting of data (e.g., the credits and flits taught in Guo). Yu further teaches internal logic (which is a very broad term), and a clock circuit (see the rejection of Claim 1, above).
Applicant goes on to argue on pages 6-7 that Guo does not teach FIFO structures being used to manage debug-triggered clock gating at the link level, and “said internal logic comprises First In, First Out (FIFO) storage”. It is noted that Claim 1 does not recite how the FIFO storage is used, but merely states that an “internal logic” of the NOC comprises FIFO storage. It is noted that “internal logic”, as is recited in Claim 1, is very broad, and may include any number and combination of chip elements. Further, Guo explicitly teaches FIFO storage in a NoC (see the updated rejection of Claim 1, above), and it appears that FIFO storage is commonly used in NoCs (see, e.g., the Kim, Maruccia, and Tokuoka references cited in the prior art of record section, above).
Applicant goes on to argue on pages 7 that the combination of Yu and Guo glosses over the architectural and operational differences between a centralized ethernet controller and a distributed NOC. It is noted these architectural and operational differences are not reflected in Applicant’s claims, and that the Examiner is merely applying the prior art according to the broadest reasonable interpretation of Applicant’s claim language.
In response to Applicant's argument on page 7 that the examiner's conclusion of obviousness cannot be derived from the cited references without hindsight, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Regarding Claim 2, it is noted that amended Claim 2, and dependent Claims 6 and 10, are withdrawn from consideration due to election by original presentation as being directed to a different species from the originally claimed species (the previously presented Claim 2 was not patentably distinct from Claim 1).
Regarding Claim 8, new grounds of rejection based on Applicant’s amendments are provided above based on the Ouyang reference.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (i.e., Claim 4).
Regarding dependent Claim 12, the Claim features “wherein the at least one trigger condition is selected by the NOC management unit from a configurable set of trigger conditions including a timeout count value and a match of a predefined flit pattern, and wherein the freeze state is triggered when the selected trigger condition or a combination of selected trigger conditions is satisfied” were not found in the prior art. It is noted that, as argued by Applicant on pages 10-11 of the Remarks filed on 1/14/2026, amended Claim 12 requires that the NoC management unit itself include a configurable set of trigger conditions including both a timeout count value and a match of a predefined flit pattern, and that at least one trigger condition is selected by the NoC management unit from the configurable set of trigger conditions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA L DAVIS whose telephone number is (571)272-1599. The examiner can normally be reached Monday-Friday, 7am to 3pm.
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/CYNTHIA L DAVIS/Examiner, Art Unit 2857
/SHELBY A TURNER/Supervisory Patent Examiner, Art Unit 2857