DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 13 February 2026 is acknowledged. Claims 10-12 have been canceled. Claims 1, 9, 13, 14, 21, and 31 have been amended. Claims 32-34 have been added. Claims 1, 6-9, 13-21, and 31-34 are pending.
Claim Objections
Claim 33 is objected to because of the following informalities:
Claim 33 recites the limitation, “wherein the 2D semiconductor material comprises MoS2, MoSe2, WS2, WSe2, InSe, GaTe, or_black phosphorus (BP).” This appears to contain a typographical error and may be corrected as, “wherein the 2D semiconductor material comprises MoS2, MoSe2, WS2, WSe2, InSe, GaTe, or[[_]] black phosphorus (BP).”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 31, 33, and 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 31 recites the limitation, “the sub-stoichiometric S:Mo ratio.” There is insufficient antecedent basis for this limitation in the claim.
Claim 33 recites the limitation, “wherein the 2D semiconductor material comprises MoS2, MoSe2, WS2, WSe2, InSe, GaTe, or_black phosphorus (BP).” The claim does not invoke Markush language and the transitional phrase “comprising” is inclusive. Because the grouping recited in the claim is an open list of numerous alternatives and combinations of alternatives, it unclear as to what material or combination of materials may make up the 2D semiconductor material. See MPEP 2111.03, 2117, and 2173.05(h).
Claim 34 recites the limitation, “wherein the 2D semiconductor material comprises MoS2.” It is unclear how the 2D semiconductor material may comprise MoS2 if said 2D semiconductor material is selected from one of the alternative materials or combination of materials recited in claim 33 from which the claim depends. It is noted that claim 33 does not invoke Markush language when reciting its list of alternative materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 17-19, 32, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Hersam et al. (US Patent Application Publication 2016/0248007, hereinafter Hersam ‘007) in view of Iezzi et al. (US Patent Application Publication 2014/0353166, hereinafter Iezzi ‘166), both of record.
With respect to claim 1, Hersam ‘007 teaches (FIGs. 1A-1C) a memtransistor substantially as claimed, comprising:
a polycrystalline monolayer film (120; the MoS2 monolayer film is described as being polycrystalline in para. [0102, 0105, 0120]) of an atomically thin material ([0076]);
a gate electrode (140) defined on a second substrate (110 and 140) ([0076]); and
source and drain electrodes (131 and 132) spatially-apart formed on the polycrystalline monolayer film (120) to define a channel region (125) in the polycrystalline monolayer film therebetween ([0076]), and
wherein the gate electrode (140) is capacitively coupled (by dielectric 110) with the channel region (125) ([0076]).
Thus, Hersam ‘007 is shown to teach all the features of the claim with the exception of:
wherein the polycrystalline monolayer film is characterized by a reduced density of lattice defects and a specific crystallographic registry resulting from being grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride, and
wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses.
However, Iezzi ‘166 teaches growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]). Such a process would result in a polycrystalline monolayer film characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses as claimed.
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the polycrystalline monolayer film of MoS2 of Hersam ‘007 and Iezzi ‘166 would inherently have the property of characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, quartz, graphene, or hexagonal boron nitride and transferred onto a second substrate of SiO2/Si or of a high-k dielectric layer including Al2O3 or HfO2, which are the same materials and processes as disclosed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the polycrystalline monolayer film of Hersam ‘007 grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride resulting in said polycrystalline monolayer film being characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses as taught by Iezzi ‘166 to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity and because these properties are presumed to be inherent.
The expression “grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride,” is taken to be a product-by-process limitation and is given limited patentable weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
With respect to claim 6, Hersam ‘007 teaches wherein the second substrate (110 and 140) is an SiO2/Si substrate, or a substrate of a high-k dielectric layer including Al2O3 or HfO2 ([0088]).
With respect to claim 7, Hersam ‘007 teaches wherein the SiO2/Si substrate comprises a silicon substrate with a silicon dioxide overlayer ([0088]).
With respect to claim 8, Hersam ‘007 teaches wherein the gate (140), source (131) and drain (132) electrodes comprises a same conductive material or different conductive materials ([0088]).
With respect to claim 17, Hersam ‘007 in view of Iezzi ‘166 teach (FIGs. 1A-1C) a circuit as claimed, comprising one or more memtransistors according to claim 1 (see the rejection of claim 1 above).
With respect to claim 18, Hersam ‘007 in view of Iezzi ‘166 teach (FIGs. 1A-1C) an electronic device as claimed, comprising one or more memtransistors according to claim 1 (see the rejection of claim 1 above).
With respect to claim 19, Hersam ‘007 in view of Iezzi ‘166 teach (FIGs. 1A-1C) a system for continuous learning in a spiking neural network as claimed, comprising:
one or more synaptic units (110, 120, 125, 131, 132, and 140), wherein each synaptic unit comprises one or more memtransistors according to claim 1 (see the rejection of claim 1 above).
With respect to claim 32, Hersam ‘007 teaches wherein the atomically thin material (the polycrystalline MoS2 monolayer film) comprises two-dimensional (2D) semiconductor material ([0088]).
With respect to claim 33, Hersam ‘007 teaches wherein the 2D semiconductor material comprises MoS2, MoSe2, WS2, WSe2, InSe, GaTe, or_black phosphorus (BP) ([0088]).
Claims 9, 13-16, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hersam ‘007 and Iezzi ‘166 as applied to claims 1 and 19 above, and further in view of Tang et al. (US Patent Application Publication 2012/0011092, hereinafter Tang ‘092) of record.
With respect to claims 9, 13-16, 20, and 21, Hersam ‘007 and Iezzi ‘166 teach the devices as described in claims 1 and 19 above, but primary reference Hersam ‘007 does not explicitly teach the additional limitations being reconfigurable with gate tunability that enables continuous learning that allows selective forgetting of tasks, thereby freeing up neural resources to learn new tasks; wherein additional learning behaviors are achieved by varying temporal evolution of gate bias pulses; wherein gate pulses are used to modulate potentiation and depression, resulting in learning curves and simplified spike-timing-dependent plasticity that facilitate unsupervised learning in a simulated spiking neural network (SNN); wherein a library of learning curves obtained from temporal evolution of a pulsing amplitude is used to perform unsupervised image recognition in the SNN with functions of continuous learning; wherein the unsupervised learning in the SNN is performed using an experimental memtransistor learning behavior modelled in a simplified spike-timing-dependent plasticity (STDP) scheme; wherein each synaptic unit has learning and/or unlearning behaviors with gate-tunable characteristics of the memtransistors; and wherein switching LTP-LTD learning behavior is achieved by only reversing a polarity of gate pulses, while further adjustments in a gate amplitude produce learning curves and thus learning behaviors.
However, Iezzi ‘166 teaches a bottom-gate memtransistor formed by growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]).
Further, Tang ‘092 teaches memristive devices used for designing neural systems having machine learning properties ([0037[).
Still further, the limitations of claims 9-16, 20, and 21 merely recite functional language and intended use. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, transferred onto a second substrate of SiO2/Si, and formed as the memtransistor as disclosed, the device is presumed capable of performing the functions and intended uses as claimed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the memtransistor and the system for continuous learning in a spiking neural network of Hersam ‘007 and Iezzi ‘166 being reconfigurable with gate tunability that enables continuous learning that allows selective forgetting of tasks, thereby freeing up neural resources to learn new tasks; wherein additional learning behaviors are achieved by varying temporal evolution of gate bias pulses; wherein gate pulses are used to modulate potentiation and depression, resulting in learning curves and simplified spike-timing-dependent plasticity that facilitate unsupervised learning in a simulated spiking neural network (SNN); wherein a library of learning curves obtained from temporal evolution of a pulsing amplitude is used to perform unsupervised image recognition in the SNN with functions of continuous learning; wherein the unsupervised learning in the SNN is performed using an experimental memtransistor learning behavior modelled in a simplified spike-timing-dependent plasticity (STDP) scheme; wherein each synaptic unit has learning and/or unlearning behaviors with gate-tunable characteristics of the memtransistors; and wherein switching LTP-LTD learning behavior is achieved by only reversing a polarity of gate pulses, while further adjustments in a gate amplitude produce learning curves and thus learning behaviors as taught by Iezzi ‘166 to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity and Tang ‘092 to design neural systems having machine learning properties. Further, because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, transferred onto a second substrate of SiO2/Si, and formed as the memtransistor as disclosed, the device is presumed capable of performing the functions and intended uses as claimed.
Claims 31 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Hersam ‘007 and Iezzi ‘166 as applied to claims 32 and 33 above, and further in view of Kamiya et al. (US Patent Application Publication 2010/0213420, hereinafter Kamiya ‘420) of record.
With respect to claim 31, Hersam ‘007 and Iezzi ‘166 teach the device as described in claim 32 above with the exception of the additional limitation wherein the sub-stoichiometric S:Mo ratio is about 1.82.
However, Kamiya ‘420 teaches a MoS2 thin film (“a” and “b”) having a sub-stoichiometric S:Mo ratio (i.e. less than 2:1) between 1.6 and 2.0 ([0110]) to reduce the crystallinity of the MoS2 thin film ([0111]) which would have application in e.g., devices requiring low-temperature processing.
Further, it would have been obvious to one of ordinary skill in the art to optimize the S:Mo ratio and arrive at the claimed limitation because the S:Mo ratio is a result effective variable. Varying the S:Mo ratio affects the crystallinity of the MoS2 think film. Because the general conditions are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). See MPEP 2144.05 II.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the sub-stoichiometric S:Mo ratio of Hersam ‘007 and Iezzi ‘166 to about 1.82 as taught by Kamiya ‘420 to reduce the crystallinity of the MoS2 thin film which would have application in e.g., devices requiring low-temperature processing, and as a matter of routine optimization.
With respect to claim 34, Hersam ‘007 and Iezzi ‘166 teach the device as described in claim 33 above, with primary reference Hersam ‘007 teaching the additional limitation wherein the 2D semiconductor material comprises MoS2 ([0088]).
Thus, Hersam ‘007 is shown to teach all the features of the claim with the exception of wherein the polycrystalline monolayer film has a sub-stoichiometric S:Mo ratio.
However, Kamiya ‘420 teaches a MoS2 thin film (“a” and “b”) having a sub-stoichiometric S:Mo ratio (i.e. less than 2:1) between 1.6 and 2.0 ([0110]) to reduce the crystallinity of the MoS2 thin film ([0111]) which would have application in e.g., devices requiring low-temperature processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the polycrystalline monolayer film of Hersam ‘007 and Iezzi ‘166 having a sub-stoichiometric S:Mo ratio as taught by Kamiya ‘420 to reduce the crystallinity of the MoS2 thin film which would have application in e.g., devices requiring low-temperature processing.
Response to Arguments
Applicant’s amendments to claims 1, 9, 14, and 21 are sufficient to overcome the 35 U.S.C. 112(b) rejections of claims 1, 6-21, and 31 made in the non-final rejection filed 20 November 2025. The 35 U.S.C. 112(b) rejections of claims 1, 6-21, and 31 have been withdrawn.
Applicant's arguments filed 13 February 2026 with respect to the 35 U.S.C. 103 rejection of claim 1 have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 6) that Hersam ‘007 fails to teach or suggest, “a polycrystalline monolayer film characterized by a reduced density of lattice defects and a specific crystallographic registry resulting from being grown directly on a first substrate and transferred onto a second substrate,” as amended. Applicant identifies that the MoS2 flakes of Hersam ‘007 are grown on an SiO2/Si substrate. Applicant discloses that growing on sapphire reduces the distribution of grain boundary angles and defect density. This reduction in defects is functionally and purposefully essential: it attenuates the lateral resistive switching response, thereby allowing the vertical electric field from the gate to exert a dominant effect. One skilled in the art would have no motivation to utilize the more complex sapphire-growth-and-transfer process to achieve an “attenuated” response unless they were specifically seeking the gate-tunable reconfigurability disclosed herein. Examiner respectfully disagrees.
Hersam ‘007 is not cited to address the limitation, “a polycrystalline monolayer film characterized by a reduced density of lattice defects and a specific crystallographic registry resulting from being grown directly on a first substrate and transferred onto a second substrate.” Rather, Iezzi ‘166 teaches this feature as set forth in the above rejection. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Iezzi ‘166 teaches growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]). Such a process would result in a polycrystalline monolayer film characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses as claimed.
Further, Iezzi ‘166 provides a motivation to grow the polycrystalline monolayer film directly on a first substrate and transfer it onto a second substrate: such a process produces large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]). The fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Applicant argues (remarks, pp. 6-7) that the prior art of record fails to teach or suggest the newly presented feature of the claim wherein the device reconfigures between LTP and LTD solely by reversing the polarity of the gate bias without changing the polarity of the drain pulses. The claim now ties the physical structure (reduced defects from sapphire growth) to the functional utility (gate-driven reconfigurability). This synergy is not a predictable result of combining known elements, as the attenuated resistive switching is a specific requirement for the “continuous learning” logic demonstrated in the application. Applicant maintains that in conventional neuromorphic hardware, switching from potentiation to depression typically requires reversing the drain bias, which is less bio-realistic and hinders the “continuous learning” capability where synapses must unlearn or forget tasks selectively while other neurons remain active. The present invention achieves this reversal through gate-controlled Schottky barrier modulation at the contacts, a mechanism uniquely enabled by the high-quality material properties of the polycrystalline monolayer film grown on sapphire. This unique capability is enabled by the specific material properties of the polycrystalline monolayer film grown on sapphire, which modulates the Schottky barrier height at the contacts in a manner not taught by the cited prior art references. Furthermore, none of cited prior art references, alone or in combination, teach or suggest a device architecture capable of this bio-realistic, gate-driven switching. A combination of Hersam ‘007, Iezzi ‘166, Kamiya ‘420, and Tang ‘092 does not lead to the unexpected results demonstrated by Applicant, specifically, the implementation of “continuous learning” and “selective forgetting.” Examiner respectfully disagrees.
As discussed above, Iezzi ‘166 teaches growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]). Such a process would result in a polycrystalline monolayer film characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses as claimed.
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the polycrystalline monolayer film of MoS2 of Hersam ‘007 and Iezzi ‘166 would inherently have the property of characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the reduced density of lattice defects in the polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, quartz, graphene, or hexagonal boron nitride and transferred onto a second substrate of SiO2/Si or of a high-k dielectric layer including Al2O3 or HfO2, which are the same materials and processes as disclosed. Because the polycrystalline monolayer film of Hersam ‘007 in view of Iezzi ‘166 is the same as the polycrystalline monolayer film as disclosed, said polycrystalline monolayer film enables the gate electrode to qualitatively reconfigure synaptic learning behavior between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias without changing a polarity of drain pulses as claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893