DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 June 2026 has been entered.
Status of the Claims
Amendment filed 9 June 2026 is acknowledged. Claims 1, 31, 33, and 34 have been amended. Claims 1, 6-9, 13-21, and 31-34 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 17-19, 32, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Hersam et al. (US Patent Application Publication 2016/0248007, hereinafter Hersam ‘007) in view of Iezzi et al. (US Patent Application Publication 2014/0353166, hereinafter Iezzi ‘166), both of record.
With respect to claim 1, Hersam ‘007 teaches (FIGs. 1A-1C) a memtransistor substantially as claimed, comprising:
a polycrystalline monolayer film (120; the MoS2 monolayer film is described as being polycrystalline in para. [0102, 0105, 0120]) of an atomically thin material ([0076]);
a gate electrode (140) defined on a second substrate (110 and 140) ([0076]); and
source and drain electrodes (131 and 132) spatially-apart formed on the polycrystalline monolayer film (120) to define a channel region (125) in the polycrystalline monolayer film therebetween ([0076]), and
wherein the gate electrode (140) is capacitively coupled (by dielectric 110) with the channel region (125) ([0076]).
Thus, Hersam ‘007 is shown to teach all the features of the claim with the exception of:
wherein the polycrystalline monolayer film is characterized by a reduced density of lattice defects and a specific crystallographic registry resulting from being grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride,
wherein the memtransistor is configured such that a synaptic learning behavior of the memtransistor is qualitatively reconfigurable between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias applied to the gate electrode while maintaining a fixed polarity of drain pulses applied between the source and drain electrodes; and
wherein the reduced density of lattice defects in the polycrystalline monolayer film attenuates resistive switching induced by the drain pulses relative to a vertical field effect induced by the gate bias, thereby enabling the gate electrode to exert dominant control over the synaptic learning behavior.
However, Iezzi ‘166 teaches growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]). Such a process would result in a polycrystalline monolayer film characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the memtransistor is configured such that a synaptic learning behavior of the memtransistor is qualitatively reconfigurable between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias applied to the gate electrode while maintaining a fixed polarity of drain pulses applied between the source and drain electrodes; and wherein the reduced density of lattice defects in the polycrystalline monolayer film attenuates resistive switching induced by the drain pulses relative to a vertical field effect induced by the gate bias, thereby enabling the gate electrode to exert dominant control over the synaptic learning behavior as claimed.
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the polycrystalline monolayer film of MoS2 of Hersam ‘007 and Iezzi ‘166 would inherently have the property of characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the memtransistor is configured such that a synaptic learning behavior of the memtransistor is qualitatively reconfigurable between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias applied to the gate electrode while maintaining a fixed polarity of drain pulses applied between the source and drain electrodes; and wherein the reduced density of lattice defects in the polycrystalline monolayer film attenuates resistive switching induced by the drain pulses relative to a vertical field effect induced by the gate bias, thereby enabling the gate electrode to exert dominant control over the synaptic learning behavior because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, quartz, graphene, or hexagonal boron nitride and transferred onto a second substrate of SiO2/Si or of a high-k dielectric layer including Al2O3 or HfO2, which are the same materials and processes as disclosed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the polycrystalline monolayer film of Hersam ‘007 grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride resulting in said polycrystalline monolayer film being characterized by a reduced density of lattice defects and a specific crystallographic registry, wherein the memtransistor is configured such that a synaptic learning behavior of the memtransistor is qualitatively reconfigurable between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias applied to the gate electrode while maintaining a fixed polarity of drain pulses applied between the source and drain electrodes; and wherein the reduced density of lattice defects in the polycrystalline monolayer film attenuates resistive switching induced by the drain pulses relative to a vertical field effect induced by the gate bias, thereby enabling the gate electrode to exert dominant control over the synaptic learning behavior as taught by Iezzi ‘166 to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity and because these properties are presumed to be inherent.
Further, the limitations, “wherein the memtransistor is configured such that a synaptic learning behavior of the memtransistor is qualitatively reconfigurable between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias applied to the gate electrode while maintaining a fixed polarity of drain pulses applied between the source and drain electrodes; and wherein the reduced density of lattice defects in the polycrystalline monolayer film attenuates resistive switching induced by the drain pulses relative to a vertical field effect induced by the gate bias, thereby enabling the gate electrode to exert dominant control over the synaptic learning behavior,” are a mix of functional recitations and descriptions of intended use. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Still further, the expression “grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride,” is taken to be a product-by-process limitation and is given limited patentable weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
With respect to claim 6, Hersam ‘007 teaches wherein the second substrate (110 and 140) is an SiO2/Si substrate, or a substrate of a high-k dielectric layer including Al2O3 or HfO2 ([0088]).
With respect to claim 7, Hersam ‘007 teaches wherein the SiO2/Si substrate comprises a silicon substrate with a silicon dioxide overlayer ([0088]).
With respect to claim 8, Hersam ‘007 teaches wherein the gate (140), source (131) and drain (132) electrodes comprises a same conductive material or different conductive materials ([0088]).
With respect to claim 17, Hersam ‘007 in view of Iezzi ‘166 teach (FIGs. 1A-1C) a circuit as claimed, comprising one or more memtransistors according to claim 1 (see the rejection of claim 1 above).
With respect to claim 18, Hersam ‘007 in view of Iezzi ‘166 teach (FIGs. 1A-1C) an electronic device as claimed, comprising one or more memtransistors according to claim 1 (see the rejection of claim 1 above).
With respect to claim 19, Hersam ‘007 in view of Iezzi ‘166 teach (FIGs. 1A-1C) a system for continuous learning in a spiking neural network as claimed, comprising:
one or more synaptic units (110, 120, 125, 131, 132, and 140), wherein each synaptic unit comprises one or more memtransistors according to claim 1 (see the rejection of claim 1 above).
With respect to claim 32, Hersam ‘007 teaches wherein the atomically thin material (the polycrystalline MoS2 monolayer film) comprises two-dimensional (2D) semiconductor material ([0088]).
With respect to claim 33, Hersam ‘007 teaches wherein the 2D semiconductor material is selected from the group consisting of MoS2, MoSe2, WS2, WSe2, InSe, GaTe, and black phosphorus (BP) ([0088]).
Claims 9, 13-16, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hersam ‘007 and Iezzi ‘166 as applied to claims 1 and 19 above, and further in view of Tang et al. (US Patent Application Publication 2012/0011092, hereinafter Tang ‘092) of record.
With respect to claims 9, 13-16, 20, and 21, Hersam ‘007 and Iezzi ‘166 teach the devices as described in claims 1 and 19 above, but primary reference Hersam ‘007 does not explicitly teach the additional limitations being reconfigurable with gate tunability that enables continuous learning that allows selective forgetting of tasks, thereby freeing up neural resources to learn new tasks; wherein additional learning behaviors are achieved by varying temporal evolution of gate bias pulses; wherein gate pulses are used to modulate potentiation and depression, resulting in learning curves and simplified spike-timing-dependent plasticity that facilitate unsupervised learning in a simulated spiking neural network (SNN); wherein a library of learning curves obtained from temporal evolution of a pulsing amplitude is used to perform unsupervised image recognition in the SNN with functions of continuous learning; wherein the unsupervised learning in the SNN is performed using an experimental memtransistor learning behavior modelled in a simplified spike-timing-dependent plasticity (STDP) scheme; wherein each synaptic unit has learning and/or unlearning behaviors with gate-tunable characteristics of the memtransistors; and wherein switching LTP-LTD learning behavior is achieved by only reversing a polarity of gate pulses, while further adjustments in a gate amplitude produce learning curves and thus learning behaviors.
However, Iezzi ‘166 teaches a bottom-gate memtransistor formed by growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]).
Further, Tang ‘092 teaches memristive devices used for designing neural systems having machine learning properties ([0037[).
Still further, the limitations of claims 9-16, 20, and 21 merely recite functional language and intended use. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, transferred onto a second substrate of SiO2/Si, and formed as the memtransistor as disclosed, the device is presumed capable of performing the functions and intended uses as claimed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the memtransistor and the system for continuous learning in a spiking neural network of Hersam ‘007 and Iezzi ‘166 being reconfigurable with gate tunability that enables continuous learning that allows selective forgetting of tasks, thereby freeing up neural resources to learn new tasks; wherein additional learning behaviors are achieved by varying temporal evolution of gate bias pulses; wherein gate pulses are used to modulate potentiation and depression, resulting in learning curves and simplified spike-timing-dependent plasticity that facilitate unsupervised learning in a simulated spiking neural network (SNN); wherein a library of learning curves obtained from temporal evolution of a pulsing amplitude is used to perform unsupervised image recognition in the SNN with functions of continuous learning; wherein the unsupervised learning in the SNN is performed using an experimental memtransistor learning behavior modelled in a simplified spike-timing-dependent plasticity (STDP) scheme; wherein each synaptic unit has learning and/or unlearning behaviors with gate-tunable characteristics of the memtransistors; and wherein switching LTP-LTD learning behavior is achieved by only reversing a polarity of gate pulses, while further adjustments in a gate amplitude produce learning curves and thus learning behaviors as taught by Iezzi ‘166 to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity and Tang ‘092 to design neural systems having machine learning properties. Further, because the polycrystalline monolayer film of MoS2 is grown directly on a first substrate formed of sapphire, transferred onto a second substrate of SiO2/Si, and formed as the memtransistor as disclosed, the device is presumed capable of performing the functions and intended uses as claimed.
Claims 31 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Hersam ‘007 and Iezzi ‘166 as applied to claim 32 above, and further in view of Kamiya et al. (US Patent Application Publication 2010/0213420, hereinafter Kamiya ‘420) of record.
With respect to claim 31, Hersam ‘007, Iezzi ‘166, and Kamiya ‘420 teach the device as described in claim 32 above, but primary reference Hersam ‘007 does not explicitly teach the additional limitation wherein the sub-stoichiometric S:Mo ratio is about 1.82.
However, Kamiya ‘420 teaches a MoS2 thin film (“a” and “b”) having a sub-stoichiometric S:Mo ratio (i.e. less than 2:1) between 1.6 and 2.0 ([0110]) to reduce the crystallinity of the MoS2 thin film ([0111]) which would have application in e.g., devices requiring low-temperature processing.
Further, it would have been obvious to one of ordinary skill in the art to optimize the S:Mo ratio and arrive at the claimed limitation because the S:Mo ratio is a result effective variable. Varying the S:Mo ratio affects the crystallinity of the MoS2 think film. Because the general conditions are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). See MPEP 2144.05 II.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the sub-stoichiometric S:Mo ratio of Hersam ‘007, Iezzi ‘166, and Kamiya ‘420 to about 1.82 as taught by Kamiya ‘420 to reduce the crystallinity of the MoS2 thin film which would have application in e.g., devices requiring low-temperature processing, and as a matter of routine optimization.
With respect to claim 34, Hersam ‘007 and Iezzi ‘166 teach the device as described in claim 32 above, with primary reference Hersam ‘007 teaching the additional limitation wherein the 2D semiconductor material comprises MoS2 ([0088]).
Thus, Hersam ‘007 is shown to teach all the features of the claim with the exception of wherein the polycrystalline monolayer film has a sub-stoichiometric S:Mo ratio.
However, Kamiya ‘420 teaches a MoS2 thin film (“a” and “b”) having a sub-stoichiometric S:Mo ratio (i.e. less than 2:1) between 1.6 and 2.0 ([0110]) to reduce the crystallinity of the MoS2 thin film ([0111]) which would have application in e.g., devices requiring low-temperature processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the polycrystalline monolayer film of Hersam ‘007 and Iezzi ‘166 having a sub-stoichiometric S:Mo ratio as taught by Kamiya ‘420 to reduce the crystallinity of the MoS2 thin film which would have application in e.g., devices requiring low-temperature processing.
Response to Arguments
Applicant’s amendments to claim 33 are sufficient to overcome the objection to claim 33 made in the final rejection filed 12 March 2026. The objection to claim 3 has been withdrawn.
Applicant’s amendments to claims 31, 33, and 34 are sufficient to overcome the 35 U.S.C. 112(b) rejections of claims 31, 33, and 34 made in the final rejection filed 12 March 2026. The 35 U.S.C. 112(b) rejections of claims 31, 33, and 34 have been withdrawn.
Applicant's arguments filed 9 June 2026 with respect to the 35 U.S.C. 103 rejections of claims 1, 6-9, 13-21, and 31-34 have been fully considered but they are not persuasive.
Applicant argues (remarks, pp. 7-8) that Hersam ‘007 teaches drain-polarity switching, not gate-only switching as recited in claim 1. See FIG. 2B and para. [0091]. The gate electrode (140) in Hersam ‘007 is used to tune the SET voltage ([0097]), but not to qualitatively reconfigure the learning behavior (LTP VS. LTD) without changing drain polarity. Hersam ‘007 does not teach or suggest a memtransistor wherein LTP and LTD are selectable solely by reversing gate bias while drain pulses remain at a fixed polarity. Iezzi ‘166 does not cure this deficiency. Applicant maintains that there is no evidence that the memristor of Hersam ‘007, even if formed on a sapphire-grown and transferred film as taught by Iezzi ‘166, would exhibit the claimed gate-only LTP/LTD reconfiguration. Examiner respectfully disagrees.
The claims are directed to an apparatus, not a method of use. The limitation, “wherein the memtransistor is configured such that a synaptic learning behavior of the memtransistor is qualitatively reconfigurable between long-term potentiation (LTP) and long-term depression (LTD) solely by reversing a polarity of a gate bias applied to the gate electrode while maintaining a fixed polarity of drain pulses applied between the source and drain electrodes,” is a mix of functional recitations and a description of intended use. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Although the device of Hersam ‘007 is not described as relying on gate-only switching, the combination of Hersam ‘007 and Iezzi ‘166 could use gate-only switching by applying gate bias while keeping the drain at a fixed polarity with a reasonable expectation of success. This would result in LTP and LTD being selectable solely by reversing gate bias while drain pulses remain at a fixed polarity.
Applicant argues (remarks, pp. 8) the recognition that reduced defect density (from sapphire growth) attenuates the drain switching response to such an extent that the gate can dominate the synaptic learning behavior is a non-obvious design choice. The ordinary artisan would typically view defects as essential for memristive switching and would therefore expect that reducing defects would degrade device performance. Applicant instead leverages a moderate defect density to achieve a new, bio-realistic function. This is the essence of an inventive step. Examiner respectfully disagrees.
Iezzi ‘166 teaches growing a polycrystalline MoS2 monolayer film directly on a sapphire substrate, and then transferring said film to an SiO2/Si substrate ([0085]) to produce large-area, high quality MoS2 monolayer films with unprecedented uniformity ([0090]). The fact that the inventor has recognized another advantage (i.e. attenuating the drain switching response to such an extent that the gate can dominate the synaptic learning behavior) which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Applicant argues (remarks, pp. 8-9) that claim 1 recites not merely a product-by-process limitation but a specific structural characteristic (reduced density of lattice defects from sapphire growth) directly tied to a functional capability (attenuation of drain switching, enabling gate-only LTP/LTD reconfiguration). This is not a “mere intended use.” Examiner respectfully disagrees.
Examiner cites merely the limitation, “grown directly on a first substrate and transferred onto a second substrate, wherein the first substrate is formed of sapphire, quartz, graphene, or hexagonal boron nitride,” as being a product-by-process limitation. The cited structural characteristic (reduced density of lattice defects from sapphire growth) is a byproduct of the obvious combination of Hersam ‘007 in view Iezzi ‘166, and the functional capability (attenuation of drain switching, enabling gate-only LTP/LTD reconfiguration) may be obtained by said combination.
Applicant argues (remarks, pp. 9-10) that the memristor of Tang ‘092 is a two-terminal device, and does not disclosure or suggest a synaptic device who weight-update rule is tunable by a gate electrode. Applicant maintains that the limitations of claims 9, 13-16, 20, and 21 are not “mere intended uses.” Applicant maintains that the prior art structure is not capable of performing the claimed functions because it lacks the fundamental switching mode of gate-only LTP/LTD reconfiguration. Tang ‘009 does not provide any teaching or motivation to add a gate electrode for synaptic plasticity control. The memristor of Tang ‘009 is a passive component in a neuron soma, not an active, three-terminal synapse with a modulatory input. A person of ordinary skill would have no reason to combine Hersam ‘007 (a two-terminal-switching memristor), Iezzi ‘166 (a growth method), and Tang ‘009 (a neuron circuit design) to arrive at a three-terminal synaptic memtransistor with gate-only LTP-LTD reconfiguration and continuous learning capabilities. Examiner respectfully disagrees.
Tang ‘092 teaches memristive devices used for designing neural systems having machine learning properties ([0037[). Although the memristive device of Tang ‘092 does not have the same number of terminals as the memristor of Hersam ‘007, the principle of applying memristive devices for designing neural systems having machine learning properties of Tang ‘092 could be applied to the memristor of Hersam ‘007 with a reasonable expectation of success. The memristive device of Hersam ‘007 with the modifications supplied by Iezzi ‘166 and using operating principles (i.e. designing neural systems having machine learning properties) of Tang ‘092 would be capable of performing the functions and/or intended uses of claims 9, 13-16, 20, and 21.
Applicant argues (remarks, p. 10) that Kamiya ‘420 teaches a range of S:Mo ratios (1.6-2.0) for a catalyst material in a fuel cell, not for a memtransistor. The selection of a specific ratio (~1.82) as recited in claim 31 to achieve a particular balance of defect density for gate-dominant switching is not obvious from Kamiya ‘420, which is directed to an entirely different field of art. Examiner respectfully disagrees.
Kamiya ‘420 teaches a MoS2 thin film (“a” and “b”) having a sub-stoichiometric S:Mo ratio (i.e. less than 2:1) between 1.6 and 2.0 ([0110]) to reduce the crystallinity of the MoS2 thin film ([0111]) which would have application in e.g., devices requiring low-temperature processing. Although the MoS2 monolayer of Kamiya ‘420 may find utility in a different application, Kamiya ‘420 remains analogous art to the claimed invention, and to Hersam ‘007 in view of Iezzi ‘166, as being directed to formation of molybdenum sulfide monolayer thin films.
Conclusion
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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