ELECTRONIC DEVICE

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/04/2026 has been entered. Response to Amendments Applicant's response of 08/05/2026 has been acknowledged. Claims 1, 6-8 and 14 have been amended. No new matter has been added. This office action considers claims 1-4 and 6-20 pending for prosecution and are examined on their merits. Response to Arguments Applicant’s arguments filed 08/05/2026 with respect to the rejection of claims 1 and 14 have been fully considered but are moot in view of the new grounds of rejection. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. Claims 1-4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 112507828 A – hereinafter Liu) in view of Li et al. (US 20220376006 A1 – hereinafter Li), Zhang et al. (US 20240257734 A1 – hereinafter Zhang) , Zhou et al. (US 20210408095 A1 – hereinafter Zhou), and Xie et al. (US 20180165498 A1 – hereinafter Xie). Regarding independent claim 1, Liu teaches (Currently Amended) An electronic device ([n00040] – “The purpose of the present application is to provide an optical fingerprint recognition structure and a manufacturing method thereof, and a display device”) comprising: a base layer (110 – Fig. 2 annotated, see below – [n0062] – “substrate 110”); a pixel definition layer (160 – Fig. 2 – [n0076] – “pixel defining layer 160”) disposed on the base layer (110), the pixel definition layer (160) including a first opening (161 – Fig. 2 annotated, see below – hereinafter ‘161-2’) extending therethrough and a second opening (161 – Fig. 2 – [n0076] – “opening 161”) extending therethrough; a light emitting element (Fig. 2 annotated, see below – [n0060] – “including a display area and a sensing area, wherein the display area includes a first TFT formed on a substrate 110 and a light-emitting device driven by the first TFT to emit light, and the light-emitting device is driven by the first TFT to emit light to the finger” – hereinafter ‘LED’) disposed on the base layer (110) and overlapping the first opening (161-2); a light sensing element (Fig. 2 annotated, see below – [n0060] – “The sensing area includes a second TFT 130, a PIN photodiode 140 and a capacitor 150 formed on the substrate, wherein the second TFT 130 includes a source 131, a drain 132, an active area 133” – this is a light sensing element, hereinafter ‘LSE’) disposed on the base layer (110) and overlapping the second opening (161), the light sensing element (LSE) comprising a photodiode (140 – Fig. 1 – [n0084] – “intrinsic region 143 of the PIN photodiode 140”) and a conductive pattern that directly contacts the photodiode; a first pixel transistor connected to the light emitting element, the first pixel transistor comprises a first semiconductor pattern and a first electrode; a second pixel transistor electrically connected to the first pixel transistor and the light emitting element, wherein the second pixel transistor comprises a second semiconductor pattern and a second electrode, the second semiconductor pattern comprises a material different from a material of the first semiconductor pattern, a sensing transistor (130 – Fig. 2 annotated, see below – [n0060] – “The sensing area includes a second TFT 130, a PIN photodiode 140 and a capacitor 150 formed on the substrate, wherein the second TFT 130 includes a source 131, a drain 132, an active area 133”) connected to the light sensing element (LSE); and an insulating layer over the first electrode and disposed between the first semiconductor pattern and the second semiconductor pattern in a thickness direction of the base layer, and wherein the light sensing element is disposed between a layer that the first and second pixel transistors is disposed and a layer that the light emitting element is disposed, wherein the light sensing element is disposed on the insulating layer and wherein the light sensing element is apart from the light emitting element in a plan view. PNG media_image1.png 545 755 media_image1.png Greyscale Liu does not expressly disclose the other limitations of claim 1. However, in an analogous art, Li teaches a conductive pattern (201 – Fig. 2 – [0077] – “the first electrode 201 of the photosensitive element 2”) that directly contacts the photodiode (2 – Fig. 2 – [0051] – “photosensitive element 2 is a PIN photodiode” – Fig. 2 shows this), wherein the light sensing element (2) is disposed between a layer that the first and second pixel transistors (Fig. 2 annotated, see below – hereinafter ‘T1’ and ‘T2’ respectively) is disposed and a layer that the light emitting element (10 – Fig. 2 – [0051] – “display element 10 is an Organic Light-Emitting Diode (OLED)”) is disposed (Fig. 2 shows this), wherein the light sensing element (2) is disposed on the insulating layer (7 – Fig. 2 – [0067] – “cover layer 7 has an insulation function”) and wherein the light sensing element (2) is apart from the light emitting element (10). PNG media_image2.png 611 1101 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive pattern and light sensing element structure as taught by Li into Liu. An ordinary artisan would have been motivated to use the known technique of Li in the manner set forth above to produce the predictable result of correcting the problem of [0003] – “the amount of light reflected by the valley of the fingerprint and reaching the photosensitive element and the amount of light reflected by the ridge of the fingerprint and reaching the photosensitive element are less, so that the difference between the electrical signals generated by the photosensitive element corresponding to the valley of the fingerprint and the photosensitive element corresponding to the ridge of the fingerprint is less, which affects the final recognition accuracy.” Liu and Li do not expressly disclose the other limitations of claim 1. However, in an analogous art, Zhang teaches a first pixel transistor ([0048] – “the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors”) connected to the light emitting element (OLED – Fig. 2 – [0048] – “light emitting unit OLED”), the first pixel transistor (T6) comprises a first semiconductor pattern ([0048] – “the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors” – hereinafter ‘A6’) and a first electrode ([0048] – “second electrode of the sixth transistor T6” – hereinafter ‘T6SE’); a second pixel transistor (T2 – Fig. 2 – [0048] – “transistor T2 can be N-type metal oxide transistors”) electrically connected to the first pixel transistor (T6 – Fig. 2 shows this) and the light emitting element (OLED – Fig. 2 shows this), wherein the second pixel transistor (T2) comprises a second semiconductor pattern ([0048] – “transistor T2 can be N-type metal oxide transistors” – hereinafter ‘A2’) and a second electrode ([0048] – “first electrode of the second transistor T2 is connected to the node N” – hereinafter ‘T2FE’), the second semiconductor pattern (A2) comprises a material different from a material of the first semiconductor pattern (A6). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transistor structure as taught by Zhang into Liu and Li. An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of [0048] – “The low-temperature polycrystalline silicon transistors have high carrier mobility, thus being beneficial to realizing a display panel with high resolution, high reaction speed, high pixel density and high aperture ratio.” Liu, Li, and Zhang do not expressly disclose the other limitations of claim 1. However, in an analogous art, Zhou teaches an insulating layer (410 – Fig. 3 – [0066] – “first interlayer insulating layer 410”) over the first electrode (12 – Fig. 3 – [0066] – “first gate 12”) and disposed between the first semiconductor pattern (11 – Fig. 3 – [0067] – “polysilicon active layer 11”) and the second semiconductor pattern (22 – Fig. 3 – [0068] – “oxide active layer 22”) in a thickness direction (Fig. 3 shows this) of the base layer (100 – Fig. 3 – [0066] – “base substrate 100”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer structure as taught by Zhou into Liu, Li, and Zhang. An ordinary artisan would have been motivated to use the known technique of Zhou in the manner set forth above to produce the predictable result of [0005] – “an array substrate, an electronic device, and a manufacturing method of the array substrate, which can improve uniformity and stability of a control unit composed of a first transistor and a second transistor.” Liu, Li, Zhang, and Zhou do not expressly disclose the other limitations of claim 1. However, in an analogous art, Xie teaches wherein the light sensing element is apart from the light emitting element in a plan view (Fig. 1 – [0033] – “As shown in FIG. 1 and FIG. 2, the display panel 1 may include an array substrate 10, a plurality of organic light-emitting structures 12, a plurality of fingerprint identification units 21”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer structure as taught by Xie into Liu, Li, Zhang, and Zhou. An ordinary artisan would have been motivated to use the known technique of Xie in the manner set forth above to produce the predictable result of better visualizing the overall configuration of the device. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Regarding claim 2, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 1 from which claim 2 depends. Liu, Zhang, Zhou, and Xie do not expressly disclose the limitations of claim 2. However, in an analogous art, Li teaches (Original) The electronic device of claim 1, wherein the conductive pattern (203 – Fig. 2 – [0102] – “second electrode 203” – this corresponds to the conductive pattern) comprises a transparent conductive oxide ([0102] – “second electrode material film includes a transparent conductive material film (ensuring that light can enter the photosensitive pattern), such as an indium tin oxide material film”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive structure as taught by Li into Liu, Zhang, Zhou, and Xie. An ordinary artisan would have been motivated to use the known technique of Li in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding claim 3, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 1 from which claim 3 depends. Liu further teaches (Previously Presented) The electronic device of claim 1, wherein: the sensing transistor (130) comprises: a semiconductor pattern (133 – Fig. 3 – [n0060] – “an active area 133” – this is a semiconductor pattern) disposed on a same layer (170 – Fig. 3 – [n0087] – “insulating layer 170”) as a layer that the first semiconductor pattern (123) is disposed (Fig. 2 shows this); and an electrode (131 – Fig. 3 – [n0085] – “the source 131” – this is the source electrode) disposed on a same layer (170) as a layer that the first electrode (130) is disposed (Fig. 3 shows this). Regarding claim 4, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 3 from which claim 4 depends. Liu further teaches (Original) The electronic device of claim 3, further comprising: a first conductive pattern (127 – Fig. 3 – [n0087] – “metal portion 127” – this is a conductive pattern), connected to the first semiconductor pattern (123); and a second conductive pattern (137 – Fig. 2 – [n0087] – “metal portion 137”) connected to a semiconductor pattern (133) of the sensing transistor (130) and disposed on a same layer (1100 – Fig. 2 – [n0088] – “planarization layer 1100”) as a layer that the first conductive pattern (127) is disposed, wherein the photodiode (140) directly contacts the second conductive pattern (137 – Fig. 2 shows this). Regarding claim 8, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 1 from which claim 8 depends. Liu, Li, Zhang and Xie do not expressly disclose the limitations of claim 8. However, in an analogous art, Zhou teaches (Currently Amended) The electronic device of claim 1, wherein the second semiconductor pattern (22 – Fig. 3 – [0068] – “oxide active layer 22”) comprises an oxide semiconductor, and the first semiconductor pattern (11 – Fig. 3 – [0067] – “polysilicon active layer 11”) comprises polysilicon. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive structure as taught by Zhou into Liu, Li, Zhang, and Xie. An ordinary artisan would have been motivated to use the known technique of Zhou in the manner set forth above to produce the predictable result as stated above in claim 1. Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Li, Zhang, Zhou, Xie, and Oh et al. (US 20160064421 A1 – hereinafter Oh). Regarding claim 6, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 5 from which claim 6 depends. Liu, Li, Zhang, Zhou, and Xie do not expressly disclose the limitations of claim 6. However, in an analogous art, Oh teaches (Currently Amended) The electronic device of claim 5 1, wherein the second semiconductor pattern (ACT2 – Fig. 4 – [0075] – “semiconductor pattern ACT2”) and the second electrode (G2) are disposed between the layer that the first electrode (G1 – Fig. 4 – [0074] – “gate G1” – this is an electrode, Fig. 4 shows this) is disposed and the layer that the first conductive pattern (D2 – Fig. 4 – [0047] – “drain D2”) – this compares to the conductive pattern) is disposed. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the semiconductor and conductive pattern structure as taught by Oh into Liu, Li, Zhang, Zhou, and Xie. An ordinary artisan would have been motivated to use the known technique of Oh in the manner set forth above to produce the predictable result to [0010] - "to provide a thin film transistor substrate for flat panel display having at least two transistors of different characteristics on the same substrate". Regarding claim 7, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 5 from which claim 6 depends. Liu, Li, Zhang, Zhou, and Xie do not expressly disclose the limitations of claim 7. However, in an analogous art, Oh teaches (Currently Amended) The electronic device of claim 5 1, further comprising a metal pattern (E11 – Fig. 4 – [0079] – “electrode E11” – this is a metal pattern) disposed under the second semiconductor pattern (ACT2 – Fig. 4 – [0075] – “semiconductor pattern ACT2”), wherein the metal pattern (E11) is disposed on a same layer as the layer that the first electrode (G1 – Fig. 4 – [0074] – “gate G1” – this is an electrode, Fig. 4 shows this) is disposed. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the semiconductor and conductive pattern structure as taught by Oh into Liu, Li, Zhang, Zhou, and Xie. An ordinary artisan would have been motivated to use the known technique of Oh in the manner set forth above to produce the predictable result to [0010] - "to provide a thin film transistor substrate for flat panel display having at least two transistors of different characteristics on the same substrate". Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Li, Zhang, Zhou, and Xie and Cheng et al. (US 20220214758 A1 – hereinafter Cheng). Regarding claim 9, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 4 from which claim 9 depends. Liu, Zhang, Zhou, and Xie do not expressly disclose the limitations of claim 9. However, in an analogous art, Li teaches a fourth conductive pattern (801a – Fig. 9J – [0068] – “first transparent conductive pattern 801a”) connected to the light sensing element (2 – Fig. 9J – [0068] – “photosensitive element 2”), wherein the third conductive pattern (Fig. 9J annotated, see below – hereinafter ‘1001a’, this is a conductive pattern below element 1001 that is the pixel electrode) is disposed on a same layer (11 – fig. 9J – [0078] – “planarization layer 11”) as a layer that the fourth conductive pattern (801a) is disposed. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the semiconductor and conductive pattern structure as taught by Li into Liu, Zhang, Zhou, and Xie. An ordinary artisan would have been motivated to use the known technique of Li in the manner set forth above to produce the predictable result of solving the issue of [0003] – “the amount of light reflected by the valley of the fingerprint and reaching the photosensitive element and the amount of light reflected by the ridge of the fingerprint and reaching the photosensitive element are less, so that the difference between the electrical signals generated by the photosensitive element corresponding to the valley of the fingerprint and the photosensitive element corresponding to the ridge of the fingerprint is less, which affects the final recognition accuracy.” Liu, Zhang, Zhou, Xie, and Li do not expressly disclose the limitations of claim 9. However, in an analogous art, Cheng teaches (Original) The electronic device of claim 4, further comprising: a third conductive pattern (CP2 – Fig. 2 – [0019] – “conductive patterns CP2”) disposed between the first conductive pattern (DE – Fig. 2 – [0018] – “drain DE” – labeled as DE in Fig. 2 but refers to the conductive pattern) and the light emitting element (PX – Fig. 2 – [0020] – “pixel structures PX”) and connected to the first conductive pattern (DE) and the light emitting element (PX); and a fourth conductive pattern connected to the light sensing element, wherein the third conductive pattern is disposed on a same layer as a layer that the fourth conductive pattern is disposed. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the semiconductor and conductive pattern structure as taught by Cheng into Liu, Zhang, Zhou, Xie, and Li. An ordinary artisan would have been motivated to use the known technique of Cheng in the manner set forth above to produce the predictable result of [0006] – “The spacing between the edge of one pixel opening and the edge of the corresponding electrode opening on one side of the pixel opening where the light sensing device is disposed is greater than the spacing between the edge of another pixel opening and the edge of another corresponding electrode opening on one side of the another pixel opening where no light sensing device is disposed. Accordingly, the light emitted by the light emitting structure disposed in the pixel opening may be prevented from being transmitted to the light sensing device through the internal reflection of the touch electrode layer, and thereby the light sensing sensitivity and accuracy of the touch display panel are improved.” Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Li, Zhang, Zhou, Xie, and Heo et al. (US 20180181240 A1 – hereinafter Heo ). Regarding claim 10, Liu, as modified by Li, Zhang, Zhou, and Xie, teaches claim 1 from which claim 10 depends. Liu, Li, Zhang, Zhou, and Xie do not expressly disclose the limitations of claim 10. However, in an analogous art, Heo teaches (Original) The electronic device of claim 1, further comprising a color filter layer (50 – Fig. 6 – [0066] – “color filter layer 50”) disposed on the light emitting element (20 – Fig. 6 – [0066] – “organic light emitting device layer 20”) and comprising a black matrix (BM1 – Fig. 6 – [0104] – “The black matrix BM may include a plurality of first black matrixes BM1”), wherein the black matrix (BM1) includes openings (Fig. 6 annotated, see below, this shows openings) extending therethrough to respectively overlap the first opening (Fig. 6 annotated, see below, - hereinafter ‘OP1’) and the second opening (Fig. 6 annotated, see below, - hereinafter ‘OP2’). PNG media_image3.png 681 907 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the black matrix structure as taught by Heo into Liu, Li, Zhang, Zhou, and Xie. An ordinary artisan would have been motivated to use the known technique of Heo in the manner set forth above to produce the predictable result to [0010] - "provide a display device with integrated touch screen and a method of manufacturing the same, in which a contrast ratio is enhanced". Regarding claim 12, Liu, as modified by Li, Zhang, Zhou, Xie, and Heo, teaches claim 10 from which claim 12 depends. Liu, Li, Zhang, Zhou, and Xie do not expressly disclose the limitations of claim 12. However, in an analogous art, Heo teaches (Original) The electronic device of claim 10, further comprising an input sensing layer (40 – Fig. 6 – [0098] – “touch sensing layer 40” – this is an input sensing layer) disposed between the color filter layer (50) and the light emitting element (20). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the input sensing layer structure as taught by Heo into Liu, Li, Zhang, Zhou, and Xie. An ordinary artisan would have been motivated to use the known technique of Heo in the manner set forth above to produce the predictable result to [0009] - "provide a display device with integrated touch screen and a method of manufacturing the same, in which an increase in thickness caused by touch electrodes is minimized". Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Li, Zhang, Zhou, Xie, Heo, and Lee at al. (US 20220206620 A1 – hereinafter Lee). Regarding claim 11, Liu, as modified by Li, Zhang, Zhou, Xie, and Heo, teaches claim 10 from which claim 11 depends. Liu, Li, Zhang, Zhou, Xie, and Heo do not expressly disclose the limitations of claim 11. However, in an analogous art, Lee teaches (Original) The electronic device of claim 10, wherein the pixel definition layer (114 – Fig. 4A – [0060] – “bank insulating layer 114” – this is the PDL) comprises a dye or a pigment ([0129] – “bank insulating layer 114 may include a black dye”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dye in the pixel definition layer structure as taught by Lee into Liu, Li, Zhang, Zhou, Xie, and Heo. An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result of [0129] - "the direction of the light emitted from the light-emitting device 130 of each pixel area PA may be restricted by the bank insulating layer 114". Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Li, Zhang, Zhou, Xie, Heo, and Kim et al. (US 20190377438 A1 – hereinafter Kim). Regarding claim 13, Liu, as modified by Li, Zhang, Zhou, Xie, and Heo, teaches claim 12 from which claim 13 depends. Liu, Li, Zhang, Zhou, Xie, and Heo do not expressly disclose the limitations of claim 13. However, in an analogous art, Kim teaches (Original) The electronic device of claim 12, wherein the input sensing layer (TS – Fig. 6 – [0098] – “the touch sensor TS includes a base layer BSL”) comprises mesh lines ([0113] – Fig. 6 – “touch electrode 121 has a mesh structure” – 121 is part of the touch sensor) connected to each other, and the mesh lines overlap the pixel definition layer ({[0113] – “For example, the mesh structure may be positioned so that a hole of the mesh structure overlaps the emission area PXA”}, {(PDL – Fig. 5 – [0083] – “pixel defining layer PDL”)} – PDL is in PXA) when viewed in a plane. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the mesh line structure as taught by Kim into Liu, Li, Zhang, Zhou, Xie, and Heo. An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0113] - "when the first touch electrode 121 has a mesh structure, the first touch electrode 121 may be disposed such that it does not overlap with the emission area PXA to prevent it from being observed by a viewer". Claims 14, 15, 16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Heo, Lee, Wang et al. (US 20200044004 A1 – hereinafter Wang), Ito et al. (US 20220199657 A1 – hereinafter Ito), and Zhou. Regarding independent claim 14, Liu teaches: (Currently Amended) An electronic device comprising: a base layer (110 – Fig. 2 annotated, see below – [n0062] – “substrate 110”); a circuit layer (Fig. 2 annotated, see below – hereinafter ‘DP-CL’) disposed on the base layer (110) and comprising a first pixel transistor (Fig. 2 annotated, see below – [n080] – “the source 121, the drain 122 of the first TFT” – hereinafter ‘PT’), a second pixel transistor (Fig. 2 annotated, see below – [n080] – “the source 121, the drain 122 of the first TFT” – hereinafter ‘PT2’), a light sensing element (Fig. 2 annotated, see below – [n0060] – “The sensing area includes a second TFT 130, a PIN photodiode 140 and a capacitor 150 formed on the substrate, wherein the second TFT 130 includes a source 131, a drain 132, an active area 133” – this is a light sensing element, hereinafter ‘LSE’), a sensing transistor (130 – Fig. 2 annotated, see below – [n0060] – “The sensing area includes a second TFT 130, a PIN photodiode 140 and a capacitor 150 formed on the substrate, wherein the second TFT 130 includes a source 131, a drain 132, an active area 133”) connected to the light sensing element (LSE), and an insulating layer (190 – Fig. 2 – [n0087] – “dielectric layer 190 covering the source 121, the drain 122 and the active area 123 of the first TFT, the source 131, the drain 132 and the active area 133 of the second TFT 130 and the PIN photodiode 140”); a pixel definition layer (160) disposed on the circuit layer (DP-CL) and comprising a dye or a pigment, the pixel definition layer (160) including a first opening (161 – Fig. 2 annotated, see below – hereinafter ‘161-2’) and a second opening (161 – Fig. 2 – [n0076] – “opening 161”) and spaced apart from the first opening (161 – Fig. 2 shows this), the second opening overlapping (161) the light sensing element (LSE – Fig. 2 shows this); a light emitting element overlapping (Fig. 2 annotated, see below – [n0060] – “including a display area and a sensing area, wherein the display area includes a first TFT formed on a substrate 110 and a light-emitting device driven by the first TFT to emit light, and the light-emitting device is driven by the first TFT to emit light to the finger” – hereinafter ‘LED’) the first opening (161-2 – Fig. 2 shows this); an encapsulation layer disposed on the light emitting element; and a color filter layer disposed on the encapsulation layer and comprising a black matrix, the light sensing element (LSE) comprising: a photodiode (140) disposed on the sensing transistor (130); and a transparent electrode disposed on the photodiode, wherein the first pixel transistor comprises a first semiconductor pattern and the second pixel transistor comprises a second semiconductor pattern disposed on the upper layer from the first semiconductor pattern and a second electrode, the second semiconductor pattern comprises oxide semiconductor material different from the first semiconductor pattern, the insulating layer is over the first electrode and directly contacting an upper surface of the first pixel transistor, the insulating layer is between the first semiconductor layer and the second semiconductor layer in a thickness direction of the base layer, the photodiode disposed on the insulating layer and is apart from the light emitting element in a plan view, the photodiode does not directly contact the insulating layer. PNG media_image1.png 545 755 media_image1.png Greyscale Liu does not expressly disclose the other limitations of claim 14. However, in an analogous art, Heo teaches an encapsulation layer (30 – Fig. 6 – [0067] – “encapsulation layer 30”) disposed on the light emitting element (20 – Fig. 6 – [0066] – “organic light emitting device layer 20”); and a color filter layer (50 – Fig. 6 – [0066] – “color filter layer 50”) disposed on the encapsulation layer (30) and comprising a black matrix (BM1 – Fig. 6 – [0104] – “The black matrix BM may include a plurality of first black matrixes BM1”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the color filter and black matrix structure as taught by Heo into Liu. An ordinary artisan would have been motivated to use the known technique of Heo in the manner set forth above to produce the predictable result to [0010] - "provide a display device with integrated touch screen and a method of manufacturing the same, in which a contrast ratio is enhanced". Liu and Heo do not expressly disclose the other limitations of claim 14. However, in an analogous art, Lee teaches a pixel definition layer disposed on the circuit layer and comprising a dye or a pigment ([0129] – “bank insulating layer 114 may include a black dye”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dye in the pixel definition layer structure as taught by Lee into Liu and Heo. An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result of [0129] - "the direction of the light emitted from the light-emitting device 130 of each pixel area PA may be restricted by the bank insulating layer 114". Liu, Heo, and Lee do not expressly disclose the other limitations of claim 14. However, in an analogous art, Wang teaches the insulating layer (ILD – Fig. 5(c) – [0062] – “first thin-film transistor 300 and the second thin-film transistor 400 includes: sequentially forming an active layer, a gate insulating layer (GI), a gate electrode, an interlayer insulating layer (ILD), a source electrode and a drain electrode patterning layer”) is over the first electrode (304 – Fig. 2 – [0054] – “gate electrode 304 of the first thin-film transistor 300”) and directly contacting an upper surface of the first pixel transistor (300 – Fig. 2 – [0062] – “first thin-film transistor 300” – Fig. 2 shows this), the photodiode (200 – Fig. 2 – [0048] – “photosensitive unit 200 may comprise: a third electrode 201 and a fourth electrode 202 disposed in opposition to each other, and a PIN photodiode 203 (also called as a PIN photosensitive diode)”) disposed on the insulating layer (ILD) and is apart from the light emitting element (100 – Fig. 3 – [0072] – “self-luminous unit 100”) in a plan view (Fig. 3 shows this), the photodiode (200) does not directly contact the insulating layer (ILD – Fig. 5(c) shows this). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer structure as taught by Wang into Liu, Heo, and Lee. An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable result of [0003] – “A luminance uniformity of a display image of a display device is an important parameter index for assessing the display device; in particular, for an Organic Light-Emitting Diode (which is called as “OLED”) display device, luminance non-uniformity due to process, material, design and the like would result in a decrease in quality of the display image.” To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Liu, Heo, Lee, and Wang do not expressly disclose the other limitations of claim 14. However, in an analogous art, Ito teaches wherein the first pixel transistor (TRp – Fig. 2 – [0039] – “a first transistor TRp is configured to include the crystalline silicon semiconductor layer including the gate electrode GE and the first channel region LTPSCH “) comprises a first semiconductor pattern ([0039] – “a first transistor TRp is configured to include the crystalline silicon semiconductor layer including the gate electrode GE and the first channel region LTPSCH” – hereinafter ‘A1’, Fig. 2 shows this) and a first electrode (ito (GE – Fig. 2 – [0039] – “a first transistor TRp is configured to include the crystalline silicon semiconductor layer including the gate electrode GE and the first channel region LTPSCH “), the second pixel transistor (TRs – Fig. 2 – [0039] – “second transistor TRs is configured to include the oxide semiconductor layer”) comprises a second semiconductor pattern ([0039] – “second transistor TRs is configured to include the oxide semiconductor layer including the gate electrode GE' and the second channel region IGZOCH” – hereinafter ‘A2’) disposed on the upper layer from the first semiconductor pattern ([0039] – “a first transistor TRp is configured to include the crystalline silicon semiconductor layer including the gate electrode GE and the first channel region LTPSCH” – hereinafter ‘A1’, Fig. 2 shows this) and a second electrode (GE – Fig. 2 – [0039] – “a first transistor TRp is configured to include the crystalline silicon semiconductor layer including the gate electrode GE and the first channel region LTPSCH”), the second semiconductor pattern (A2) comprises oxide semiconductor material ([0039] – “second transistor TRs is configured to include the oxide semiconductor layer including the gate electrode GE' and the second channel region IGZOCH” – hereinafter ‘A2’) different from the first semiconductor pattern (A1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second pixel transistor structure as taught by Ito into Liu, Heo, Lee, and Wang. An ordinary artisan would have been motivated to use the known technique of Ito in the manner set forth above to produce the predictable result of [0020] – “According to an aspect of the disclosure, it is possible to provide a display device in which increase in contact resistance and enlargement of a contact area can be suppressed.” To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Liu, Heo, Lee, Wang, and Ito do not expressly disclose the other limitations of claim 14. However, in an analogous art, Zhou teaches the insulating layer (410 – Fig. 3 – [0066] – “first interlayer insulating layer 410”) is between the first semiconductor layer (11 – Fig. 3 – [0067] – “polysilicon active layer 11”) and the second semiconductor layer (22 – Fig. 3 – [0068] – “oxide active layer 22”) in a thickness direction (Fig. 3 shows this) of the base layer (100 – Fig. 3 – [0066] – “base substrate 100”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulating layer structure as taught by Zhou into Liu, Heo, Lee, Wang, and Ito. An ordinary artisan would have been motivated to use the known technique of Zhou in the manner set forth above to produce the predictable result as stated above in claim 1. Regarding claim 15, Liu, as modified by Heo, Lee, Wang, Ito, and Zhou, teaches claim 14 from which claim 15 depends. Liu further teaches (Previously Presented) The electronic device of claim 14, wherein: the sensing transistor (130) comprises a semiconductor pattern (133 – Fig. 3 – [n0060] – “an active area 133” – this is a semiconductor pattern) disposed on a same layer (170 – Fig. 3 – [n0087] – “insulating layer 170”) as a layer that the semiconductor pattern (123) of the pixel transistor (PT) is disposed (Fig. 3 shows this) and an electrode (131) disposed on a same layer as a layer that the electrode (122) of the pixel transistor (PT) is disposed (Fig. 2 shows this). Regarding claim 16, Liu, as modified by Heo, Lee, Wang, Ito, and Zhou, teaches claim 15 from which claim 16 depends. Liu further teaches (Original) The electronic device of claim 15, further comprising a conductive pattern (137 – Fig. 2 – [n0087] – “metal portion 137”) connected to the semiconductor pattern (133) of the sensing transistor (130), wherein the photodiode (140) is disposed on the conductive pattern (143 – Fig. 2 – [n0064] – “the intrinsic region 143 in the PIN photodiode 140 are located on the same layer” – the intrinsic region is conductive therefore this is a conductive pattern) and directly contacts the conductive pattern (137 – Fig. 2 shows this). Regarding claim 19, Liu, as modified by Heo, Lee, Wang, Ito, and Zhou, teaches claim 14 from which claim 19 depends. Liu further teaches (Original) The electronic device of claim 14, wherein the pixel transistor and the sensing transistor comprise polysilicon ([n0080] – “a polysilicon layer formed on the substrate 110, wherein the source 121, the drain 122 of the first TFT, the source 131, the drain 132, the N-type doping region 141 and the P-type doping region 142 of the second TFT 130 are all doped regions formed in the polysilicon layer; the intrinsic region 143 and the active region 123 of the first TFT, and the active region 133 of the second TFT 130 are undoped regions in the polysilicon layer” – all regions contain polysilicon, regions for the first and second TFT are for the sensing transistor and region 123 is for the pixel transistor). Regarding claim 20, Liu, as modified by Heo, Lee, Wang, Ito, and Zhou, teaches claim 14 from which claim 20 depends. Liu, Lee, Wang, Ito, and Zhou do not expressly disclose the limitations of claim 20. However, in an analogous art, Heo teaches (Original) The electronic device of claim 14, further comprising an input sensing layer (40 – Fig. 6 – [0098] – “touch sensing layer 40” – this is an input sensing layer) disposed between the color filter layer (50) and the encapsulation layer (30 – Fig. 6 shows this). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the input sensing layer, the encapsulation layer and the color filter layer structure as taught by Heo into Liu, Lee, Wang, Ito, and Zhou. An ordinary artisan would have been motivated to use the known technique of Heo in the manner set forth above to produce the predictable result to [0008] - "provide a display device with integrated touch screen". Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Heo, Lee, Wang, Ito, Zhou, and Oh. Regarding claim 17, Liu, as modified by Heo, Lee, Wang, Ito, and Zhou, teaches claim 16 from which claim 17 depends. Liu, Heo, Lee, Wang, Ito, and Zhou do not expressly disclose the limitations of claim 17. However, in analogous art, Oh teaches further comprising a second pixel transistor (T2 - Fig. 3 - [0037] - "second TFT T2") spaced apart (Fig. 3 shows this) from the pixel transistor (T1 - Fig. 1 - [0037] - "first TFT T1 ") and connected to the light emitting element ([0061] - "In an organic light emitting display device or a liquid crystal display device of example embodiments, a single switching element may be implemented to have a structure in which the first TFT T1 and the second TFT T2 are connected" - not shown in Fig. 3 but T1 and T2 are transistors for a light emitting element), wherein the second pixel transistor (T2) comprises a second semiconductor pattern (ACT2 - Fig. 4 - [0075] - "semiconductor pattern ACT2") and a second electrode (G2 - Fig. 4 - [0047] - "second TFT T2 includes a gate G2" - this is an electrode of T2) that are disposed on layers respectively different (Fig. 4 shows this) from layers that the semiconductor pattern (ACT1 - Fig. 4 - [0038] - "first semiconductor pattern ACT1 of a first TFT T1") and the electrode (G1 - Fig. 4 - [0074] - "gate G1" - this is an electrode, Fig. 4 shows this) are disposed. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate pixels and light emitting element structure as taught by Oh into Liu, Heo, Lee, Wang, Ito, and Zhou. An ordinary artisan would have been motivated to use the known technique of Oh in the manner set forth above to produce the predictable result [0061] - "When the first TFT T1 and the second TFT T2 are distributed on a plane, an aspect ratio of pixels is lowered. The first and second TFTs are vertically disposed as illustrated in FIGS. 3 and 4, thereby minimizing the disposition area to prevent a degradation of the aspect ratio of pixels. When the first and second TFTs T1 and T2 are applied to a driving circuit within a bezel region, the bezel region may be narrowed". Regarding claim 18, Liu, as modified by Heo, Lee, Wang, Ito, Zhou, and Oh, teaches claim 17 from which claim 18 depends. Liu, Heo, Lee, Wang, Ito, and Zhou do not expressly disclose the limitations of claim 18. However, in analogous art, Oh teaches wherein the second pixel transistor (T2 - [0038] - "TFT T2 includes an oxide semiconductor") comprises an oxide semiconductor. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to the oxide semiconductor structure as taught by Oh into Liu, Heo, Lee, Wang, Ito, and Zhou. An ordinary artisan would have been motivated to use the known technique of Oh in the manner set forth above to produce the predictable result of [0033] - "a thin film transistor using the oxide semiconductor material is suitable for use in a display requiring low frequency driving and/or low power consumption". Pertinent Art For the benefits of the Applicant, US 20220214758 A1, US 20150102344 A1, US 20070252145 A1, and US 20200044004 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including light-emitting/receiving element, or a second light-emitting layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRA/ Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897