DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed October 20 has been entered. Claims 1, 3-7, and 9-16 remain pending in the application.
Response to Arguments
Applicant’s arguments, see Pages 6-7, filed October 20, 2025, with respect to the rejections of claims 1, 3-7, and 9-16 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of newly found prior art reference Chang et al. (Patent Publication Number WO 2007/019147 A2), hereafter referred to as Chang.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7, and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choksi et al. (Patent Publication Number US 2016/0126896 A1), hereafter referred to as Choksi, in view of Hu et al. (Patent Publication Number US 2021/0067117 A1), hereafter referred to as Hu, and Chang.
Regarding claim 1, Choksi discloses:
An ultra-high frequency amplifier (Choksi, Fig. 4A) comprising: a first conductor (Fig. 4A, 422) connected to an amplifier input terminal to receive an RF signal applied to the amplifier input terminal (Fig. 4A, see connection between 422 and RFin terminals); a second conductor (Fig. 4A, 424) [inductively coupled] to a first portion of the first conductor (Fig. 4A, see inductive coupling between 424 and 422); a third conductor (Fig. 4A, 426, consider length from ground to tap coupled to transistor 410) separated from the second conductor (Paragraph 28, lines 8-12) and [inductively coupled] to a second portion of the first conductor (Fig. 4A, see inductive coupling between 426 and 422); a transistor (Fig. 4A, 410) including a gate terminal (Fig. 4A, see gate of 410) connected to one end of the second conductor (Fig. 4A, see connection between gate of 410 and 424), a first terminal (Fig. 4A, see source of 410) connected to one end of the third conductor (Fig. 4A, see connection between source of 410 and tap of 426), and a second terminal (Fig. 4A, see drain of 410) connected to an amplifier output terminal (Fig. 4A, see connection between drain of 410 and output nodes 460, 462), wherein the first conductor and the second conductor form a first balun to output a first balance signal based on the RF signal (Paragraph 28, lines 8-12), the first conductor and the third conductor form a second balun to output a second balance signal based on the RF signal (Paragraph 28, lines 8-12), and the first balance signal and the second balance signal output from the first balun and the second balun, respectively, control an amount of drain-source current of the transistor (Paragraph 31, lines 18-24), but fails to disclose [a second conductor] parallel [to a first portion of the first conductor]; [a third conductor] parallel [to a second portion of the first conductor].
However, Hu teaches [a second conductor] parallel [to a first portion of the first conductor] (Hu, Fig. 3, see parallel connection of L2 and L1, see also Paragraph 34); [a third conductor] parallel [to a second portion of the first conductor] (Fig. 3, see parallel connection of L3 and L1, see also Paragraph 34); but fails to teach and an inductor connected between the gate terminal of the transistor and one end of the second conductor and configured so that a resonance frequency of the inductor and a parasitic capacitance of the transistor corresponds to a frequency of the RF signal.
However, Chang teaches and an inductor (Chang, Fig. 7A, 55) connected between the gate terminal of the transistor (Fig. 7A, see connection between 55 and gate of 10) and one end of the second conductor (Fig. 7A, see connection between 55 and 70) and configured so that a resonance frequency of the inductor and a parasitic capacitance of the transistor corresponds to a frequency of the RF signal (Paragraph 31, lines 1-6, see also Paragraph 6, lines 1-2 [the resonant frequency is the ideal frequency for the RF signal, because it maximizes voltage gain]).
Choksi, Hu, and Chang are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Choksi to incorporate the teachings of Hu and Chang to incorporate the inductances of Choksi in parallel to each other, which would have the effect of providing a well-known implementation method to implement the circuit of Choksi, and to include the inductor resonant circuit of Chang in the circuit of Choksi, which would have the effect of increasing the voltage gain of the amplifier of Choksi (Chang, Paragraph 6, lines 1-2).
Regarding claim 3, Choksi further discloses:
further comprising: an input resistor (Choksi, Fig. 4A, 492) having one end connected to the gate terminal of the transistor (Fig. 4A, see connection between 492 and gate of 410) and an opposite end connected to a gate bias terminal (Fig. 4A, see connection between 492 and node on left side of 492) to which a gate input voltage is applied (Paragraph 36, lines 1-4).
Regarding claim 4, Choksi further discloses:
wherein a phase of the first balance signal is opposite to a phase of the second balance signal (Choksi, Paragraph 31, lines 17-24 [Note: negative polarity is equivalent to a 180 degree phase shift]).
Regarding claim 5, Choksi further discloses:
wherein a length of the second conductor is different from a length of the third conductor (Choksi, Fig. 4A, see that length of 424 from ground to 410 gives inductance L2, while length of 426 from ground to 410 gives inductance L3, and that these lengths are different).
Regarding claim 7, Choksi discloses:
An ultra-high frequency amplifier (Choksi, Fig. 4A) comprising: a first conductor (Fig. 4A, 422) connected to an amplifier input terminal to receive an RF signal applied to the amplifier input terminal (Fig. 4A, see connection between 422 and RFin terminals); a second conductor (Fig. 4A, 426, consider length from ground to tap coupled to transistor 410) [inductively coupled] to a first portion of the first conductor (Fig. 4A, see inductive coupling between 426 and 422); a third conductor (Fig. 4A, 424, consider length from ground to tap coupled to transistor 412) separated from the second conductor (Paragraph 28, lines 8-12) and [inductively coupled] to a second portion of the first conductor (Fig. 4A, see inductive coupling between 424 and 422); a fourth conductor (Fig. 4A, 424) [inductively coupled] to a third portion of the first conductor (Fig. 4A, see inductive coupling between 424 and 422); a fifth conductor (Fig. 4A, 426) separated from the fourth conductor (Paragraph 28, lines 8-12) and [inductively coupled] to a fourth portion of the first conductor (Fig. 4A, see inductive coupling between 426 and 422); a first transistor (Fig. 4A, 410) including a first terminal (Fig. 4A, see source of 410) connected to one end of the second conductor (Fig. 4A, see connection between source of 410 and tap of 426), a gate terminal (Fig. 4A, see gate of 410) connected to one end of the fourth conductor (Fig. 4A, see connection between 410 and 424), and a second terminal (Fig. 4A, see drain of 410) connected to an amplifier output terminal (Fig. 4A, see connection between drain of 410 and output nodes 460, 462); a second transistor (Fig. 4A, 412) including a first terminal (Fig. 4A, see source of 412) connected to one end of the third conductor (Fig. 4A, see connection between source of 412 and tap of 424), a gate terminal (Fig. 4A, see gate of 412) connected to one end of the fifth conductor (Fig. 4A, see connection between 412 and 426), and a second terminal (Fig. 4A, see drain of 412) connected to the amplifier output terminal (Fig. 4A, see connection between drain of 412 and output nodes 460, 462), wherein the first conductor and the second conductor form a first balun to output a first balance signal based on the RF signal (Paragraph 28, lines 8-12), the first conductor and the third conductor form a second balun to output a second balance signal based on the RF signal (Paragraph 28, lines 8-12), the first conductor and the fourth conductor form a third balun to output a third balance signal based on the RF signal (Paragraph 28, lines 8-12), the first conductor and the fifth conductor form a fourth balun to output a fourth balance signal based on the RF signal (Paragraph 28, lines 8-12), the first balance signal and the third balance signal output from the first balun and the third balun, respectively, control an amount of drain-source current of the first transistor (Paragraph 31, lines 18-21), and the second balance signal and the fourth balance signal output from the second balun and the fourth balun, respectively, control an amount of drain-source current of the second transistor (Paragraph 31, lines 21-24), but fails to disclose [a second conductor] parallel [to a first portion of the first conductor]; [a third conductor] parallel [to a second portion of the first conductor]; [a fourth conductor] parallel [to a third portion of the first conductor]; [a fifth conductor] parallel [to a fourth portion of the first conductor]; a first inductor connected between the gate terminal of the first transistor and one end of the fourth conductor and configured so that a resonance frequency of the first inductor and a parasitic capacitance of the first transistor corresponds to a frequency of the RF signal; and a second inductor connected between the gate terminal of the second transistor and one end of the fifth conductor and configured so that a resonance frequency of the second inductor and a parasitic capacitance of the second transistor corresponds to the frequency of the RF signal.
However, Hu teaches [a second conductor] parallel [to a first portion of the first conductor] (Hu, Fig. 3, see parallel connection of L2 and L1, see also Paragraph 34); [a third conductor] parallel [to a second portion of the first conductor] (Fig. 3, see parallel connection of L3 and L1, see also Paragraph 34); [a fourth conductor] parallel [to a third portion of the first conductor] (Fig. 3, see parallel connection of L2 and L1, see also Paragraph 34); [a fifth conductor] parallel [to a fourth portion of the first conductor] (Fig. 3, see parallel connection of L3 and L1, see also Paragraph 34), but fails to teach a first inductor connected between the gate terminal of the first transistor and one end of the fourth conductor and configured so that a resonance frequency of the first inductor and a parasitic capacitance of the first transistor corresponds to a frequency of the RF signal; and a second inductor connected between the gate terminal of the second transistor and one end of the fifth conductor and configured so that a resonance frequency of the second inductor and a parasitic capacitance of the second transistor corresponds to the frequency of the RF signal.
However, Chang teaches a first inductor (Chang, Fig. 7A, 55) connected between the gate terminal of the first transistor (Fig. 7A, see connection between 55 and gate of 10) and one end of the fourth conductor (Fig. 7A, see connection between 55 and 70) and configured so that a resonance frequency of the first inductor and a parasitic capacitance of the first transistor corresponds to a frequency of the RF signal (Paragraph 31, lines 1-6, see also Paragraph 6, lines 1-2 [the resonant frequency is the ideal frequency for the RF signal, because it maximizes voltage gain]); and a second inductor (Fig. 7A, 55) connected between the gate terminal of the second transistor (Fig. 7A, see connection between 55 and gate of 10) and one end of the fifth conductor (Fig. 7A, see connection between 55 and 70) and configured so that a resonance frequency of the second inductor and a parasitic capacitance of the second transistor corresponds to the frequency of the RF signal (Paragraph 31, lines 1-6, see also Paragraph 6, lines 1-2 [the resonant frequency is the ideal frequency for the RF signal, because it maximizes voltage gain]).
Choksi, Hu, and Chang are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Choksi to incorporate the teachings of Hu and Chang to incorporate the inductances of Choksi in parallel to each other, which would have the effect of providing a well-known implementation method to implement the circuit of Choksi, and to include the inductor resonant circuit of Chang in the circuit of Choksi, which would have the effect of increasing the voltage gain of the amplifier of Choksi (Chang, Paragraph 6, lines 1-2).
Regarding claim 9, Choksi further discloses:
further comprising: a first input resistor (Choksi, Fig. 4A, 492) having one end connected to the gate terminal of the first transistor (Fig. 4A, see connection between 492 and gate of 410) and an opposite end connected to a gate bias terminal (Fig. 4A, see connection between 492 and node on left side of 492) to which a gate input voltage is applied (Paragraph 36, lines 1-4); and a second input resistor (Fig. 4A, 494) having one end connected to the gate terminal of the second transistor (Fig. 4A, see connection between 494 and gate of 412) and an opposite end connected to the gate bias terminal (Fig. 4A, see connection between 494 and node on right side of 494) to which the gate input voltage is applied (Paragraph 36, lines 1-4).
Regarding claim 10, Choksi further discloses:
wherein a phase of the first balance signal is opposite to a phase of the third balance signal (Choksi, Paragraph 31, lines 17-24 [Note: negative polarity is equivalent to a 180 degree phase shift]).
Regarding claim 11, Choksi further discloses:
wherein a phase of the second balance signal is opposite to a phase of the fourth balance signal (Choksi, Paragraph 31, lines 17-24 [Note: negative polarity is equivalent to a 180 degree phase shift]).
Regarding claim 12, Choksi further discloses:
wherein a length of the second conductor is different from a length of the fourth conductor (Choksi, Fig. 4A, see that length of 426 from ground to 410 gives inductance L3, while length of 424 from ground to 410 gives inductance L2, and that these lengths are different).
Regarding claim 13, Choksi further discloses:
wherein a length of the third conductor is different from a length of the fifth conductor (Choksi, Fig. 4A, see that length of 424 from ground to 412 gives inductance L3, while length of 426 from ground to 412 gives inductance L2, and that these lengths are different).
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choksi in view of Hu and Chang as applied to claims 1 and 7, respectively, above, and further in view of Huang et al. (Patent Publication Number CN 112,671,346 A), hereafter referred to as Huang.
Regarding claim 6, Choksi further discloses:
wherein one end of the second conductor is connected to the gate terminal of the transistor (Choksi, Fig. 4A, see connection between 424 and gate of 410), and wherein the ultra-high frequency amplifier further comprises an input resistor (Fig. 4A, 492) having an opposite end connected to a gate bias terminal (Fig. 4A, see connection between 492 and node on left side of 492) to which a gate input voltage is applied (Paragraph 36, lines 1-4), but fails to disclose and one end [of the input resistor] connected to an opposite end of the second conductor.
However, Huang teaches and one end [of the input resistor] connected to an opposite end of the second conductor (Huang, Fig. 8, see connection between Rb and tap of B2 in modified Fig. 8 below).
Choksi, Hu, Chang, and Huang are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Choksi to incorporate the teachings of Huang to move the bias resistor of Choksi to be located between the secondary windings of the balun of Choksi and ground, which would have the effect of biasing the signals output from the balun of Choksi to allow for making appropriate adjustments to the signals.
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Regarding claim 14, Choksi further discloses:
wherein one end of the fourth conductor is connected to the gate terminal of the first transistor (Choksi, Fig. 4A, see connection between 424 and gate of 410), wherein one end of the fifth conductor is connected to the gate terminal of the second transistor (Fig. 4A, see connection between 426 and gate of 412), and wherein the ultra-high frequency amplifier further comprises a first input resistor (Fig. 4A, 492) having an opposite end connected to a gate bias terminal (Fig. 4A, see connection between 492 and node on left side of 492) to which a gate input voltage is applied (Paragraph 36, lines 1-4), and a second input resistor (Fig. 4A, 494) having an opposite end connected to the gate bias terminal (Fig. 4A, see connection between 494 and node on right side of 494) to which the gate input voltage is applied (Paragraph 36, lines 1-4), but fails to disclose and one end [of the first input resistor] connected to an opposite end of the fourth conductor and one end [of the second input resistor] connected to an opposite end of the fifth conductor.
However, Huang teaches and one end [of the first input resistor] connected to an opposite end of the fourth conductor (Huang, Fig. 8, see connection between Rb and tap of B2 in modified Fig. 8 above) and one end [of the second input resistor] connected to an opposite end of the fifth conductor (Fig. 8, see connection between Rb and tap of B2 in modified Fig. 8 above).
Choksi, Hu, Chang, and Huang are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Choksi to incorporate the teachings of Huang to move the bias resistors of Choksi to be located between the secondary windings of the balun of Choksi and ground, which would have the effect of biasing the signals output from the balun of Choksi to allow for making appropriate adjustments to the signals.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Choksi in view of Hu and Chang as applied to claims 7 and 1, respectively, above, and further in view of Li.
Regarding claim 15, Choksi further discloses:
wherein a first end of the first conductor is connected to the amplifier input terminal (Choksi, Fig. 4A, see connection between L1 and input 402), but fails to disclose and wherein a second end of the first conductor opposite the first end is open whenever the first end is receiving the RF signal.
However, Li teaches and wherein a second end of the first conductor opposite the first end is open whenever the first end is receiving the RF signal (Li, Fig. 1, see that opposite side of primary conductor “Ind” from the single input “Input” is an open circuit “OC” in modified Fig. 1 below).
Choksi, Hu, Chang, and Li are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Choksi to incorporate the teachings of Li to make the opposite end of the first conductor of Choksi from the input signal an open circuit, which would have the effect of improving input matching and efficiency (Li, Paragraph 26, lines 1-3).
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Regarding claim 16, Choksi further discloses:
wherein a first end of the first conductor is connected to the amplifier input terminal (Choksi, Fig. 4A, see connection between L1 and input 402), but fails to disclose and wherein a second end of the first conductor opposite the first end is open whenever the first end is receiving the RF signal.
However, Li teaches and wherein a second end of the first conductor opposite the first end is open whenever the first end is receiving the RF signal (Li, Fig. 1, see that opposite side of primary conductor “Ind” from the single input “Input” is an open circuit “OC” in modified Fig. 1 above).
Choksi, Hu, Chang, and Li are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Choksi to incorporate the teachings of Li to make the opposite end of the first conductor of Choksi from the input signal an open circuit, which would have the effect of improving input matching and efficiency (Li, Paragraph 26, lines 1-3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kong et al. (Patent Publication Number US 2017/0302234 A1) discloses (Fig. 3) an amplifier with two input baluns coupled between both gates and sources of amplifier transistors.
Bagga et al. (Patent Publication Number CN 109,661,774 A) discloses (Fig. 4) an amplifier with two input baluns that provide opposite phase signals to the gate and source of an amplifier transistor.
Cao et al. (Patent Number CN 208,797,908 U) discloses (Fig. 4A) an amplifier with a bias resistor coupled to an opposite side of a secondary input balun winding relative to the amplifier transistor.
Cai et al. (Patent Publication Number US 2015/0288334 A1) discloses (Fig. 2) a differential amplifier with an LC resonator that resonates with a transistor parasitic capacitance at the RF signal frequency.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843