DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Claims 1-3, 7-10, 14-16, 20-22 are entitled to the benefit of the prior-filed provisional application 63/032602. The effective filing date of the corresponding claims 5/30/2020.
Claims 4-6, 11-13, 17-19 are not entitled to the benefit of the prior-filed provisional application 63/032602, but are entitled to the benefit of the prior-filed application PCT/US2020/053055. The provisional application appears silent to a second normalization unit operatively coupled to a second FP execution pipeline. The effective filing date of the corresponding claims is 9/28/2020.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
first normalization unit in claims 1, 8, 16;
second normalization unit in claims 4, 11, 17; and
denormal unit in claims 7, 14, 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
As to claims 1, 8, 16’s first normalization unit, the examiner interprets the means plus function limitation to the corresponding structure: denormal normalizing unit comprising an execution stage and register as disclosed in Fig. 4 element 415, [0070]-[0071] of the applicant’s specification.
As to claims 4, 11, 17’s second normalization unit, the examiner interprets the means plus function limitation to the corresponding structure: denormal normalizing unit comprising an execution stage and register as disclosed in Fig. 4 element 417, [0070]-[0071]of the applicant’s specification.
As to claims 7, 14, 20’s denormal unit, no corresponding structure is found in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 14, 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim limitation denormal unit invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Paragraph [0073] in applicant’s specification only describes the functions of the denormalize unit. However, the written description fails to provide an adequate description of the structure, materials, or acts to perform the claimed functions of these limitations
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitation “denormal unit” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Paragraph [0073] in applicant’s specification only describes the functions of the denormalize unit. However, the disclosure is devoid of any structure that performs the function in the claim. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, 14-16, 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. (US 5267186 A, hereinafter “Gupta”) in view of Hinds et al. (US 5339266 A, hereinafter “Hinds”).
As per claim 1, Gupta teaches A floating-point (FP) arithmetic unit comprising: a first FP execution pipeline operatively coupled to a register file and an instruction dispatch (Gupta: Fig. 2 elements 20, 22, or 26), the first FP execution pipeline configured to: perform a first FP operation on a first FP operand provided by the register file, the first FP execution pipeline comprising a first plurality of execution units (Gupta: col 7 lines 10-16);
and a first normalization unit operatively coupled to the first FP execution pipeline, and the instruction dispatch, the first normalization unit configured to: normalize the first FP operand provided by the register file (Gupta: col 9 lines 48-50),
in response to detecting that the first FP operand is a denormal: assert a first FP execution pipeline busy flag to stall the instruction dispatch of a first subsequent FP operation (Gupta: col 9 line 62 – col 10 line 6; the normalized operand wraps back to the corresponding execution unit),
and provide the normalized first FP operand to the first FP execution pipeline, the first FP operation and the first subsequent FP operation being of a first FP operation type (Gupta: col 10 lines 6-20).
However, while Gupta discloses a normalizing unit parallel to the multiply and divide units, Gupta does not explicitly disclose the normalizing unit operating in parallel to all arithmetic units. Thus, Gupta does not teach and a first normalization unit operatively coupled to the register file, wherein the first normalization unit is configured to: operate in parallel with the first FP execution pipeline,
Hinds teaches and a first normalization unit operatively coupled to the register file (Hinds: Fig. 1 element 24; coupled to the operand registers), wherein the first normalization unit is configured to: operate in parallel with the first FP execution pipeline (Hinds: col 5 lines 29-32),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the renormalizing unit of Gupta (Fig. 2 element 28) with the special floating-point circuit of Hinds (Fig. 2); such that the renormalizing unit may also operate in parallel with the add unit. One would have been motivated to combine these references because both references disclose handling denormal numbers, and performing special floating point operations in parallel with floating point math units is speed efficient (Hinds: col 2 lines 38-40).
As per claim 2, Gupta/Hinds further teaches The FP arithmetic unit of claim 1, wherein the first FP execution pipeline is further configured to: perform a second FP operation on a second FP operand provided by the register file, wherein the first normalization unit is further configured to: normalize the second FP operand provided by the register file, and in response to detecting that the second FP operand is normal, discard the normalized second FP operand (Gupta: col 7 line 56- col 8 line 6; normalization of operands is discarded because the arithmetic result is propagated at the round unit instead of the normalization result; col 7 lines 45-49).
As per claim 3, Gupta/Hinds further teaches The FP arithmetic unit of claim 1, wherein the FP execution pipeline comprises one of a FP addition execution pipeline, a FP multiplication pipeline, an FP division pipeline, an FP square-root or generalized root pipeline, an FP exponential pipeline, an FP power pipeline, or an FP logarithm pipeline, or any other operation or instruction on a floating-point operand (Gupta: Fig. 2 elements 20, 22, 26; col 7 lines 10-17).
As per claim 7, Gupta/Hinds further teaches The FP arithmetic unit of claim 1, further comprising a denormal unit operatively coupled to the first FP execution pipeline, the denormal unit configured to: convert a fifth FP operand outputted by the first FP execution pipeline into a denormal (Gupta: Fig. 2 element 24; col 11 lines 29-50).
As per claims 8-10, 14, the claims are directed to a system that implements the same or similar features as the FP arithmetic unit of claims 1-3, 7, respectively, and is therefore rejected for at least the same reasons therein.
As per claims 15-16, 20-21, the claims are directed to a method that implements the same or similar features as the FP arithmetic unit of claims 1-2, 7, 3, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 22, Gupta/Hinds further teaches The method of claim 15, the first subsequent FP operation and the first FP operation are or the same FP operation type (Gupta: col 9 line 62 – col 10 line 12).
Allowable Subject Matter
Claims 4-6,11-13, 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 4, 11, 17, the prior art of record does not teach or suggest a combination as claimed including: a second normalization unit operatively coupled to the register file, the second FP execution pipeline, and the instruction dispatch, the second normalization unit configured to: normalize the third FP operand provided by the register file, wherein the second normalization unit is configured to: operate in parallel with the second FP execution pipeline, in response to detecting that the third FP operand is a denormal: assert a second FP execution pipeline busy flag to stall the instruction dispatch of a second subsequent FP operation, and provide the normalized third FP operand to the second FP execution pipeline, the third FP operation and the second subsequent FP operation being of a second FP operation type.
Gupta discloses utilizing normalization circuitry for floating-point addition/subtraction to also normalize operands to minimize required normalization circuitry (col 4 lines 42-49). Gupta does not suggest additional normalization circuitry to further enable parallel floating-point instruction operation. Therefore, Gupta does not teach or suggest a combination as claimed including the limitations identified above.
Hinds discloses a special floating-point circuit operating in parallel with all floating-point arithmetic units (Fig. 1 element 24). Hinds does not suggest additional special floating-point circuits to further enable parallel floating-point instruction operation. Therefore, Hinds does not teach or suggest a combination as claimed including the limitations identified above.
Muff et al. (US 20140164465 A1, hereinafter “Muff” provided in IDS filed 9/8/2022) discloses parallel processing lanes which may normalize denormal operands to then be processed by a dot product adder (Fig. 5; [0059]). Muff does not suggest a second normalization lane for a second FP operation type. Therefore, Muff does not teach or suggest a combination as claimed including the limitations identified above.
Oberman et al. (US 6487653 B1, hereinafter “Oberman”) discloses adding a stage to the floating-point operation pipeline when denormal operands are detected (col 3 lines 17-35). Oberman does not suggest additional denormal operand detection circuitry to further enable parallel floating-point instruction operation. Therefore, Oberman does not teach or suggest a combination as claimed including the limitations identified above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182