DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn.
Prior Art Rejections
Applicant's arguments filed 6/18/2026 have been fully considered and are not persuasive.
The Examiner notes in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant asserts in Gupta, the multiply/divide unit cannot begin executing on the operand until normalization through the add unit and renormalizing unit is complete and is therefore a gate that the operand must pass through rather than operating in parallel.
Examiner agrees Gupta does not disclose a normalization unit configured to “operate in parallel with the first FP execution pipeline”. However, the rejection is the combination of Gupta and Hinds and not by either reference alone.
Applicant asserts Hinds does not cure the deficiencies of Gupta because none of steps 102, 106, 110, 112, and 114 in Hinds is a normalizing step, and Hinds’ special floating point circuit detects special operands and substitutes a correct result onto the output bus but does not normalize an operand and provide the normalized operand back to the FP execution pipeline.
Examiner respectfully disagrees. Hinds teaches a special floating point circuit operating in parallel with floating point operation units (col 5 lines 29-32), wherein a special floating point operand type includes denomalized and non-normalized floating point numbers (col 4 lines 36-29). Therefore, it would have been obvious for one of ordinary skill in the art to modify Gupta’s renormalizing unit with Hinds such that renormalizing unit operates in parallel with floating point operating units because both references disclose units handling denormal numbers, and Hinds discusses performing the special floating point operations in parallel with floating point math units is speed efficient (Hinds: col 2 lines 38-40).
Priority
Claims 1-3, 8-10, 15-16, 21-22 are entitled to the benefit of the prior-filed provisional application 63/032602. The effective filing date of the corresponding claims 5/30/2020.
Claims 4-6, 11-13, 17-19 are not entitled to the benefit of the prior-filed provisional application 63/032602, but are entitled to the benefit of the prior-filed application PCT/US2020/053055. The provisional application appears to be silent to a second normalization unit operatively coupled to a second FP execution pipeline. The effective filing date of the corresponding claims is 9/28/2020.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, 15-16, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. (US 5267186 A, hereinafter “Gupta”) in view of Hinds et al. (US 5339266 A, hereinafter “Hinds”).
As per claim 1, Gupta teaches A floating-point (FP) arithmetic unit comprising: a first FP execution pipeline operatively coupled to a register file and an instruction dispatch (Gupta: Fig. 2 elements 20, 22, or 26), the first FP execution pipeline configured to: perform a first FP operation on a first FP operand provided by the register file, the first FP execution pipeline comprising a first plurality of execution units (Gupta: col 7 lines 10-16);
and a first normalization circuit operatively coupled to the first FP execution pipeline, and the instruction dispatch, the first normalization circuit configured to: normalize the first FP operand provided by the register file (Gupta: col 9 lines 48-50),
wherein the first normalization unit is configured to: in response to detecting that the first FP operand is a denormal: assert a first FP execution pipeline busy flag to stall the instruction dispatch of a first subsequent FP operation (Gupta: col 9 line 62 – col 10 line 6; the normalized operand wraps back to the corresponding execution unit),
and provide the normalized first FP operand to the first FP execution pipeline, the first FP operation and the first subsequent FP operation being of a first FP operation type (Gupta: col 10 lines 6-20).
However, while Gupta discloses a normalizing unit parallel to the multiply and divide units, Gupta does not explicitly disclose the normalizing unit operating in parallel to all arithmetic units. Thus, Gupta does not teach and a first normalization circuit operatively coupled to the register file, the first normalization circuit configured to: operate in parallel with the first FP execution pipeline while the first FP execution pipeline performs the first FP operation on the first FP operand
Hinds teaches and a first normalization unit operatively coupled to the register file (Hinds: Fig. 1 element 24; coupled to the operand registers), the first normalization circuit configured to: operate in parallel with the first FP execution pipeline while the first FP execution pipeline performs the first FP operation on the first FP operand (Hinds: col 5 lines 29-32),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the renormalizing unit of Gupta (Fig. 2 element 28) with the special floating-point circuit of Hinds (Fig. 2); such that the renormalizing unit may also operate in parallel with the add unit. One would have been motivated to combine these references because both references disclose handling denormal numbers, and performing special floating point operations in parallel with floating point math units is speed efficient (Hinds: col 2 lines 38-40).
As per claim 2, Gupta/Hinds further teaches The FP arithmetic unit of claim 1, wherein the first FP execution pipeline is further configured to: perform a second FP operation on a second FP operand provided by the register file, wherein the first normalization circuit is further configured to: normalize the second FP operand provided by the register file, and in response to detecting that the second FP operand is normal, discard the normalized second FP operand (Gupta: col 7 line 56- col 8 line 6; normalization of operands is discarded because the arithmetic result is propagated at the round unit instead of the normalization result; col 7 lines 45-49).
As per claim 3, Gupta/Hinds further teaches The FP arithmetic unit of claim 1, wherein the FP execution pipeline comprises one of a FP addition execution pipeline, a FP multiplication pipeline, an FP division pipeline, an FP square-root or generalized root pipeline, an FP exponential pipeline, an FP power pipeline, an FP logarithm pipeline, or any other operation or instruction on a floating-point operand (Gupta: Fig. 2 elements 20, 22, 26; col 7 lines 10-17).
As per claims 8-10, the claims are directed to a system that implements the same or similar features as the FP arithmetic unit of claims 1-3, respectively, and is therefore rejected for at least the same reasons therein.
As per claims 15-16, 21, the claims are directed to a method that implements the same or similar features as the FP arithmetic unit of claims 1-3, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 22, Gupta/Hinds further teaches The method of claim 15, the first subsequent FP operation and the first FP operation are or the same FP operation type (Gupta: col 9 line 62 – col 10 line 12).
Allowable Subject Matter
Claims 4-6, 11-13, 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the reasons stated in the Non-Final Office Action mailed 3/19/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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