DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to amendment filed on 07/16/2026. Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chalamalsetti - US 2020042287.
The apparatus claim 12 is addressed before the method claim 1.
Regarding claim 12, Chalamalsetti teaches a device (Chalamalsetti figure 1A integrated circuit 100 [i.e., a device]), comprising:
a memory cell array (Chalamalsetti figure 1A, each core includes an array of memristive cells [i.e., a memory cell array]); and a logic circuit, configured to:
program, in a first mode, threshold voltages of first memory cells in the memory cell array in an integrated circuit device to store first weight matrices representative of a first artificial neural network (Chalamalsetti [0036] describes a programming operation [i.e., a first mode], the memristors of the array is programmed to store weight matrices of a neural network using programming voltages . Figures 2, 4B, [0044], [0052] describes the dynamically precision selection for different neural networks configured with different precision levels. Thus, a control unit [i.e., a logic circuit] would program threshold voltages for memory cells having a second precision 210 [i.e., a first memory cells] in the memory array as illustrated in figure 1A in an integrated circuit device 100 to store first weight matrices of a neural network corresponding to such precision [i.e., a first artificial neural network]); and program, in the first mode, threshold voltages of second memory cells in the memory cell array to store second weight matrices representative of a second artificial neural network (Chalamalsetti, as illustrated in figure 4B different neural networks can be selected for different level precision. Thus, based on a next input stream, the control unit also program threshold voltages for memory cells having a first precision 205 [i.e., a second memory cells] in the memory array as illustrated in figure 1A to store second weight matrices of a neural network corresponding to such precision [i.e., a second artificial neural network]), wherein a count of the first memory cells is larger than a count of the second memory cell (Chalamalsetti figure 2 [0040] illustrates different precision type, where using larger area of the crossbar matrix allows for high precision. Thus, the count of memory cells having second precision 210 is larger than memory cells having first precision 205).
Claim 1 recite method claims that would be practiced by the apparatus claim 12. Thus, it is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chalamalsetti in view of Cantin - US 20190065943.
Regarding claim 18, Chalamalsetti teaches an apparatus (Chalamalsetti figure 1A teaches an integrated circuit 100), comprising: an integrated circuit die having a memory cell array (Chalamalsetti figure 1A [0026] illustrates an array of memory cells DPE 160 implemented on an integrated circuit [i.e., an integrated circuit die having a memory cell array] ); and an integrated circuit die having a logic circuit (Chalamalsetti figure 1A [0044] describes a control circuitry [i.e., an integrated circuit die having a logic circuit]); wherein the apparatus is configured to: program, in a first mode, threshold voltages of first memory cells in a first subset to store first weight matrices representative of a first artificial neural network (Chalamalsetti [0036] describes a programming operation [i.e., a first mode], the memristors of the array is programmed to store weight matrices of a neural network using programming voltages. Figures 2, 4B, [0044], [0052] describes the dynamically precision selection for different neural networks configured with different precision levels. Thus, threshold voltages are programmed for memory cells having a second precision 210 [i.e., a first memory cells in a first subset] in the memory array as illustrated in figure 1A in an integrated circuit device 100 to store first weight matrices of a neural network corresponding to such precision [i.e., a first artificial neural network]).
Chalamalsetti does not teach a memory cell array configured in a plurality of layers having a first subset and a second subset, the first subset and the second subset being mutually exclusive. However, Cantin teaches a memory cell array configured in a plurality of layers having a first subset and a second subset, the first subset and the second subset being mutually exclusive (Cantin figures 1-2 illustrate a crossbar array stack 145 [i.e., a memory cell array] configured in a plurality of layers having a first crossbar array 210 and a second crossbar array 230 [i.e., first subset and second subset] mutually exclusive).
It would have been obvious for to modify the plurality of crossbar arrays as illustrated in Chalamalsetti figure 1 to be the crossbar array stack 145 as taught in Cantin. This modification would have been obvious because both references teach crossbar array to perform matrix multiplication operation. Furthermore, as recognized by Cantin [0042], stacking crossbar array is more efficient as driving a Through-Silicon-Via (TSV) requires less power than driving long chip wires and stacking the crossbar array also reduces the hardware area comparing to the configuration as disclosed in Chalamalsetti.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
