Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application. Claims 17-18 are amended by applicant’s amendment filed 9 April 2026.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 9 April 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Moser et al. (U.S. Patent 11,861,181) in view of Jia, Hongyang, et al. (“Scalable and programmable neural network inference accelerator based on in-memory computing,” IEEE Journal of Solid-State Circuits 57.1 (2021): 198-211; hereinafter “Jia”).
Regarding Claim 17, Moser teaches an apparatus (fig. 1; col. 2, line 55 – col. 3, line 9), comprising:
a plurality of integrated circuit devices (fig. 1, memories 160a, 160b, and 160c; col. 2, line 55 – col. 3, line 9), each having:
a memory cell array having memory cells programmed to store a redundant copy of data (fig. 1, memory chips 150a, 150b, and 150c; col. 2, line 55 – col. 3, line 9—the three memories store redundant data to identify errors); and
a logic circuit coupled to the memory cell array (fig. 1, memory controllers 130a, 130b, and 130c; col. 2, line 55 – col. 3, line 9);
a microprocessor (figs. 1, 2, and 4 Microprocessor 400 inside microcontroller 230, which is inside TMR System 120; col. 4, lines 33-46); and
an interconnect coupled between the microprocessor and the integrated circuit devices (fig. 2, interconnects shown in the TMR System 120 between Microcontroller 230 and Memory Controllers 130; col. 3, lines 16-32);
wherein the microprocessor is configured to compare a plurality of results each using the memory cells programmed to store the redundant copy of the data, and select an output result from the plurality of results (Moser, col. 3, line 41 – col. 4, line 4—the microprocessor in the TMR system compares data values in the memories and selects an output by majority vote).
Moser does not specifically teach that the data are weight matrices of an artificial neural network; that the logic circuit is to perform operations of multiplication and accumulation using the memory cells; and that the plurality of results are generated by the plurality of integrated circuit devices.
However, Jia teaches:
a memory cell array having memory cells programmed to store weight matrices of an artificial neural network (fig. 1; sections I and II. B—a memory cell array stores matrix weight elements for in-memory matrix-vector multiplies. See also section III and fig. 3);
a logic circuit coupled to the memory cell array to perform operations of multiplication and accumulation using the memory cells (sections IV. A and D; figs. 7 and 9—logic coupled to the memory cell array forms the datapath that performs multiply-accumulate operations using the memory cells); and
a plurality of results generated by a plurality of integrated circuit devices each using the memory cells programmed to store weight matrices of the artificial neural network (section III and fig. 3—results are generated for multiply-accumulate operations using the memory cells that store weight matrices of an artificial neural network).
All of the claimed elements were known in Moser and Jia and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the weight matrices and logic performing multiplication and accumulation operations of Jia with the memory cell arrays, logic circuits, and redundant copy of data of Moser to yield the predictable result of a plurality of integrated circuit devices, each having: a memory cell array having memory cells programmed to store a redundant copy of weight matrices of an artificial neural network; and a logic circuit coupled to the memory cell array to perform operations of multiplication and accumulation using the memory cells; wherein the microprocessor is configured to compare a plurality of results, generated by the plurality of integrated circuit devices each using the memory cells programmed to store the redundant copy of the weight matrices of the artificial neural network, and select an output result from the plurality of results. One would be motivated to make this combination for the purpose of accelerating computations and reducing memory accessing for matrix-vector computations (Jia, Abstract).
Regarding Claim 18, Moser/Jia teaches wherein each respective memory cell among the memory cells has a threshold voltage programmed to cause the respective memory cell to output: a predetermined amount of current to represent a weight of one stored in the respective memory cell when the respective memory cell is read using a predetermined read voltage; or a negligible amount of current to represent a weight of zero stored in the respective memory cell when the respective memory cell is read using the predetermined read voltage (Jia, section III. A describes analog charge accumulation, and section VI. A describes voltages applied to an ADC input to access the memories. Figs. 7 and 9, among others, show circuit diagrams of the memory cells and logic circuits. The examiner takes official notice that the threshold voltage, currents, and read process of the present claim are well-known techniques for memories like those taught by Jia).
Regarding Claim 19, Moser/Jia teaches wherein the memory cell array are configured as a plurality of layers, each of the layers having a plurality of columns of memory cells having output currents connected to a plurality of bitlines respectively, each of the layers having rows of memory cells connected to wordlines respectively to receive applied voltages (Jia, section III and fig. 3—each of the CIMUs {compute in memory units} can be considered a layer, and each layer contains a memory cell array having a plurality of rows and columns. The memory cell arrays are further described in section IV and fig. 7);
wherein each of the layers has wordlines selected according to a column of input bits to have the predetermined read voltage applied concurrently for bitwise multiplication to output currents into the bitlines; and wherein each of the integrated circuit devices further comprises analog to digital converters configured to digitize summed currents in the bitlines as multiple of the predetermined amount of current (Jia, fig. IV. A and fig. 7).
Regarding Claim 20, Moser/Jia teaches wherein the logic circuit includes a field programmable gate array configured to perform a portion of computations of the artificial neural network (Moser, col. 8, line 48 – col. 9, line 3—the logic circuit can include an FPGA {field programmable gate array}).
Allowable Subject Matter
Claims 1-16 are allowed. As described in the previous office actions, none of the prior art of record teaches all of the limitations of independent claims 1 and 11. Jia teaches a memory cell array that has a plurality of regiouns operable in parallel to perform operations of multiplication and accumulation, but does not teach the redundant operations of the present claims.
Additional prior art teaches others aspects of the claims, but does not teach all of the limitations of claims 1 and 11. Amirsoleimani, Amirali, et al. (“In‐memory vector‐matrix multiplication in monolithic complementary metal–oxide–semiconductor‐memristor integrated circuits: design choices, challenges, and perspectives,” Advanced Intelligent Systems 2.11 (2020): 2000115) teaches a memristor-based memory array device that performs multiply-accumulate operations, and describes read/write voltages and currents and analog to digital conversion, and also teaches a monolithic architecture with a plurality of layers of memory cells; but does not teach redundant operations of multiplication and accumulation. Khaddam-Aljameh, Riduan, et al. (“An SRAM-based multibit in-memory matrix-vector multiplier with a precision that scales linearly in area, time, and power,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29.2 (2020): 372-385) teaches in-memory computing with an SRAM array that performs multiply-accumulate operations in an analog domain. And Wang, Yin, et al. (“An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations,” Nature communications 12.1 (2021): 3347) teaches an in-memory computing architecture that performs multiply-accumulate operations on weight matrices for neural networks, but it too does not teach redundant operations.
Response to Arguments
Applicant’s arguments with respect to claims 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant argued that Sebastian, Abu, et al. (“Memory devices and applications for in-memory computing,” Nature nanotechnology 15.7 (2020): 529-544) does not teach many of the limitations of the present claims. In place of Sebastian, the examiner now relies on Jia, in combination with Moser, as detailed above. The applicant’s remarks filed 9 April 2026 also discuss several chip bonding technologies, but the examiner notes that none of these are recited by the present claims. The applicant also asserts “Applicant's invention as directed to redundant computations performed using multiplication and accumulation circuits, is captured via the claimed elements of claims 17 & 18 as set forth below, by way of example . . .” However, as the examiner has explained previously, claims 17-20 do not recite redundant computations. They only recite redundant copies of data (weight matrices). As detailed above, Moser teaches redundant copies of data, and Jia teaches stored data that are weight matrices of an artificial neural network. The combination therefore teaches all of the limitations of claims 17 and 18, as detailed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAL W SCHNEE whose telephone number is (571) 270-1918. The examiner can normally be reached M-F 7:30 a.m. - 6:00 p.m.
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/HAL SCHNEE/Primary Examiner, Art Unit 2129
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